mdreloc.c revision 1.2
1 /* $NetBSD: mdreloc.c,v 1.2 2000/07/18 22:33:56 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Eduardo Horvath. 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <errno.h> 41 #include <stdio.h> 42 #include <stdlib.h> 43 #include <string.h> 44 #include <unistd.h> 45 #include <sys/stat.h> 46 47 #include "rtldenv.h" 48 #include "debug.h" 49 #include "rtld.h" 50 51 /* 52 * The following table holds for each relocation type: 53 * - the width in bits of the memory location the relocation 54 * applies to (not currently used) 55 * - the number of bits the relocation value must be shifted to the 56 * right (i.e. discard least significant bits) to fit into 57 * the appropriate field in the instruction word. 58 * - flags indicating whether 59 * * the relocation involves a symbol 60 * * the relocation is relative to the current position 61 * * the relocation is for a GOT entry 62 * * the relocation is relative to the load address 63 * 64 */ 65 #define _RF_S 0x80000000 /* Resolve symbol */ 66 #define _RF_A 0x40000000 /* Use addend */ 67 #define _RF_P 0x20000000 /* Location relative */ 68 #define _RF_G 0x10000000 /* GOT offset */ 69 #define _RF_B 0x08000000 /* Load address relative */ 70 #define _RF_U 0x04000000 /* Unaligned */ 71 #define _RF_SZ(s) (((s) & 0xff) << 8) /* memory target size */ 72 #define _RF_RS(s) ( (s) & 0xff) /* right shift */ 73 static int reloc_target_flags[] = { 74 0, /* NONE */ 75 _RF_S|_RF_A| _RF_SZ(8) | _RF_RS(0), /* RELOC_8 */ 76 _RF_S|_RF_A| _RF_SZ(16) | _RF_RS(0), /* RELOC_16 */ 77 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* RELOC_32 */ 78 _RF_S|_RF_A|_RF_P| _RF_SZ(8) | _RF_RS(0), /* DISP_8 */ 79 _RF_S|_RF_A|_RF_P| _RF_SZ(16) | _RF_RS(0), /* DISP_16 */ 80 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* DISP_32 */ 81 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_30 */ 82 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_22 */ 83 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HI22 */ 84 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 22 */ 85 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 13 */ 86 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LO10 */ 87 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT10 */ 88 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT13 */ 89 _RF_G| _RF_SZ(32) | _RF_RS(10), /* GOT22 */ 90 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PC10 */ 91 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC22 */ 92 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WPLT30 */ 93 _RF_SZ(32) | _RF_RS(0), /* COPY */ 94 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* GLOB_DAT */ 95 _RF_SZ(32) | _RF_RS(0), /* JMP_SLOT */ 96 _RF_A| _RF_B| _RF_SZ(64) | _RF_RS(0), /* RELATIVE */ 97 _RF_S|_RF_A| _RF_U| _RF_SZ(32) | _RF_RS(0), /* UA_32 */ 98 99 _RF_A| _RF_SZ(32) | _RF_RS(0), /* PLT32 */ 100 _RF_A| _RF_SZ(32) | _RF_RS(10), /* HIPLT22 */ 101 _RF_A| _RF_SZ(32) | _RF_RS(0), /* LOPLT10 */ 102 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT32 */ 103 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PCPLT22 */ 104 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT10 */ 105 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 10 */ 106 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 11 */ 107 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* 64 */ 108 _RF_S|_RF_A|/*extra*/ _RF_SZ(32) | _RF_RS(0), /* OLO10 */ 109 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(42), /* HH22 */ 110 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(32), /* HM10 */ 111 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* LM22 */ 112 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(42), /* PC_HH22 */ 113 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(32), /* PC_HM10 */ 114 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC_LM22 */ 115 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP16 */ 116 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP19 */ 117 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* GLOB_JMP */ 118 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 7 */ 119 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 5 */ 120 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 6 */ 121 _RF_S|_RF_A|_RF_P| _RF_SZ(64) | _RF_RS(0), /* DISP64 */ 122 _RF_A| _RF_SZ(64) | _RF_RS(0), /* PLT64 */ 123 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HIX22 */ 124 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LOX10 */ 125 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(22), /* H44 */ 126 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(12), /* M44 */ 127 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* L44 */ 128 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* REGISTER */ 129 _RF_S|_RF_A| _RF_U| _RF_SZ(64) | _RF_RS(0), /* UA64 */ 130 _RF_S|_RF_A| _RF_U| _RF_SZ(16) | _RF_RS(0), /* UA16 */ 131 }; 132 133 #ifdef RTLD_DEBUG_RELOC 134 static const char *reloc_names[] = { 135 "NONE", "RELOC_8", "RELOC_16", "RELOC_32", "DISP_8", 136 "DISP_16", "DISP_32", "WDISP_30", "WDISP_22", "HI22", 137 "22", "13", "LO10", "GOT10", "GOT13", 138 "GOT22", "PC10", "PC22", "WPLT30", "COPY", 139 "GLOB_DAT", "JMP_SLOT", "RELATIVE", "UA_32", "PLT32", 140 "HIPLT22", "LOPLT10", "LOPLT10", "PCPLT22", "PCPLT32", 141 "10", "11", "64", "OLO10", "HH22", 142 "HM10", "LM22", "PC_HH22", "PC_HM10", "PC_LM22", 143 "WDISP16", "WDISP19", "GLOB_JMP", "7", "5", "6", 144 "DISP64", "PLT64", "HIX22", "LOX10", "H44", "M44", 145 "L44", "REGISTER", "UA64", "UA16" 146 }; 147 #endif 148 149 #define RELOC_RESOLVE_SYMBOL(t) ((reloc_target_flags[t] & _RF_S) != 0) 150 #define RELOC_PC_RELATIVE(t) ((reloc_target_flags[t] & _RF_P) != 0) 151 #define RELOC_BASE_RELATIVE(t) ((reloc_target_flags[t] & _RF_B) != 0) 152 #define RELOC_UNALIGNED(t) ((reloc_target_flags[t] & _RF_U) != 0) 153 #define RELOC_USE_ADDEND(t) ((reloc_target_flags[t] & _RF_A) != 0) 154 #define RELOC_TARGET_SIZE(t) ((reloc_target_flags[t] >> 8) & 0xff) 155 #define RELOC_VALUE_RIGHTSHIFT(t) (reloc_target_flags[t] & 0xff) 156 157 static long reloc_target_bitmask[] = { 158 #define _BM(x) (~(-(1ULL << (x)))) 159 0, /* NONE */ 160 _BM(8), _BM(16), _BM(32), /* RELOC_8, _16, _32 */ 161 _BM(8), _BM(16), _BM(32), /* DISP8, DISP16, DISP32 */ 162 _BM(30), _BM(22), /* WDISP30, WDISP22 */ 163 _BM(22), _BM(22), /* HI22, _22 */ 164 _BM(13), _BM(10), /* RELOC_13, _LO10 */ 165 _BM(10), _BM(13), _BM(22), /* GOT10, GOT13, GOT22 */ 166 _BM(10), _BM(22), /* _PC10, _PC22 */ 167 _BM(30), 0, /* _WPLT30, _COPY */ 168 _BM(32), _BM(32), _BM(32), /* _GLOB_DAT, JMP_SLOT, _RELATIVE */ 169 _BM(32), _BM(32), /* _UA32, PLT32 */ 170 _BM(22), _BM(10), /* _HIPLT22, LOPLT10 */ 171 _BM(32), _BM(22), _BM(10), /* _PCPLT32, _PCPLT22, _PCPLT10 */ 172 _BM(10), _BM(11), -1, /* _10, _11, _64 */ 173 _BM(10), _BM(22), /* _OLO10, _HH22 */ 174 _BM(10), _BM(22), /* _HM10, _LM22 */ 175 _BM(22), _BM(10), _BM(22), /* _PC_HH22, _PC_HM10, _PC_LM22 */ 176 _BM(16), _BM(19), /* _WDISP16, _WDISP19 */ 177 -1, /* GLOB_JMP */ 178 _BM(7), _BM(5), _BM(6) /* _7, _5, _6 */ 179 -1, -1, /* DISP64, PLT64 */ 180 _BM(22), _BM(13), /* HIX22, LOX10 */ 181 _BM(22), _BM(10), _BM(13), /* H44, M44, L44 */ 182 -1, -1, _BM(16), /* REGISTER, UA64, UA16 */ 183 #undef _BM 184 }; 185 #define RELOC_VALUE_BITMASK(t) (reloc_target_bitmask[t]) 186 187 188 int 189 _rtld_relocate_nonplt_object(obj, rela, dodebug) 190 Obj_Entry *obj; 191 const Elf_RelA *rela; 192 bool dodebug; 193 { 194 Elf_Addr *where = (Elf_Addr *) (obj->relocbase + rela->r_offset); 195 Elf_Word type, value = 0, mask; 196 const Elf_Sym *def = NULL; 197 const Obj_Entry *defobj = NULL; 198 199 type = ELF_R_TYPE(rela->r_info); 200 if (type == R_TYPE(NONE)) 201 return (0); 202 203 /* We do JMP_SLOTs in relocate_plt_object() below */ 204 if (type == R_TYPE(JMP_SLOT)) 205 return (0); 206 207 /* COPY relocs are also handled elsewhere */ 208 if (type == R_TYPE(COPY)) 209 return (0); 210 211 /* 212 * We use the fact that relocation types are an `enum' 213 * Note: R_SPARC_UA16 is currently numerically largest. 214 */ 215 if (type > R_TYPE(UA16)) 216 return (-1); 217 218 value = rela->r_addend; 219 220 /* 221 * Handle relative relocs here, because we might not 222 * be able to access globals yet. 223 */ 224 if (!dodebug && type == R_TYPE(RELATIVE)) { 225 /* XXXX -- apparently we ignore the preexisting value */ 226 *where = (Elf_Addr)(obj->relocbase + value); 227 return (0); 228 } 229 230 if (RELOC_RESOLVE_SYMBOL(type)) { 231 232 /* Find the symbol */ 233 def = _rtld_find_symdef(_rtld_objlist, rela->r_info, 234 NULL, obj, &defobj, false); 235 if (def == NULL) 236 return (-1); 237 238 /* Add in the symbol's absolute address */ 239 value += (Elf_Word)(defobj->relocbase + def->st_value); 240 } 241 242 if (RELOC_PC_RELATIVE(type)) { 243 value -= (Elf_Word)where; 244 } 245 246 if (RELOC_BASE_RELATIVE(type)) { 247 /* 248 * Note that even though sparcs use `Elf_rela' exclusively 249 * we still need the implicit memory addend in relocations 250 * referring to GOT entries. Undoubtedly, someone f*cked 251 * this up in the distant past, and now we're stuck with 252 * it in the name of compatibility for all eternity.. 253 * 254 * In any case, the implicit and explicit should be mutually 255 * exclusive. We provide a check for that here. 256 */ 257 #ifdef DIAGNOSTIC 258 if (value != 0 && *where != 0) { 259 xprintf("BASE_REL(%s): where=%p, *where 0x%lx, " 260 "addend=0x%lx, base %p\n", 261 obj->path, where, *where, 262 rela->r_addend, obj->relocbase); 263 } 264 #endif 265 /* XXXX -- apparently we ignore the preexisting value */ 266 value += (Elf_Word)(obj->relocbase); 267 } 268 269 mask = RELOC_VALUE_BITMASK(type); 270 value >>= RELOC_VALUE_RIGHTSHIFT(type); 271 value &= mask; 272 273 if (RELOC_UNALIGNED(type)) { 274 /* Handle unaligned relocations. */ 275 Elf_Word tmp = 0; 276 char *ptr = (char *)where; 277 int i, size = RELOC_TARGET_SIZE(type)/8; 278 279 /* Read it in one byte at a time. */ 280 for (i=0; i<size; i++) 281 tmp = (tmp << 8) | ptr[i]; 282 283 tmp &= ~mask; 284 tmp |= value; 285 286 /* Write it back out. */ 287 for (i=0; i<size; i++) 288 ptr[i] = ((tmp >> (8*i)) & 0xff); 289 #ifdef RTLD_DEBUG_RELOC 290 value = (Elf_Word)tmp; 291 #endif 292 293 } else if (RELOC_TARGET_SIZE(type) > 32) { 294 *where &= ~mask; 295 *where |= value; 296 #ifdef RTLD_DEBUG_RELOC 297 value = (Elf_Word)*where; 298 #endif 299 } else { 300 Elf32_Addr *where32 = (Elf32_Addr *)where; 301 302 *where32 &= ~mask; 303 *where32 |= value; 304 #ifdef RTLD_DEBUG_RELOC 305 value = (Elf_Word)*where32; 306 #endif 307 } 308 309 #ifdef RTLD_DEBUG_RELOC 310 if (RELOC_RESOLVE_SYMBOL(type)) { 311 rdbg(dodebug, ("%s %s in %s --> %p %s", 312 reloc_names[type], 313 defobj->strtab + def->st_name, obj->path, 314 (void *)value, defobj->path)); 315 } 316 else { 317 rdbg(dodebug, ("%s --> %p", reloc_names[type], 318 (void *)value)); 319 } 320 #endif 321 return (0); 322 } 323 324 /* 325 * Instruction templates: 326 */ 327 #define BAA 0x10400000 /* ba,a %xcc, 0 */ 328 #define SETHI 0x03000000 /* sethi %hi(0), %g1 */ 329 #define JMP 0x81c06000 /* jmpl %g1+%lo(0), %g0 */ 330 #define NOP 0x01000000 /* sethi %hi(0), %g0 */ 331 #define OR 0x82806000 /* or %g1, 0, %g1 */ 332 #define XOR 0x82c06000 /* xor %g1, 0, %g1 */ 333 #define MOV71 0x8283a000 /* or %o7, 0, %g1 */ 334 #define MOV17 0x9c806000 /* or %g1, 0, %o7 */ 335 #define CALL 0x40000000 /* call 0 */ 336 #define SLLX 0x8b407000 /* sllx %g1, 0, %g1 */ 337 #define SETHIG5 0x0b000000 /* sethi %hi(0), %g5 */ 338 #define ORG5 0x82804005 /* or %g1, %g5, %g1 */ 339 340 341 /* %hi(v) with variable shift */ 342 #define HIVAL(v, s) (((v) >> (s)) & 0x003fffff) 343 #define LOVAL(v) ((v) & 0x000003ff) 344 345 int 346 _rtld_relocate_plt_object(obj, rela, addrp, bind_now, dodebug) 347 Obj_Entry *obj; 348 const Elf_RelA *rela; 349 caddr_t *addrp; 350 bool bind_now; 351 bool dodebug; 352 { 353 const Elf_Sym *def; 354 const Obj_Entry *defobj; 355 Elf32_Word *where = (Elf32_Word *)((Elf_Addr)obj->pltgot + rela->r_offset); 356 Elf_Addr value, offset; 357 358 if (bind_now == 0 && obj->pltgot != NULL) 359 return (0); 360 361 /* Fully resolve procedure addresses now */ 362 363 assert(ELF_R_TYPE(rela->r_info) == R_TYPE(JMP_SLOT)); 364 365 def = _rtld_find_symdef(_rtld_objlist, rela->r_info, 366 NULL, obj, &defobj, true); 367 if (def == NULL) 368 return (-1); 369 370 value = (Elf_Addr) (defobj->relocbase + def->st_value); 371 rdbg(dodebug, ("bind now %d/fixup in %s --> old=%lx new=%lx", 372 (int)bind_now, defobj->strtab + def->st_name, 373 (u_long)*where, (u_long)value)); 374 375 /* 376 * At the PLT entry pointed at by `where', we now construct 377 * a direct transfer to the now fully resolved function 378 * address. 379 * 380 * A PLT entry is supposed to start by looking like this: 381 * 382 * sethi %hi(. - .PLT0), %g1 383 * ba,a %xcc, .PLT1 384 * nop 385 * nop 386 * nop 387 * nop 388 * nop 389 * nop 390 * 391 * When we replace these entries we start from the second 392 * entry and do it in reverse order so the last thing we 393 * do is replace the branch. That allows us to change this 394 * atomically. 395 * 396 * We now need to find out how far we need to jump. We 397 * have a choice of several different relocation techniques 398 * which are increasingly expensive. 399 */ 400 401 offset = ((Elf_Addr)where) - value; 402 if (rela->r_addend) { 403 Elf_Addr *ptr = (Elf_Addr *)where; 404 /* 405 * This entry is >32768. Just replace the pointer. 406 */ 407 ptr[0] = value; 408 409 } else if (offset <= (1L<<20) && offset >= -(1L<<20)) { 410 /* 411 * We're within 1MB -- we can use a direct branch insn. 412 * 413 * We can generate this pattern: 414 * 415 * sethi %hi(. - .PLT0), %g1 416 * ba,a %xcc, addr 417 * nop 418 * nop 419 * nop 420 * nop 421 * nop 422 * nop 423 * 424 */ 425 where[1] = BAA | ((offset >> 2) &0x3fffff); 426 __asm __volatile("iflush %0+4" : : "r" (where)); 427 } else if (value >= 0 && value < (1L<<32)) { 428 /* 429 * We're withing 32-bits of address zero. 430 * 431 * The resulting code in the jump slot is: 432 * 433 * sethi %hi(. - .PLT0), %g1 434 * sethi %hi(addr), %g1 435 * jmp %g1+%lo(addr) 436 * nop 437 * nop 438 * nop 439 * nop 440 * nop 441 * 442 */ 443 where[2] = JMP | LOVAL(value); 444 where[1] = SETHI | HIVAL(value, 10); 445 __asm __volatile("iflush %0+8" : : "r" (where)); 446 __asm __volatile("iflush %0+4" : : "r" (where)); 447 448 } else if (value <= 0 && value > -(1L<<32)) { 449 /* 450 * We're withing 32-bits of address -1. 451 * 452 * The resulting code in the jump slot is: 453 * 454 * sethi %hi(. - .PLT0), %g1 455 * sethi %hix(addr), %g1 456 * xor %g1, %lox(addr), %g1 457 * jmp %g1 458 * nop 459 * nop 460 * nop 461 * nop 462 * 463 */ 464 where[3] = JMP; 465 where[2] = XOR | ((~value) & 0x00001fff); 466 where[1] = SETHI | HIVAL(~value, 10); 467 __asm __volatile("iflush %0+12" : : "r" (where)); 468 __asm __volatile("iflush %0+8" : : "r" (where)); 469 __asm __volatile("iflush %0+4" : : "r" (where)); 470 471 } else if (offset <= (1L<<32) && offset >= -((1L<<32) - 4)) { 472 /* 473 * We're withing 32-bits -- we can use a direct call insn 474 * 475 * The resulting code in the jump slot is: 476 * 477 * sethi %hi(. - .PLT0), %g1 478 * mov %o7, %g1 479 * call (.+offset) 480 * mov %g1, %o7 481 * nop 482 * nop 483 * nop 484 * nop 485 * 486 */ 487 where[3] = MOV17; 488 where[2] = CALL | ((offset >> 4) & 0x3fffffff); 489 where[1] = MOV71; 490 __asm __volatile("iflush %0+12" : : "r" (where)); 491 __asm __volatile("iflush %0+8" : : "r" (where)); 492 __asm __volatile("iflush %0+4" : : "r" (where)); 493 494 } else if (offset >= 0 && offset < (1L<<44)) { 495 /* 496 * We're withing 44 bits. We can generate this pattern: 497 * 498 * The resulting code in the jump slot is: 499 * 500 * sethi %hi(. - .PLT0), %g1 501 * sethi %h44(addr), %g1 502 * or %g1, %m44(addr), %g1 503 * sllx %g1, 12, %g1 504 * jmp %g1+%l44(addr) 505 * nop 506 * nop 507 * nop 508 * 509 */ 510 where[4] = JMP | LOVAL(offset); 511 where[3] = SLLX | 12; 512 where[2] = OR | (((offset) >> 12) & 0x00001fff); 513 where[1] = SETHI | HIVAL(offset, 22); 514 __asm __volatile("iflush %0+16" : : "r" (where)); 515 __asm __volatile("iflush %0+12" : : "r" (where)); 516 __asm __volatile("iflush %0+8" : : "r" (where)); 517 __asm __volatile("iflush %0+4" : : "r" (where)); 518 519 } else if (offset < 0 && offset > -(1L<<44)) { 520 /* 521 * We're withing 44 bits. We can generate this pattern: 522 * 523 * The resulting code in the jump slot is: 524 * 525 * sethi %hi(. - .PLT0), %g1 526 * sethi %h44(-addr), %g1 527 * xor %g1, %m44(-addr), %g1 528 * sllx %g1, 12, %g1 529 * jmp %g1+%l44(addr) 530 * nop 531 * nop 532 * nop 533 * 534 */ 535 where[4] = JMP | LOVAL(offset); 536 where[3] = SLLX | 12; 537 where[2] = XOR | (((~offset) >> 12) & 0x00001fff); 538 where[1] = SETHI | HIVAL(~offset, 22); 539 __asm __volatile("iflush %0+16" : : "r" (where)); 540 __asm __volatile("iflush %0+12" : : "r" (where)); 541 __asm __volatile("iflush %0+8" : : "r" (where)); 542 __asm __volatile("iflush %0+4" : : "r" (where)); 543 544 } else { 545 /* 546 * We need to load all 64-bits 547 * 548 * The resulting code in the jump slot is: 549 * 550 * sethi %hi(. - .PLT0), %g1 551 * sethi %hh(addr), %g1 552 * sethi %lm(addr), %g5 553 * or %g1, %hm(addr), %g1 554 * sllx %g1, 32, %g1 555 * or %g1, %g5, %g1 556 * jmp %g1+%lo(addr) 557 * nop 558 * 559 */ 560 where[6] = JMP | LOVAL(value); 561 where[5] = ORG5; 562 where[4] = SLLX | 12; 563 where[3] = OR | LOVAL((value) >> 32); 564 where[2] = SETHIG5 | HIVAL(value, 10); 565 where[1] = SETHI | HIVAL(value, 42); 566 __asm __volatile("iflush %0+20" : : "r" (where)); 567 __asm __volatile("iflush %0+16" : : "r" (where)); 568 __asm __volatile("iflush %0+16" : : "r" (where)); 569 __asm __volatile("iflush %0+12" : : "r" (where)); 570 __asm __volatile("iflush %0+8" : : "r" (where)); 571 __asm __volatile("iflush %0+4" : : "r" (where)); 572 573 } 574 575 if (addrp != NULL) 576 *addrp = (caddr_t)value; 577 578 return (0); 579 } 580 581 /* 582 * Install rtld function call into this PLT slot. 583 */ 584 #define SAVE 0x9de3bf50 585 #define SETHI_l0 0x21000000 586 #define SETHI_l1 0x23000000 587 #define OR_l0_l0 0xa0142000 588 #define SLLX_l0_32_l0 0xa12c3020 589 #define OR_l0_l1_l0 0xa0140011 590 #define JMPL_l0_o0 0x93c42000 591 #define MOV_g1_o0 0x90100001 592 593 void _rtld_install_plt __P((Elf32_Word *pltgot, Elf_Addr proc)); 594 595 void 596 _rtld_install_plt(pltgot, proc) 597 Elf32_Word *pltgot; 598 Elf_Addr proc; 599 { 600 pltgot[0] = SAVE; 601 pltgot[1] = SETHI_l0 | HIVAL(proc, 42); 602 pltgot[2] = SETHI_l1 | HIVAL(proc, 10); 603 pltgot[3] = OR_l0_l0 | LOVAL((proc) >> 32); 604 pltgot[4] = SLLX_l0_32_l0; 605 pltgot[5] = OR_l0_l1_l0; 606 pltgot[6] = JMPL_l0_o0 | LOVAL(proc); 607 pltgot[7] = MOV_g1_o0; 608 } 609 610 long _rtld_bind_start_0_stub __P((long x, long y)); 611 long 612 _rtld_bind_start_0_stub(x, y) 613 long x, y; 614 { 615 long i; 616 long n; 617 618 i = x - y + 1048596; 619 n = 32768 + (i/5120)*160 + (i%5120)/24; 620 621 return (n); 622 } 623 624
Indexes created Mon Sep 29 21:09:56 GMT 2025