mdreloc.c revision 1.20
1 /* $NetBSD: mdreloc.c,v 1.20 2002/09/12 20:24:03 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Eduardo Horvath. 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <errno.h> 41 #include <stdio.h> 42 #include <stdlib.h> 43 #include <string.h> 44 #include <unistd.h> 45 #include <sys/stat.h> 46 47 #include "rtldenv.h" 48 #include "debug.h" 49 #include "rtld.h" 50 51 /* 52 * The following table holds for each relocation type: 53 * - the width in bits of the memory location the relocation 54 * applies to (not currently used) 55 * - the number of bits the relocation value must be shifted to the 56 * right (i.e. discard least significant bits) to fit into 57 * the appropriate field in the instruction word. 58 * - flags indicating whether 59 * * the relocation involves a symbol 60 * * the relocation is relative to the current position 61 * * the relocation is for a GOT entry 62 * * the relocation is relative to the load address 63 * 64 */ 65 #define _RF_S 0x80000000 /* Resolve symbol */ 66 #define _RF_A 0x40000000 /* Use addend */ 67 #define _RF_P 0x20000000 /* Location relative */ 68 #define _RF_G 0x10000000 /* GOT offset */ 69 #define _RF_B 0x08000000 /* Load address relative */ 70 #define _RF_U 0x04000000 /* Unaligned */ 71 #define _RF_SZ(s) (((s) & 0xff) << 8) /* memory target size */ 72 #define _RF_RS(s) ( (s) & 0xff) /* right shift */ 73 static const int reloc_target_flags[] = { 74 0, /* NONE */ 75 _RF_S|_RF_A| _RF_SZ(8) | _RF_RS(0), /* RELOC_8 */ 76 _RF_S|_RF_A| _RF_SZ(16) | _RF_RS(0), /* RELOC_16 */ 77 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* RELOC_32 */ 78 _RF_S|_RF_A|_RF_P| _RF_SZ(8) | _RF_RS(0), /* DISP_8 */ 79 _RF_S|_RF_A|_RF_P| _RF_SZ(16) | _RF_RS(0), /* DISP_16 */ 80 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* DISP_32 */ 81 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_30 */ 82 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_22 */ 83 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HI22 */ 84 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 22 */ 85 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 13 */ 86 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LO10 */ 87 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT10 */ 88 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT13 */ 89 _RF_G| _RF_SZ(32) | _RF_RS(10), /* GOT22 */ 90 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PC10 */ 91 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC22 */ 92 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WPLT30 */ 93 _RF_SZ(32) | _RF_RS(0), /* COPY */ 94 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* GLOB_DAT */ 95 _RF_SZ(32) | _RF_RS(0), /* JMP_SLOT */ 96 _RF_A| _RF_B| _RF_SZ(64) | _RF_RS(0), /* RELATIVE */ 97 _RF_S|_RF_A| _RF_U| _RF_SZ(32) | _RF_RS(0), /* UA_32 */ 98 99 _RF_A| _RF_SZ(32) | _RF_RS(0), /* PLT32 */ 100 _RF_A| _RF_SZ(32) | _RF_RS(10), /* HIPLT22 */ 101 _RF_A| _RF_SZ(32) | _RF_RS(0), /* LOPLT10 */ 102 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT32 */ 103 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PCPLT22 */ 104 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT10 */ 105 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 10 */ 106 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 11 */ 107 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* 64 */ 108 _RF_S|_RF_A|/*extra*/ _RF_SZ(32) | _RF_RS(0), /* OLO10 */ 109 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(42), /* HH22 */ 110 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(32), /* HM10 */ 111 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* LM22 */ 112 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(42), /* PC_HH22 */ 113 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(32), /* PC_HM10 */ 114 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC_LM22 */ 115 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP16 */ 116 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP19 */ 117 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* GLOB_JMP */ 118 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 7 */ 119 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 5 */ 120 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 6 */ 121 _RF_S|_RF_A|_RF_P| _RF_SZ(64) | _RF_RS(0), /* DISP64 */ 122 _RF_A| _RF_SZ(64) | _RF_RS(0), /* PLT64 */ 123 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HIX22 */ 124 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LOX10 */ 125 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(22), /* H44 */ 126 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(12), /* M44 */ 127 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* L44 */ 128 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* REGISTER */ 129 _RF_S|_RF_A| _RF_U| _RF_SZ(64) | _RF_RS(0), /* UA64 */ 130 _RF_S|_RF_A| _RF_U| _RF_SZ(16) | _RF_RS(0), /* UA16 */ 131 }; 132 133 #ifdef RTLD_DEBUG_RELOC 134 static const char *reloc_names[] = { 135 "NONE", "RELOC_8", "RELOC_16", "RELOC_32", "DISP_8", 136 "DISP_16", "DISP_32", "WDISP_30", "WDISP_22", "HI22", 137 "22", "13", "LO10", "GOT10", "GOT13", 138 "GOT22", "PC10", "PC22", "WPLT30", "COPY", 139 "GLOB_DAT", "JMP_SLOT", "RELATIVE", "UA_32", "PLT32", 140 "HIPLT22", "LOPLT10", "LOPLT10", "PCPLT22", "PCPLT32", 141 "10", "11", "64", "OLO10", "HH22", 142 "HM10", "LM22", "PC_HH22", "PC_HM10", "PC_LM22", 143 "WDISP16", "WDISP19", "GLOB_JMP", "7", "5", "6", 144 "DISP64", "PLT64", "HIX22", "LOX10", "H44", "M44", 145 "L44", "REGISTER", "UA64", "UA16" 146 }; 147 #endif 148 149 #define RELOC_RESOLVE_SYMBOL(t) ((reloc_target_flags[t] & _RF_S) != 0) 150 #define RELOC_PC_RELATIVE(t) ((reloc_target_flags[t] & _RF_P) != 0) 151 #define RELOC_BASE_RELATIVE(t) ((reloc_target_flags[t] & _RF_B) != 0) 152 #define RELOC_UNALIGNED(t) ((reloc_target_flags[t] & _RF_U) != 0) 153 #define RELOC_USE_ADDEND(t) ((reloc_target_flags[t] & _RF_A) != 0) 154 #define RELOC_TARGET_SIZE(t) ((reloc_target_flags[t] >> 8) & 0xff) 155 #define RELOC_VALUE_RIGHTSHIFT(t) (reloc_target_flags[t] & 0xff) 156 157 static const long reloc_target_bitmask[] = { 158 #define _BM(x) (~(-(1ULL << (x)))) 159 0, /* NONE */ 160 _BM(8), _BM(16), _BM(32), /* RELOC_8, _16, _32 */ 161 _BM(8), _BM(16), _BM(32), /* DISP8, DISP16, DISP32 */ 162 _BM(30), _BM(22), /* WDISP30, WDISP22 */ 163 _BM(22), _BM(22), /* HI22, _22 */ 164 _BM(13), _BM(10), /* RELOC_13, _LO10 */ 165 _BM(10), _BM(13), _BM(22), /* GOT10, GOT13, GOT22 */ 166 _BM(10), _BM(22), /* _PC10, _PC22 */ 167 _BM(30), 0, /* _WPLT30, _COPY */ 168 _BM(32), _BM(32), _BM(32), /* _GLOB_DAT, JMP_SLOT, _RELATIVE */ 169 _BM(32), _BM(32), /* _UA32, PLT32 */ 170 _BM(22), _BM(10), /* _HIPLT22, LOPLT10 */ 171 _BM(32), _BM(22), _BM(10), /* _PCPLT32, _PCPLT22, _PCPLT10 */ 172 _BM(10), _BM(11), -1, /* _10, _11, _64 */ 173 _BM(10), _BM(22), /* _OLO10, _HH22 */ 174 _BM(10), _BM(22), /* _HM10, _LM22 */ 175 _BM(22), _BM(10), _BM(22), /* _PC_HH22, _PC_HM10, _PC_LM22 */ 176 _BM(16), _BM(19), /* _WDISP16, _WDISP19 */ 177 -1, /* GLOB_JMP */ 178 _BM(7), _BM(5), _BM(6) /* _7, _5, _6 */ 179 -1, -1, /* DISP64, PLT64 */ 180 _BM(22), _BM(13), /* HIX22, LOX10 */ 181 _BM(22), _BM(10), _BM(13), /* H44, M44, L44 */ 182 -1, -1, _BM(16), /* REGISTER, UA64, UA16 */ 183 #undef _BM 184 }; 185 #define RELOC_VALUE_BITMASK(t) (reloc_target_bitmask[t]) 186 187 /* 188 * Instruction templates: 189 */ 190 #define BAA 0x10400000 /* ba,a %xcc, 0 */ 191 #define SETHI 0x03000000 /* sethi %hi(0), %g1 */ 192 #define JMP 0x81c06000 /* jmpl %g1+%lo(0), %g0 */ 193 #define NOP 0x01000000 /* sethi %hi(0), %g0 */ 194 #define OR 0x82806000 /* or %g1, 0, %g1 */ 195 #define XOR 0x82c06000 /* xor %g1, 0, %g1 */ 196 #define MOV71 0x8283a000 /* or %o7, 0, %g1 */ 197 #define MOV17 0x9c806000 /* or %g1, 0, %o7 */ 198 #define CALL 0x40000000 /* call 0 */ 199 #define SLLX 0x8b407000 /* sllx %g1, 0, %g1 */ 200 #define SETHIG5 0x0b000000 /* sethi %hi(0), %g5 */ 201 #define ORG5 0x82804005 /* or %g1, %g5, %g1 */ 202 203 204 /* %hi(v) with variable shift */ 205 #define HIVAL(v, s) (((v) >> (s)) & 0x003fffff) 206 #define LOVAL(v) ((v) & 0x000003ff) 207 208 void _rtld_bind_start_0(long, long); 209 void _rtld_bind_start_1(long, long); 210 void _rtld_relocate_nonplt_self(Elf_Dyn *, Elf_Addr); 211 212 int 213 _rtld_relocate_plt_object(obj, rela, addrp, dodebug) 214 const Obj_Entry *obj; 215 const Elf_Rela *rela; 216 caddr_t *addrp; 217 bool dodebug; 218 { 219 const Elf_Sym *def; 220 const Obj_Entry *defobj; 221 Elf_Word *where = (Elf_Word *)((Elf_Addr)obj->relocbase + rela->r_offset); 222 Elf_Addr value, offset; 223 224 /* Fully resolve procedure addresses now */ 225 226 assert(ELF_R_TYPE(rela->r_info) == R_TYPE(JMP_SLOT)); 227 228 def = _rtld_find_symdef(ELF_R_SYM(rela->r_info), obj, &defobj, true); 229 if (def == NULL) 230 return (-1); 231 232 value = (Elf_Addr) (defobj->relocbase + def->st_value); 233 rdbg(dodebug, ("bind now/fixup in %s --> old=%lx new=%lx", 234 defobj->strtab + def->st_name, 235 (u_long)*where, (u_long)value)); 236 237 /* 238 * At the PLT entry pointed at by `where', we now construct 239 * a direct transfer to the now fully resolved function 240 * address. 241 * 242 * A PLT entry is supposed to start by looking like this: 243 * 244 * sethi %hi(. - .PLT0), %g1 245 * ba,a %xcc, .PLT1 246 * nop 247 * nop 248 * nop 249 * nop 250 * nop 251 * nop 252 * 253 * When we replace these entries we start from the second 254 * entry and do it in reverse order so the last thing we 255 * do is replace the branch. That allows us to change this 256 * atomically. 257 * 258 * We now need to find out how far we need to jump. We 259 * have a choice of several different relocation techniques 260 * which are increasingly expensive. 261 */ 262 263 offset = ((Elf_Addr)where) - value; 264 if (rela->r_addend) { 265 Elf_Addr *ptr = (Elf_Addr *)where; 266 /* 267 * This entry is >32768. Just replace the pointer. 268 */ 269 ptr[0] = value; 270 271 } else if (offset <= (1L<<20) && offset >= -(1L<<20)) { 272 /* 273 * We're within 1MB -- we can use a direct branch insn. 274 * 275 * We can generate this pattern: 276 * 277 * sethi %hi(. - .PLT0), %g1 278 * ba,a %xcc, addr 279 * nop 280 * nop 281 * nop 282 * nop 283 * nop 284 * nop 285 * 286 */ 287 where[1] = BAA | ((offset >> 2) &0x3fffff); 288 __asm __volatile("iflush %0+4" : : "r" (where)); 289 } else if (value >= 0 && value < (1L<<32)) { 290 /* 291 * We're withing 32-bits of address zero. 292 * 293 * The resulting code in the jump slot is: 294 * 295 * sethi %hi(. - .PLT0), %g1 296 * sethi %hi(addr), %g1 297 * jmp %g1+%lo(addr) 298 * nop 299 * nop 300 * nop 301 * nop 302 * nop 303 * 304 */ 305 where[2] = JMP | LOVAL(value); 306 where[1] = SETHI | HIVAL(value, 10); 307 __asm __volatile("iflush %0+8" : : "r" (where)); 308 __asm __volatile("iflush %0+4" : : "r" (where)); 309 310 } else if (value <= 0 && value > -(1L<<32)) { 311 /* 312 * We're withing 32-bits of address -1. 313 * 314 * The resulting code in the jump slot is: 315 * 316 * sethi %hi(. - .PLT0), %g1 317 * sethi %hix(addr), %g1 318 * xor %g1, %lox(addr), %g1 319 * jmp %g1 320 * nop 321 * nop 322 * nop 323 * nop 324 * 325 */ 326 where[3] = JMP; 327 where[2] = XOR | ((~value) & 0x00001fff); 328 where[1] = SETHI | HIVAL(~value, 10); 329 __asm __volatile("iflush %0+12" : : "r" (where)); 330 __asm __volatile("iflush %0+8" : : "r" (where)); 331 __asm __volatile("iflush %0+4" : : "r" (where)); 332 333 } else if (offset <= (1L<<32) && offset >= -((1L<<32) - 4)) { 334 /* 335 * We're withing 32-bits -- we can use a direct call insn 336 * 337 * The resulting code in the jump slot is: 338 * 339 * sethi %hi(. - .PLT0), %g1 340 * mov %o7, %g1 341 * call (.+offset) 342 * mov %g1, %o7 343 * nop 344 * nop 345 * nop 346 * nop 347 * 348 */ 349 where[3] = MOV17; 350 where[2] = CALL | ((offset >> 4) & 0x3fffffff); 351 where[1] = MOV71; 352 __asm __volatile("iflush %0+12" : : "r" (where)); 353 __asm __volatile("iflush %0+8" : : "r" (where)); 354 __asm __volatile("iflush %0+4" : : "r" (where)); 355 356 } else if (offset >= 0 && offset < (1L<<44)) { 357 /* 358 * We're withing 44 bits. We can generate this pattern: 359 * 360 * The resulting code in the jump slot is: 361 * 362 * sethi %hi(. - .PLT0), %g1 363 * sethi %h44(addr), %g1 364 * or %g1, %m44(addr), %g1 365 * sllx %g1, 12, %g1 366 * jmp %g1+%l44(addr) 367 * nop 368 * nop 369 * nop 370 * 371 */ 372 where[4] = JMP | LOVAL(offset); 373 where[3] = SLLX | 12; 374 where[2] = OR | (((offset) >> 12) & 0x00001fff); 375 where[1] = SETHI | HIVAL(offset, 22); 376 __asm __volatile("iflush %0+16" : : "r" (where)); 377 __asm __volatile("iflush %0+12" : : "r" (where)); 378 __asm __volatile("iflush %0+8" : : "r" (where)); 379 __asm __volatile("iflush %0+4" : : "r" (where)); 380 381 } else if (offset < 0 && offset > -(1L<<44)) { 382 /* 383 * We're withing 44 bits. We can generate this pattern: 384 * 385 * The resulting code in the jump slot is: 386 * 387 * sethi %hi(. - .PLT0), %g1 388 * sethi %h44(-addr), %g1 389 * xor %g1, %m44(-addr), %g1 390 * sllx %g1, 12, %g1 391 * jmp %g1+%l44(addr) 392 * nop 393 * nop 394 * nop 395 * 396 */ 397 where[4] = JMP | LOVAL(offset); 398 where[3] = SLLX | 12; 399 where[2] = XOR | (((~offset) >> 12) & 0x00001fff); 400 where[1] = SETHI | HIVAL(~offset, 22); 401 __asm __volatile("iflush %0+16" : : "r" (where)); 402 __asm __volatile("iflush %0+12" : : "r" (where)); 403 __asm __volatile("iflush %0+8" : : "r" (where)); 404 __asm __volatile("iflush %0+4" : : "r" (where)); 405 406 } else { 407 /* 408 * We need to load all 64-bits 409 * 410 * The resulting code in the jump slot is: 411 * 412 * sethi %hi(. - .PLT0), %g1 413 * sethi %hh(addr), %g1 414 * sethi %lm(addr), %g5 415 * or %g1, %hm(addr), %g1 416 * sllx %g1, 32, %g1 417 * or %g1, %g5, %g1 418 * jmp %g1+%lo(addr) 419 * nop 420 * 421 */ 422 where[6] = JMP | LOVAL(value); 423 where[5] = ORG5; 424 where[4] = SLLX | 12; 425 where[3] = OR | LOVAL((value) >> 32); 426 where[2] = SETHIG5 | HIVAL(value, 10); 427 where[1] = SETHI | HIVAL(value, 42); 428 __asm __volatile("iflush %0+20" : : "r" (where)); 429 __asm __volatile("iflush %0+16" : : "r" (where)); 430 __asm __volatile("iflush %0+16" : : "r" (where)); 431 __asm __volatile("iflush %0+12" : : "r" (where)); 432 __asm __volatile("iflush %0+8" : : "r" (where)); 433 __asm __volatile("iflush %0+4" : : "r" (where)); 434 435 } 436 437 *addrp = (caddr_t)value; 438 return (0); 439 } 440 441 /* 442 * Install rtld function call into this PLT slot. 443 */ 444 #define SAVE 0x9de3bf50 445 #define SETHI_l0 0x21000000 446 #define SETHI_l1 0x23000000 447 #define OR_l0_l0 0xa0142000 448 #define SLLX_l0_32_l0 0xa12c3020 449 #define OR_l0_l1_l0 0xa0140011 450 #define JMPL_l0_o1 0x93c42000 451 #define MOV_g1_o0 0x90100001 452 453 void _rtld_install_plt __P((Elf_Word *pltgot, Elf_Addr proc)); 454 455 void 456 _rtld_install_plt(pltgot, proc) 457 Elf_Word *pltgot; 458 Elf_Addr proc; 459 { 460 pltgot[0] = SAVE; 461 pltgot[1] = SETHI_l0 | HIVAL(proc, 42); 462 pltgot[2] = SETHI_l1 | HIVAL(proc, 10); 463 pltgot[3] = OR_l0_l0 | LOVAL((proc) >> 32); 464 pltgot[4] = SLLX_l0_32_l0; 465 pltgot[5] = OR_l0_l1_l0; 466 pltgot[6] = JMPL_l0_o1 | LOVAL(proc); 467 pltgot[7] = MOV_g1_o0; 468 } 469 470 long _rtld_bind_start_0_stub __P((long x, long y)); 471 long 472 _rtld_bind_start_0_stub(x, y) 473 long x, y; 474 { 475 long i; 476 long n; 477 478 i = x - y + 1048596; 479 n = 32768 + (i/5120)*160 + (i%5120)/24; 480 481 return (n); 482 } 483 484 void 485 _rtld_setup_pltgot(const Obj_Entry *obj) 486 { 487 /* 488 * On sparc64 we got troubles. 489 * 490 * Instructions are 4 bytes long. 491 * Elf[64]_Addr is 8 bytes long, so are our pltglot[] 492 * array entries. 493 * Each PLT entry jumps to PLT0 to enter the dynamic 494 * linker. 495 * Loading an arbitrary 64-bit pointer takes 6 496 * instructions and 2 registers. 497 * 498 * Somehow we need to issue a save to get a new stack 499 * frame, load the address of the dynamic linker, and 500 * jump there, in 8 instructions or less. 501 * 502 * Oh, we need to fill out both PLT0 and PLT1. 503 */ 504 { 505 Elf_Word *entry = (Elf_Word *)obj->pltgot; 506 507 /* Install in entries 0 and 1 */ 508 _rtld_install_plt(&entry[0], (Elf_Addr) &_rtld_bind_start_0); 509 _rtld_install_plt(&entry[8], (Elf_Addr) &_rtld_bind_start_1); 510 511 /* 512 * Install the object reference in first slot 513 * of entry 2. 514 */ 515 obj->pltgot[8] = (Elf_Addr) obj; 516 } 517 } 518 519 void 520 _rtld_relocate_nonplt_self(dynp, relocbase) 521 Elf_Dyn *dynp; 522 Elf_Addr relocbase; 523 { 524 const Elf_Rela *rela = 0, *relalim; 525 Elf_Addr relasz = 0; 526 Elf_Addr *where; 527 528 for (; dynp->d_tag != DT_NULL; dynp++) { 529 switch (dynp->d_tag) { 530 case DT_RELA: 531 rela = (const Elf_Rela *)(relocbase + dynp->d_un.d_ptr); 532 break; 533 case DT_RELASZ: 534 relasz = dynp->d_un.d_val; 535 break; 536 } 537 } 538 relalim = (const Elf_Rela *)((caddr_t)rela + relasz); 539 for (; rela < relalim; rela++) { 540 where = (Elf_Addr *)(relocbase + rela->r_offset); 541 *where = (Elf_Addr)(relocbase + rela->r_addend); 542 } 543 } 544 545 int 546 _rtld_relocate_nonplt_objects(obj, self, dodebug) 547 const Obj_Entry *obj; 548 bool self; 549 bool dodebug; 550 { 551 const Elf_Rela *rela; 552 553 if (self) 554 return (0); 555 556 for (rela = obj->rela; rela < obj->relalim; rela++) { 557 Elf_Addr *where; 558 Elf_Word type; 559 Elf_Addr value = 0, mask; 560 const Elf_Sym *def = NULL; 561 const Obj_Entry *defobj = NULL; 562 unsigned long symnum; 563 564 where = (Elf_Addr *) (obj->relocbase + rela->r_offset); 565 symnum = ELF_R_SYM(rela->r_info); 566 567 type = ELF_R_TYPE(rela->r_info); 568 if (type == R_TYPE(NONE)) 569 continue; 570 571 /* We do JMP_SLOTs in relocate_plt_object() below */ 572 if (type == R_TYPE(JMP_SLOT)) 573 continue; 574 575 /* COPY relocs are also handled elsewhere */ 576 if (type == R_TYPE(COPY)) 577 continue; 578 579 /* 580 * We use the fact that relocation types are an `enum' 581 * Note: R_SPARC_UA16 is currently numerically largest. 582 */ 583 if (type > R_TYPE(UA16)) 584 return (-1); 585 586 value = rela->r_addend; 587 588 /* 589 * Handle relative relocs here, as an optimization. 590 */ 591 if (type == R_TYPE(RELATIVE)) { 592 *where = (Elf_Addr)(obj->relocbase + value); 593 rdbg(dodebug, ("RELATIVE in %s --> %p", obj->path, 594 (void *)*where)); 595 continue; 596 } 597 598 if (RELOC_RESOLVE_SYMBOL(type)) { 599 600 /* Find the symbol */ 601 def = _rtld_find_symdef(symnum, obj, &defobj, false); 602 if (def == NULL) 603 return (-1); 604 605 /* Add in the symbol's absolute address */ 606 value += (Elf_Addr)(defobj->relocbase + def->st_value); 607 } 608 609 if (RELOC_PC_RELATIVE(type)) { 610 value -= (Elf_Addr)where; 611 } 612 613 if (RELOC_BASE_RELATIVE(type)) { 614 /* 615 * Note that even though sparcs use `Elf_rela' 616 * exclusively we still need the implicit memory addend 617 * in relocations referring to GOT entries. 618 * Undoubtedly, someone f*cked this up in the distant 619 * past, and now we're stuck with it in the name of 620 * compatibility for all eternity.. 621 * 622 * In any case, the implicit and explicit should be 623 * mutually exclusive. We provide a check for that 624 * here. 625 */ 626 #ifdef DIAGNOSTIC 627 if (value != 0 && *where != 0) { 628 xprintf("BASE_REL(%s): where=%p, *where 0x%lx, " 629 "addend=0x%lx, base %p\n", 630 obj->path, where, *where, 631 rela->r_addend, obj->relocbase); 632 } 633 #endif 634 /* XXXX -- apparently we ignore the preexisting value */ 635 value += (Elf_Addr)(obj->relocbase); 636 } 637 638 mask = RELOC_VALUE_BITMASK(type); 639 value >>= RELOC_VALUE_RIGHTSHIFT(type); 640 value &= mask; 641 642 if (RELOC_UNALIGNED(type)) { 643 /* Handle unaligned relocations. */ 644 Elf_Addr tmp = 0; 645 char *ptr = (char *)where; 646 int i, size = RELOC_TARGET_SIZE(type)/8; 647 648 /* Read it in one byte at a time. */ 649 for (i=0; i<size; i++) 650 tmp = (tmp << 8) | ptr[i]; 651 652 tmp &= ~mask; 653 tmp |= value; 654 655 /* Write it back out. */ 656 for (i=0; i<size; i++) 657 ptr[i] = ((tmp >> (8*i)) & 0xff); 658 #ifdef RTLD_DEBUG_RELOC 659 value = (Elf_Addr)tmp; 660 #endif 661 662 } else if (RELOC_TARGET_SIZE(type) > 32) { 663 *where &= ~mask; 664 *where |= value; 665 #ifdef RTLD_DEBUG_RELOC 666 value = (Elf_Addr)*where; 667 #endif 668 } else { 669 Elf32_Addr *where32 = (Elf32_Addr *)where; 670 671 *where32 &= ~mask; 672 *where32 |= value; 673 #ifdef RTLD_DEBUG_RELOC 674 value = (Elf_Addr)*where32; 675 #endif 676 } 677 678 #ifdef RTLD_DEBUG_RELOC 679 if (RELOC_RESOLVE_SYMBOL(type)) { 680 rdbg(dodebug, ("%s %s in %s --> %p in %s", 681 reloc_names[type], 682 obj->strtab + obj->symtab[symnum].st_name, 683 obj->path, (void *)*where, defobj->path)); 684 } else { 685 rdbg(dodebug, ("%s in %s --> %p", 686 reloc_names[type], 687 obj->path, (void *)*where)); 688 } 689 #endif 690 } 691 return (0); 692 } 693 694 int 695 _rtld_relocate_plt_lazy(obj, dodebug) 696 const Obj_Entry *obj; 697 bool dodebug; 698 { 699 return (0); 700 } 701
Indexes created Tue Sep 30 20:09:53 GMT 2025