mdreloc.c revision 1.24
1 /* $NetBSD: mdreloc.c,v 1.24 2002/09/25 14:35:39 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Eduardo Horvath. 5 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <errno.h> 41 #include <stdio.h> 42 #include <stdlib.h> 43 #include <string.h> 44 #include <unistd.h> 45 #include <sys/stat.h> 46 47 #include "rtldenv.h" 48 #include "debug.h" 49 #include "rtld.h" 50 51 /* 52 * The following table holds for each relocation type: 53 * - the width in bits of the memory location the relocation 54 * applies to (not currently used) 55 * - the number of bits the relocation value must be shifted to the 56 * right (i.e. discard least significant bits) to fit into 57 * the appropriate field in the instruction word. 58 * - flags indicating whether 59 * * the relocation involves a symbol 60 * * the relocation is relative to the current position 61 * * the relocation is for a GOT entry 62 * * the relocation is relative to the load address 63 * 64 */ 65 #define _RF_S 0x80000000 /* Resolve symbol */ 66 #define _RF_A 0x40000000 /* Use addend */ 67 #define _RF_P 0x20000000 /* Location relative */ 68 #define _RF_G 0x10000000 /* GOT offset */ 69 #define _RF_B 0x08000000 /* Load address relative */ 70 #define _RF_U 0x04000000 /* Unaligned */ 71 #define _RF_SZ(s) (((s) & 0xff) << 8) /* memory target size */ 72 #define _RF_RS(s) ( (s) & 0xff) /* right shift */ 73 static const int reloc_target_flags[] = { 74 0, /* NONE */ 75 _RF_S|_RF_A| _RF_SZ(8) | _RF_RS(0), /* RELOC_8 */ 76 _RF_S|_RF_A| _RF_SZ(16) | _RF_RS(0), /* RELOC_16 */ 77 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* RELOC_32 */ 78 _RF_S|_RF_A|_RF_P| _RF_SZ(8) | _RF_RS(0), /* DISP_8 */ 79 _RF_S|_RF_A|_RF_P| _RF_SZ(16) | _RF_RS(0), /* DISP_16 */ 80 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* DISP_32 */ 81 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_30 */ 82 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_22 */ 83 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HI22 */ 84 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 22 */ 85 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 13 */ 86 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LO10 */ 87 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT10 */ 88 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT13 */ 89 _RF_G| _RF_SZ(32) | _RF_RS(10), /* GOT22 */ 90 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PC10 */ 91 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC22 */ 92 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WPLT30 */ 93 _RF_SZ(32) | _RF_RS(0), /* COPY */ 94 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* GLOB_DAT */ 95 _RF_SZ(32) | _RF_RS(0), /* JMP_SLOT */ 96 _RF_A| _RF_B| _RF_SZ(64) | _RF_RS(0), /* RELATIVE */ 97 _RF_S|_RF_A| _RF_U| _RF_SZ(32) | _RF_RS(0), /* UA_32 */ 98 99 _RF_A| _RF_SZ(32) | _RF_RS(0), /* PLT32 */ 100 _RF_A| _RF_SZ(32) | _RF_RS(10), /* HIPLT22 */ 101 _RF_A| _RF_SZ(32) | _RF_RS(0), /* LOPLT10 */ 102 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT32 */ 103 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PCPLT22 */ 104 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT10 */ 105 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 10 */ 106 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 11 */ 107 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* 64 */ 108 _RF_S|_RF_A|/*extra*/ _RF_SZ(32) | _RF_RS(0), /* OLO10 */ 109 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(42), /* HH22 */ 110 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(32), /* HM10 */ 111 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* LM22 */ 112 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(42), /* PC_HH22 */ 113 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(32), /* PC_HM10 */ 114 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC_LM22 */ 115 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP16 */ 116 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP19 */ 117 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* GLOB_JMP */ 118 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 7 */ 119 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 5 */ 120 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 6 */ 121 _RF_S|_RF_A|_RF_P| _RF_SZ(64) | _RF_RS(0), /* DISP64 */ 122 _RF_A| _RF_SZ(64) | _RF_RS(0), /* PLT64 */ 123 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HIX22 */ 124 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LOX10 */ 125 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(22), /* H44 */ 126 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(12), /* M44 */ 127 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* L44 */ 128 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* REGISTER */ 129 _RF_S|_RF_A| _RF_U| _RF_SZ(64) | _RF_RS(0), /* UA64 */ 130 _RF_S|_RF_A| _RF_U| _RF_SZ(16) | _RF_RS(0), /* UA16 */ 131 }; 132 133 #ifdef RTLD_DEBUG_RELOC 134 static const char *reloc_names[] = { 135 "NONE", "RELOC_8", "RELOC_16", "RELOC_32", "DISP_8", 136 "DISP_16", "DISP_32", "WDISP_30", "WDISP_22", "HI22", 137 "22", "13", "LO10", "GOT10", "GOT13", 138 "GOT22", "PC10", "PC22", "WPLT30", "COPY", 139 "GLOB_DAT", "JMP_SLOT", "RELATIVE", "UA_32", "PLT32", 140 "HIPLT22", "LOPLT10", "LOPLT10", "PCPLT22", "PCPLT32", 141 "10", "11", "64", "OLO10", "HH22", 142 "HM10", "LM22", "PC_HH22", "PC_HM10", "PC_LM22", 143 "WDISP16", "WDISP19", "GLOB_JMP", "7", "5", "6", 144 "DISP64", "PLT64", "HIX22", "LOX10", "H44", "M44", 145 "L44", "REGISTER", "UA64", "UA16" 146 }; 147 #endif 148 149 #define RELOC_RESOLVE_SYMBOL(t) ((reloc_target_flags[t] & _RF_S) != 0) 150 #define RELOC_PC_RELATIVE(t) ((reloc_target_flags[t] & _RF_P) != 0) 151 #define RELOC_BASE_RELATIVE(t) ((reloc_target_flags[t] & _RF_B) != 0) 152 #define RELOC_UNALIGNED(t) ((reloc_target_flags[t] & _RF_U) != 0) 153 #define RELOC_USE_ADDEND(t) ((reloc_target_flags[t] & _RF_A) != 0) 154 #define RELOC_TARGET_SIZE(t) ((reloc_target_flags[t] >> 8) & 0xff) 155 #define RELOC_VALUE_RIGHTSHIFT(t) (reloc_target_flags[t] & 0xff) 156 157 static const long reloc_target_bitmask[] = { 158 #define _BM(x) (~(-(1ULL << (x)))) 159 0, /* NONE */ 160 _BM(8), _BM(16), _BM(32), /* RELOC_8, _16, _32 */ 161 _BM(8), _BM(16), _BM(32), /* DISP8, DISP16, DISP32 */ 162 _BM(30), _BM(22), /* WDISP30, WDISP22 */ 163 _BM(22), _BM(22), /* HI22, _22 */ 164 _BM(13), _BM(10), /* RELOC_13, _LO10 */ 165 _BM(10), _BM(13), _BM(22), /* GOT10, GOT13, GOT22 */ 166 _BM(10), _BM(22), /* _PC10, _PC22 */ 167 _BM(30), 0, /* _WPLT30, _COPY */ 168 _BM(32), _BM(32), _BM(32), /* _GLOB_DAT, JMP_SLOT, _RELATIVE */ 169 _BM(32), _BM(32), /* _UA32, PLT32 */ 170 _BM(22), _BM(10), /* _HIPLT22, LOPLT10 */ 171 _BM(32), _BM(22), _BM(10), /* _PCPLT32, _PCPLT22, _PCPLT10 */ 172 _BM(10), _BM(11), -1, /* _10, _11, _64 */ 173 _BM(10), _BM(22), /* _OLO10, _HH22 */ 174 _BM(10), _BM(22), /* _HM10, _LM22 */ 175 _BM(22), _BM(10), _BM(22), /* _PC_HH22, _PC_HM10, _PC_LM22 */ 176 _BM(16), _BM(19), /* _WDISP16, _WDISP19 */ 177 -1, /* GLOB_JMP */ 178 _BM(7), _BM(5), _BM(6) /* _7, _5, _6 */ 179 -1, -1, /* DISP64, PLT64 */ 180 _BM(22), _BM(13), /* HIX22, LOX10 */ 181 _BM(22), _BM(10), _BM(13), /* H44, M44, L44 */ 182 -1, -1, _BM(16), /* REGISTER, UA64, UA16 */ 183 #undef _BM 184 }; 185 #define RELOC_VALUE_BITMASK(t) (reloc_target_bitmask[t]) 186 187 /* 188 * Instruction templates: 189 */ 190 #define BAA 0x10400000 /* ba,a %xcc, 0 */ 191 #define SETHI 0x03000000 /* sethi %hi(0), %g1 */ 192 #define JMP 0x81c06000 /* jmpl %g1+%lo(0), %g0 */ 193 #define NOP 0x01000000 /* sethi %hi(0), %g0 */ 194 #define OR 0x82806000 /* or %g1, 0, %g1 */ 195 #define XOR 0x82c06000 /* xor %g1, 0, %g1 */ 196 #define MOV71 0x8283a000 /* or %o7, 0, %g1 */ 197 #define MOV17 0x9c806000 /* or %g1, 0, %o7 */ 198 #define CALL 0x40000000 /* call 0 */ 199 #define SLLX 0x8b407000 /* sllx %g1, 0, %g1 */ 200 #define SETHIG5 0x0b000000 /* sethi %hi(0), %g5 */ 201 #define ORG5 0x82804005 /* or %g1, %g5, %g1 */ 202 203 204 /* %hi(v) with variable shift */ 205 #define HIVAL(v, s) (((v) >> (s)) & 0x003fffff) 206 #define LOVAL(v) ((v) & 0x000003ff) 207 208 void _rtld_bind_start_0(long, long); 209 void _rtld_bind_start_1(long, long); 210 void _rtld_relocate_nonplt_self(Elf_Dyn *, Elf_Addr); 211 caddr_t _rtld_bind __P((const Obj_Entry *, Elf_Word)); 212 213 /* 214 * Install rtld function call into this PLT slot. 215 */ 216 #define SAVE 0x9de3bf50 217 #define SETHI_l0 0x21000000 218 #define SETHI_l1 0x23000000 219 #define OR_l0_l0 0xa0142000 220 #define SLLX_l0_32_l0 0xa12c3020 221 #define OR_l0_l1_l0 0xa0140011 222 #define JMPL_l0_o1 0x93c42000 223 #define MOV_g1_o0 0x90100001 224 225 void _rtld_install_plt __P((Elf_Word *pltgot, Elf_Addr proc)); 226 227 void 228 _rtld_install_plt(pltgot, proc) 229 Elf_Word *pltgot; 230 Elf_Addr proc; 231 { 232 pltgot[0] = SAVE; 233 pltgot[1] = SETHI_l0 | HIVAL(proc, 42); 234 pltgot[2] = SETHI_l1 | HIVAL(proc, 10); 235 pltgot[3] = OR_l0_l0 | LOVAL((proc) >> 32); 236 pltgot[4] = SLLX_l0_32_l0; 237 pltgot[5] = OR_l0_l1_l0; 238 pltgot[6] = JMPL_l0_o1 | LOVAL(proc); 239 pltgot[7] = MOV_g1_o0; 240 } 241 242 long _rtld_bind_start_0_stub __P((long x, long y)); 243 long 244 _rtld_bind_start_0_stub(x, y) 245 long x, y; 246 { 247 long i; 248 long n; 249 250 i = x - y + 1048596; 251 n = 32768 + (i/5120)*160 + (i%5120)/24; 252 253 return (n); 254 } 255 256 void 257 _rtld_setup_pltgot(const Obj_Entry *obj) 258 { 259 /* 260 * On sparc64 we got troubles. 261 * 262 * Instructions are 4 bytes long. 263 * Elf[64]_Addr is 8 bytes long, so are our pltglot[] 264 * array entries. 265 * Each PLT entry jumps to PLT0 to enter the dynamic 266 * linker. 267 * Loading an arbitrary 64-bit pointer takes 6 268 * instructions and 2 registers. 269 * 270 * Somehow we need to issue a save to get a new stack 271 * frame, load the address of the dynamic linker, and 272 * jump there, in 8 instructions or less. 273 * 274 * Oh, we need to fill out both PLT0 and PLT1. 275 */ 276 { 277 Elf_Word *entry = (Elf_Word *)obj->pltgot; 278 279 /* Install in entries 0 and 1 */ 280 _rtld_install_plt(&entry[0], (Elf_Addr) &_rtld_bind_start_0); 281 _rtld_install_plt(&entry[8], (Elf_Addr) &_rtld_bind_start_1); 282 283 /* 284 * Install the object reference in first slot 285 * of entry 2. 286 */ 287 obj->pltgot[8] = (Elf_Addr) obj; 288 } 289 } 290 291 void 292 _rtld_relocate_nonplt_self(dynp, relocbase) 293 Elf_Dyn *dynp; 294 Elf_Addr relocbase; 295 { 296 const Elf_Rela *rela = 0, *relalim; 297 Elf_Addr relasz = 0; 298 Elf_Addr *where; 299 300 for (; dynp->d_tag != DT_NULL; dynp++) { 301 switch (dynp->d_tag) { 302 case DT_RELA: 303 rela = (const Elf_Rela *)(relocbase + dynp->d_un.d_ptr); 304 break; 305 case DT_RELASZ: 306 relasz = dynp->d_un.d_val; 307 break; 308 } 309 } 310 relalim = (const Elf_Rela *)((caddr_t)rela + relasz); 311 for (; rela < relalim; rela++) { 312 where = (Elf_Addr *)(relocbase + rela->r_offset); 313 *where = (Elf_Addr)(relocbase + rela->r_addend); 314 } 315 } 316 317 int 318 _rtld_relocate_nonplt_objects(obj, self) 319 const Obj_Entry *obj; 320 bool self; 321 { 322 const Elf_Rela *rela; 323 324 if (self) 325 return (0); 326 327 for (rela = obj->rela; rela < obj->relalim; rela++) { 328 Elf_Addr *where; 329 Elf_Word type; 330 Elf_Addr value = 0, mask; 331 const Elf_Sym *def = NULL; 332 const Obj_Entry *defobj = NULL; 333 unsigned long symnum; 334 335 where = (Elf_Addr *) (obj->relocbase + rela->r_offset); 336 symnum = ELF_R_SYM(rela->r_info); 337 338 type = ELF_R_TYPE(rela->r_info); 339 if (type == R_TYPE(NONE)) 340 continue; 341 342 /* We do JMP_SLOTs in _rtld_bind() below */ 343 if (type == R_TYPE(JMP_SLOT)) 344 continue; 345 346 /* COPY relocs are also handled elsewhere */ 347 if (type == R_TYPE(COPY)) 348 continue; 349 350 /* 351 * We use the fact that relocation types are an `enum' 352 * Note: R_SPARC_UA16 is currently numerically largest. 353 */ 354 if (type > R_TYPE(UA16)) 355 return (-1); 356 357 value = rela->r_addend; 358 359 /* 360 * Handle relative relocs here, as an optimization. 361 */ 362 if (type == R_TYPE(RELATIVE)) { 363 *where = (Elf_Addr)(obj->relocbase + value); 364 rdbg(("RELATIVE in %s --> %p", obj->path, 365 (void *)*where)); 366 continue; 367 } 368 369 if (RELOC_RESOLVE_SYMBOL(type)) { 370 371 /* Find the symbol */ 372 def = _rtld_find_symdef(symnum, obj, &defobj, false); 373 if (def == NULL) 374 return (-1); 375 376 /* Add in the symbol's absolute address */ 377 value += (Elf_Addr)(defobj->relocbase + def->st_value); 378 } 379 380 if (RELOC_PC_RELATIVE(type)) { 381 value -= (Elf_Addr)where; 382 } 383 384 if (RELOC_BASE_RELATIVE(type)) { 385 /* 386 * Note that even though sparcs use `Elf_rela' 387 * exclusively we still need the implicit memory addend 388 * in relocations referring to GOT entries. 389 * Undoubtedly, someone f*cked this up in the distant 390 * past, and now we're stuck with it in the name of 391 * compatibility for all eternity.. 392 * 393 * In any case, the implicit and explicit should be 394 * mutually exclusive. We provide a check for that 395 * here. 396 */ 397 #ifdef DIAGNOSTIC 398 if (value != 0 && *where != 0) { 399 xprintf("BASE_REL(%s): where=%p, *where 0x%lx, " 400 "addend=0x%lx, base %p\n", 401 obj->path, where, *where, 402 rela->r_addend, obj->relocbase); 403 } 404 #endif 405 /* XXXX -- apparently we ignore the preexisting value */ 406 value += (Elf_Addr)(obj->relocbase); 407 } 408 409 mask = RELOC_VALUE_BITMASK(type); 410 value >>= RELOC_VALUE_RIGHTSHIFT(type); 411 value &= mask; 412 413 if (RELOC_UNALIGNED(type)) { 414 /* Handle unaligned relocations. */ 415 Elf_Addr tmp = 0; 416 char *ptr = (char *)where; 417 int i, size = RELOC_TARGET_SIZE(type)/8; 418 419 /* Read it in one byte at a time. */ 420 for (i=0; i<size; i++) 421 tmp = (tmp << 8) | ptr[i]; 422 423 tmp &= ~mask; 424 tmp |= value; 425 426 /* Write it back out. */ 427 for (i=0; i<size; i++) 428 ptr[i] = ((tmp >> (8*i)) & 0xff); 429 #ifdef RTLD_DEBUG_RELOC 430 value = (Elf_Addr)tmp; 431 #endif 432 433 } else if (RELOC_TARGET_SIZE(type) > 32) { 434 *where &= ~mask; 435 *where |= value; 436 #ifdef RTLD_DEBUG_RELOC 437 value = (Elf_Addr)*where; 438 #endif 439 } else { 440 Elf32_Addr *where32 = (Elf32_Addr *)where; 441 442 *where32 &= ~mask; 443 *where32 |= value; 444 #ifdef RTLD_DEBUG_RELOC 445 value = (Elf_Addr)*where32; 446 #endif 447 } 448 449 #ifdef RTLD_DEBUG_RELOC 450 if (RELOC_RESOLVE_SYMBOL(type)) { 451 rdbg(("%s %s in %s --> %p in %s", reloc_names[type], 452 obj->strtab + obj->symtab[symnum].st_name, 453 obj->path, (void *)*where, defobj->path)); 454 } else { 455 rdbg(("%s in %s --> %p", reloc_names[type], 456 obj->path, (void *)*where)); 457 } 458 #endif 459 } 460 return (0); 461 } 462 463 int 464 _rtld_relocate_plt_lazy(obj) 465 const Obj_Entry *obj; 466 { 467 return (0); 468 } 469 470 caddr_t 471 _rtld_bind(obj, reloff) 472 const Obj_Entry *obj; 473 Elf_Word reloff; 474 { 475 const Elf_Rela *rela = obj->pltrela + reloff; 476 const Elf_Sym *def; 477 const Obj_Entry *defobj; 478 Elf_Addr *where = (Elf_Addr *)(obj->relocbase + rela->r_offset); 479 Elf_Addr value, offset; 480 481 if (ELF_R_TYPE(obj->pltrela->r_info) == R_TYPE(JMP_SLOT)) { 482 /* 483 * XXXX 484 * 485 * The first four PLT entries are reserved. There is some 486 * disagreement whether they should have associated relocation 487 * entries. Both the SPARC 32-bit and 64-bit ELF 488 * specifications say that they should have relocation entries, 489 * but the 32-bit SPARC binutils do not generate them, and now 490 * the 64-bit SPARC binutils have stopped generating them too. 491 * 492 * So, to provide binary compatibility, we will check the first 493 * entry, if it is reserved it should not be of the type 494 * JMP_SLOT. If it is JMP_SLOT, then the 4 reserved entries 495 * were not generated and our index is 4 entries too far. 496 */ 497 rela -= 4; 498 } 499 500 /* Fully resolve procedure addresses now */ 501 502 assert(ELF_R_TYPE(rela->r_info) == R_TYPE(JMP_SLOT)); 503 504 def = _rtld_find_symdef(ELF_R_SYM(rela->r_info), obj, &defobj, true); 505 if (def == NULL) 506 _rtld_die(); 507 508 value = (Elf_Addr)(defobj->relocbase + def->st_value); 509 rdbg(("bind now/fixup in %s --> old=%p new=%p", 510 defobj->strtab + def->st_name, (void *)*where, (void *)value)); 511 512 /* 513 * At the PLT entry pointed at by `where', we now construct 514 * a direct transfer to the now fully resolved function 515 * address. 516 * 517 * A PLT entry is supposed to start by looking like this: 518 * 519 * sethi %hi(. - .PLT0), %g1 520 * ba,a %xcc, .PLT1 521 * nop 522 * nop 523 * nop 524 * nop 525 * nop 526 * nop 527 * 528 * When we replace these entries we start from the second 529 * entry and do it in reverse order so the last thing we 530 * do is replace the branch. That allows us to change this 531 * atomically. 532 * 533 * We now need to find out how far we need to jump. We 534 * have a choice of several different relocation techniques 535 * which are increasingly expensive. 536 */ 537 538 offset = ((Elf_Addr)where) - value; 539 if (rela->r_addend) { 540 Elf_Addr *ptr = (Elf_Addr *)where; 541 /* 542 * This entry is >32768. Just replace the pointer. 543 */ 544 ptr[0] = value; 545 546 } else if (offset <= (1L<<20) && offset >= -(1L<<20)) { 547 /* 548 * We're within 1MB -- we can use a direct branch insn. 549 * 550 * We can generate this pattern: 551 * 552 * sethi %hi(. - .PLT0), %g1 553 * ba,a %xcc, addr 554 * nop 555 * nop 556 * nop 557 * nop 558 * nop 559 * nop 560 * 561 */ 562 where[1] = BAA | ((offset >> 2) &0x3fffff); 563 __asm __volatile("iflush %0+4" : : "r" (where)); 564 } else if (value >= 0 && value < (1L<<32)) { 565 /* 566 * We're withing 32-bits of address zero. 567 * 568 * The resulting code in the jump slot is: 569 * 570 * sethi %hi(. - .PLT0), %g1 571 * sethi %hi(addr), %g1 572 * jmp %g1+%lo(addr) 573 * nop 574 * nop 575 * nop 576 * nop 577 * nop 578 * 579 */ 580 where[2] = JMP | LOVAL(value); 581 where[1] = SETHI | HIVAL(value, 10); 582 __asm __volatile("iflush %0+8" : : "r" (where)); 583 __asm __volatile("iflush %0+4" : : "r" (where)); 584 585 } else if (value <= 0 && value > -(1L<<32)) { 586 /* 587 * We're withing 32-bits of address -1. 588 * 589 * The resulting code in the jump slot is: 590 * 591 * sethi %hi(. - .PLT0), %g1 592 * sethi %hix(addr), %g1 593 * xor %g1, %lox(addr), %g1 594 * jmp %g1 595 * nop 596 * nop 597 * nop 598 * nop 599 * 600 */ 601 where[3] = JMP; 602 where[2] = XOR | ((~value) & 0x00001fff); 603 where[1] = SETHI | HIVAL(~value, 10); 604 __asm __volatile("iflush %0+12" : : "r" (where)); 605 __asm __volatile("iflush %0+8" : : "r" (where)); 606 __asm __volatile("iflush %0+4" : : "r" (where)); 607 608 } else if (offset <= (1L<<32) && offset >= -((1L<<32) - 4)) { 609 /* 610 * We're withing 32-bits -- we can use a direct call insn 611 * 612 * The resulting code in the jump slot is: 613 * 614 * sethi %hi(. - .PLT0), %g1 615 * mov %o7, %g1 616 * call (.+offset) 617 * mov %g1, %o7 618 * nop 619 * nop 620 * nop 621 * nop 622 * 623 */ 624 where[3] = MOV17; 625 where[2] = CALL | ((offset >> 4) & 0x3fffffff); 626 where[1] = MOV71; 627 __asm __volatile("iflush %0+12" : : "r" (where)); 628 __asm __volatile("iflush %0+8" : : "r" (where)); 629 __asm __volatile("iflush %0+4" : : "r" (where)); 630 631 } else if (offset >= 0 && offset < (1L<<44)) { 632 /* 633 * We're withing 44 bits. We can generate this pattern: 634 * 635 * The resulting code in the jump slot is: 636 * 637 * sethi %hi(. - .PLT0), %g1 638 * sethi %h44(addr), %g1 639 * or %g1, %m44(addr), %g1 640 * sllx %g1, 12, %g1 641 * jmp %g1+%l44(addr) 642 * nop 643 * nop 644 * nop 645 * 646 */ 647 where[4] = JMP | LOVAL(offset); 648 where[3] = SLLX | 12; 649 where[2] = OR | (((offset) >> 12) & 0x00001fff); 650 where[1] = SETHI | HIVAL(offset, 22); 651 __asm __volatile("iflush %0+16" : : "r" (where)); 652 __asm __volatile("iflush %0+12" : : "r" (where)); 653 __asm __volatile("iflush %0+8" : : "r" (where)); 654 __asm __volatile("iflush %0+4" : : "r" (where)); 655 656 } else if (offset < 0 && offset > -(1L<<44)) { 657 /* 658 * We're withing 44 bits. We can generate this pattern: 659 * 660 * The resulting code in the jump slot is: 661 * 662 * sethi %hi(. - .PLT0), %g1 663 * sethi %h44(-addr), %g1 664 * xor %g1, %m44(-addr), %g1 665 * sllx %g1, 12, %g1 666 * jmp %g1+%l44(addr) 667 * nop 668 * nop 669 * nop 670 * 671 */ 672 where[4] = JMP | LOVAL(offset); 673 where[3] = SLLX | 12; 674 where[2] = XOR | (((~offset) >> 12) & 0x00001fff); 675 where[1] = SETHI | HIVAL(~offset, 22); 676 __asm __volatile("iflush %0+16" : : "r" (where)); 677 __asm __volatile("iflush %0+12" : : "r" (where)); 678 __asm __volatile("iflush %0+8" : : "r" (where)); 679 __asm __volatile("iflush %0+4" : : "r" (where)); 680 681 } else { 682 /* 683 * We need to load all 64-bits 684 * 685 * The resulting code in the jump slot is: 686 * 687 * sethi %hi(. - .PLT0), %g1 688 * sethi %hh(addr), %g1 689 * sethi %lm(addr), %g5 690 * or %g1, %hm(addr), %g1 691 * sllx %g1, 32, %g1 692 * or %g1, %g5, %g1 693 * jmp %g1+%lo(addr) 694 * nop 695 * 696 */ 697 where[6] = JMP | LOVAL(value); 698 where[5] = ORG5; 699 where[4] = SLLX | 12; 700 where[3] = OR | LOVAL((value) >> 32); 701 where[2] = SETHIG5 | HIVAL(value, 10); 702 where[1] = SETHI | HIVAL(value, 42); 703 __asm __volatile("iflush %0+20" : : "r" (where)); 704 __asm __volatile("iflush %0+16" : : "r" (where)); 705 __asm __volatile("iflush %0+16" : : "r" (where)); 706 __asm __volatile("iflush %0+12" : : "r" (where)); 707 __asm __volatile("iflush %0+8" : : "r" (where)); 708 __asm __volatile("iflush %0+4" : : "r" (where)); 709 710 } 711 712 return (caddr_t)value; 713 } 714
Indexes created Tue Sep 30 17:09:57 GMT 2025