gio.4 revision 1.16 $NetBSD: gio.4,v 1.16 2006/12/23 10:06:09 wiz Exp $
Copyright (c) 2002 The NetBSD Foundation, Inc.
All rights reserved.
This document is derived from work contributed to The NetBSD Foundation
by Antti Kantee.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement:
This product includes software developed by the NetBSD
Foundation, Inc. and its contributors.
4. Neither the name of The NetBSD Foundation nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.Dd December 23, 2006 .Dt GIO 4 sgimips .Os .Sh NAME .Nm gio .Nd SGI's Graphics I/O (GIO) bus - an early PCI-like bus .Sh SYNOPSIS .Cd "gio0 at imc0" .Cd "gio0 at pic0" .Sh DESCRIPTION The .Nm bus is a bus for connecting high-speed peripherals to the main memory and CPU. The devices themselves are typically (but not necessarily) connected to the .Xr hpc 4 peripheral controller, and memory and CPU are accessed through the .Xr imc 4 (Indy Memory Controller) or .Xr pic 4 (Processor Interface Controller). The .Nm bus is found on the Personal Iris 4D/3x, Indigo, Indy, Challenge S, Challenge M, and Indigo2 machines and exists in three incarnations: GIO32, GIO32-bis, and GIO64. .Sh SEE ALSO .Xr giopci 4 , .Xr grtwo 4 , .Xr hpc 4 , .Xr imc 4 , .Xr newport 4 , .Xr pic 4 .Sh HISTORY The .Nm driver first appeared in .Nx 1.5 . .Sh CAVEATS On Challenge S systems only one .Nm expansion slot may be used with a DMA-capable device. This is due to the fact that the IOPLUS board uses one of the slots' DMA channels for the additional .Xr sq 4 Ethernet. Which slot to use with a DMA-capable card depends on the card in question. HPC1.5-based cards, such as the E++ Ethernet Adapter and GIO32 SCSI Adapter, must be placed in slot 1 (next to the memory banks). All other DMA-capable boards must be placed in slot 0 (closest to the edge of the case). In either case the other slot may only accommodate a PIO card.
Copyright (c) 2002 The NetBSD Foundation, Inc.
All rights reserved.
This document is derived from work contributed to The NetBSD Foundation
by Antti Kantee.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement:
This product includes software developed by the NetBSD
Foundation, Inc. and its contributors.
4. Neither the name of The NetBSD Foundation nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
.Dd December 23, 2006 .Dt GIO 4 sgimips .Os .Sh NAME .Nm gio .Nd SGI's Graphics I/O (GIO) bus - an early PCI-like bus .Sh SYNOPSIS .Cd "gio0 at imc0" .Cd "gio0 at pic0" .Sh DESCRIPTION The .Nm bus is a bus for connecting high-speed peripherals to the main memory and CPU. The devices themselves are typically (but not necessarily) connected to the .Xr hpc 4 peripheral controller, and memory and CPU are accessed through the .Xr imc 4 (Indy Memory Controller) or .Xr pic 4 (Processor Interface Controller). The .Nm bus is found on the Personal Iris 4D/3x, Indigo, Indy, Challenge S, Challenge M, and Indigo2 machines and exists in three incarnations: GIO32, GIO32-bis, and GIO64. .Sh SEE ALSO .Xr giopci 4 , .Xr grtwo 4 , .Xr hpc 4 , .Xr imc 4 , .Xr newport 4 , .Xr pic 4 .Sh HISTORY The .Nm driver first appeared in .Nx 1.5 . .Sh CAVEATS On Challenge S systems only one .Nm expansion slot may be used with a DMA-capable device. This is due to the fact that the IOPLUS board uses one of the slots' DMA channels for the additional .Xr sq 4 Ethernet. Which slot to use with a DMA-capable card depends on the card in question. HPC1.5-based cards, such as the E++ Ethernet Adapter and GIO32 SCSI Adapter, must be placed in slot 1 (next to the memory banks). All other DMA-capable boards must be placed in slot 0 (closest to the edge of the case). In either case the other slot may only accommodate a PIO card.
p Indigo2 and Challenge M systems contain either three or four GIO64 connectors, depending on the model. However, in both cases only two electrically distinct slots are present. Therefore, distinct expansion cards may not share physical connectors associated with the same slot. Refer to the PCB stencils to determine the association between physical connectors and slots. .Sh BUGS Systems employing the .Xr imc 4 may experience spurious SysAD bus parity errors when using expansion cards, which do not drive all data lines during a CPU PIO read. The only workaround is to disable SysAD parity checking when using such cards.
Indexes created Sun Oct 19 02:09:48 GMT 2025