trap.c revision 1.28
1 /* $NetBSD: trap.c,v 1.28 2020/07/01 08:01:07 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.28 2020/07/01 08:01:07 ryo Exp $"); 35 36 #include "opt_arm_intr_impl.h" 37 #include "opt_compat_netbsd32.h" 38 #include "opt_dtrace.h" 39 40 #include <sys/param.h> 41 #include <sys/kauth.h> 42 #include <sys/types.h> 43 #include <sys/atomic.h> 44 #include <sys/cpu.h> 45 #include <sys/evcnt.h> 46 #ifdef KDB 47 #include <sys/kdb.h> 48 #endif 49 #include <sys/proc.h> 50 #include <sys/systm.h> 51 #include <sys/signal.h> 52 #include <sys/signalvar.h> 53 #include <sys/siginfo.h> 54 #include <sys/xcall.h> 55 56 #ifdef ARM_INTR_IMPL 57 #include ARM_INTR_IMPL 58 #else 59 #error ARM_INTR_IMPL not defined 60 #endif 61 62 #ifndef ARM_IRQ_HANDLER 63 #error ARM_IRQ_HANDLER not defined 64 #endif 65 66 #include <aarch64/userret.h> 67 #include <aarch64/frame.h> 68 #include <aarch64/machdep.h> 69 #include <aarch64/armreg.h> 70 #include <aarch64/locore.h> 71 72 #ifdef KDB 73 #include <machine/db_machdep.h> 74 #endif 75 #ifdef DDB 76 #include <ddb/db_output.h> 77 #include <machine/db_machdep.h> 78 #endif 79 #ifdef KDTRACE_HOOKS 80 #include <sys/dtrace_bsd.h> 81 #endif 82 83 #ifdef DDB 84 int sigill_debug = 0; 85 #endif 86 87 #ifdef KDTRACE_HOOKS 88 dtrace_doubletrap_func_t dtrace_doubletrap_func = NULL; 89 dtrace_trap_func_t dtrace_trap_func = NULL; 90 int (*dtrace_invop_jump_addr)(struct trapframe *); 91 #endif 92 93 enum emul_arm_result { 94 EMUL_ARM_SUCCESS = 0, 95 EMUL_ARM_UNKNOWN, 96 EMUL_ARM_FAULT, 97 }; 98 99 const char * const trap_names[] = { 100 [ESR_EC_UNKNOWN] = "Unknown Reason (Illegal Instruction)", 101 [ESR_EC_SERROR] = "SError Interrupt", 102 [ESR_EC_WFX] = "WFI or WFE instruction execution", 103 [ESR_EC_ILL_STATE] = "Illegal Execution State", 104 105 [ESR_EC_BTE_A64] = "Branch Target Exception", 106 107 [ESR_EC_SYS_REG] = "MSR/MRS/SYS instruction", 108 [ESR_EC_SVC_A64] = "SVC Instruction Execution", 109 [ESR_EC_HVC_A64] = "HVC Instruction Execution", 110 [ESR_EC_SMC_A64] = "SMC Instruction Execution", 111 112 [ESR_EC_INSN_ABT_EL0] = "Instruction Abort (EL0)", 113 [ESR_EC_INSN_ABT_EL1] = "Instruction Abort (EL1)", 114 [ESR_EC_DATA_ABT_EL0] = "Data Abort (EL0)", 115 [ESR_EC_DATA_ABT_EL1] = "Data Abort (EL1)", 116 117 [ESR_EC_PC_ALIGNMENT] = "Misaligned PC", 118 [ESR_EC_SP_ALIGNMENT] = "Misaligned SP", 119 120 [ESR_EC_FP_ACCESS] = "Access to SIMD/FP Registers", 121 [ESR_EC_FP_TRAP_A64] = "FP Exception", 122 123 [ESR_EC_BRKPNT_EL0] = "Breakpoint Exception (EL0)", 124 [ESR_EC_BRKPNT_EL1] = "Breakpoint Exception (EL1)", 125 [ESR_EC_SW_STEP_EL0] = "Software Step (EL0)", 126 [ESR_EC_SW_STEP_EL1] = "Software Step (EL1)", 127 [ESR_EC_WTCHPNT_EL0] = "Watchpoint (EL0)", 128 [ESR_EC_WTCHPNT_EL1] = "Watchpoint (EL1)", 129 [ESR_EC_BKPT_INSN_A64] = "BKPT Instruction Execution", 130 131 [ESR_EC_CP15_RT] = "A32: MCR/MRC access to CP15", 132 [ESR_EC_CP15_RRT] = "A32: MCRR/MRRC access to CP15", 133 [ESR_EC_CP14_RT] = "A32: MCR/MRC access to CP14", 134 [ESR_EC_CP14_DT] = "A32: LDC/STC access to CP14", 135 [ESR_EC_CP14_RRT] = "A32: MRRC access to CP14", 136 [ESR_EC_SVC_A32] = "A32: SVC Instruction Execution", 137 [ESR_EC_HVC_A32] = "A32: HVC Instruction Execution", 138 [ESR_EC_SMC_A32] = "A32: SMC Instruction Execution", 139 [ESR_EC_FPID] = "A32: MCR/MRC access to CP10", 140 [ESR_EC_FP_TRAP_A32] = "A32: FP Exception", 141 [ESR_EC_BKPT_INSN_A32] = "A32: BKPT Instruction Execution", 142 [ESR_EC_VECTOR_CATCH] = "A32: Vector Catch Exception" 143 }; 144 145 const char * 146 eclass_trapname(uint32_t eclass) 147 { 148 static char trapnamebuf[sizeof("Unknown trap 0x????????")]; 149 150 if (eclass >= __arraycount(trap_names) || trap_names[eclass] == NULL) { 151 snprintf(trapnamebuf, sizeof(trapnamebuf), 152 "Unknown trap %#02x", eclass); 153 return trapnamebuf; 154 } 155 return trap_names[eclass]; 156 } 157 158 void 159 userret(struct lwp *l) 160 { 161 mi_userret(l); 162 } 163 164 void 165 trap_doast(struct trapframe *tf) 166 { 167 struct lwp * const l = curlwp; 168 169 /* 170 * allow to have a chance of context switch just prior to user 171 * exception return. 172 */ 173 #ifdef __HAVE_PREEMPTION 174 kpreempt_disable(); 175 #endif 176 struct cpu_info * const ci = curcpu(); 177 178 ci->ci_data.cpu_ntrap++; 179 180 KDASSERT(ci->ci_cpl == IPL_NONE); 181 #ifdef __HAVE_PREEMPTION 182 kpreempt_enable(); 183 #endif 184 185 if (l->l_pflag & LP_OWEUPC) { 186 l->l_pflag &= ~LP_OWEUPC; 187 ADDUPROF(l); 188 } 189 190 userret(l); 191 } 192 193 void 194 trap_el1h_sync(struct trapframe *tf) 195 { 196 const uint32_t esr = tf->tf_esr; 197 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 198 199 /* re-enable traps and interrupts */ 200 if (!(tf->tf_spsr & SPSR_I)) 201 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 202 else 203 daif_enable(DAIF_D|DAIF_A); 204 205 #ifdef KDTRACE_HOOKS 206 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(tf, eclass)) 207 return; 208 #endif 209 210 switch (eclass) { 211 case ESR_EC_INSN_ABT_EL1: 212 case ESR_EC_DATA_ABT_EL1: 213 data_abort_handler(tf, eclass); 214 break; 215 216 case ESR_EC_BKPT_INSN_A64: 217 #ifdef KDTRACE_HOOKS 218 if (__SHIFTOUT(esr, ESR_ISS) == 0x40d && 219 dtrace_invop_jump_addr != 0) { 220 (*dtrace_invop_jump_addr)(tf); 221 break; 222 } 223 /* FALLTHROUGH */ 224 #endif 225 case ESR_EC_BRKPNT_EL1: 226 case ESR_EC_SW_STEP_EL1: 227 case ESR_EC_WTCHPNT_EL1: 228 #ifdef DDB 229 if (eclass == ESR_EC_BRKPNT_EL1) 230 kdb_trap(DB_TRAP_BREAKPOINT, tf); 231 else if (eclass == ESR_EC_BKPT_INSN_A64) 232 kdb_trap(DB_TRAP_BKPT_INSN, tf); 233 else if (eclass == ESR_EC_WTCHPNT_EL1) 234 kdb_trap(DB_TRAP_WATCHPOINT, tf); 235 else if (eclass == ESR_EC_SW_STEP_EL1) 236 kdb_trap(DB_TRAP_SW_STEP, tf); 237 else 238 kdb_trap(DB_TRAP_UNKNOWN, tf); 239 #else 240 panic("No debugger in kernel"); 241 #endif 242 break; 243 244 case ESR_EC_FP_ACCESS: 245 case ESR_EC_FP_TRAP_A64: 246 case ESR_EC_PC_ALIGNMENT: 247 case ESR_EC_SP_ALIGNMENT: 248 case ESR_EC_ILL_STATE: 249 case ESR_EC_BTE_A64: 250 default: 251 panic("Trap: fatal %s: pc=%016" PRIx64 " sp=%016" PRIx64 252 " esr=%08x", eclass_trapname(eclass), tf->tf_pc, tf->tf_sp, 253 esr); 254 break; 255 } 256 } 257 258 /* 259 * There are some systems with different cache line sizes for each cpu. 260 * Userland programs can be preempted between CPUs at any time, so in such 261 * a system, the minimum cache line size must be visible to userland. 262 */ 263 #define CTR_EL0_USR_MASK \ 264 (CTR_EL0_DIC | CTR_EL0_IDC | CTR_EL0_DMIN_LINE | CTR_EL0_IMIN_LINE) 265 uint64_t ctr_el0_usr __read_mostly; 266 267 static xcfunc_t 268 configure_cpu_traps0(void *arg1, void *arg2) 269 { 270 struct cpu_info * const ci = curcpu(); 271 uint64_t sctlr; 272 uint64_t ctr_el0_raw = reg_ctr_el0_read(); 273 274 #ifdef DEBUG_FORCE_TRAP_CTR_EL0 275 goto need_ctr_trap; 276 #endif 277 278 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DMIN_LINE) > 279 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) || 280 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IMIN_LINE) > 281 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) 282 goto need_ctr_trap; 283 284 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DIC) == 1 && 285 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DIC) == 0) || 286 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 1 && 287 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 0)) 288 goto need_ctr_trap; 289 290 #if 0 /* XXX: To do or not to do */ 291 /* 292 * IDC==0, but (LoC==0 || LoUIS==LoUU==0)? 293 * Would it be better to show IDC=1 to userland? 294 */ 295 if (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 0 && 296 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 1) 297 goto need_ctr_trap; 298 #endif 299 300 return 0; 301 302 need_ctr_trap: 303 evcnt_attach_dynamic(&ci->ci_uct_trap, EVCNT_TYPE_MISC, NULL, 304 ci->ci_cpuname, "ctr_el0 trap"); 305 306 /* trap CTR_EL0 access from EL0 on this cpu */ 307 sctlr = reg_sctlr_el1_read(); 308 sctlr &= ~SCTLR_UCT; 309 reg_sctlr_el1_write(sctlr); 310 311 return 0; 312 } 313 314 void 315 configure_cpu_traps(void) 316 { 317 CPU_INFO_ITERATOR cii; 318 struct cpu_info *ci; 319 uint64_t where; 320 321 /* remember minimum cache line size out of all CPUs */ 322 for (CPU_INFO_FOREACH(cii, ci)) { 323 uint64_t ctr_el0_cpu = ci->ci_id.ac_ctr; 324 uint64_t clidr = ci->ci_id.ac_clidr; 325 326 if (__SHIFTOUT(clidr, CLIDR_LOC) == 0 || 327 (__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 && 328 __SHIFTOUT(clidr, CLIDR_LOUU) == 0)) { 329 /* this means the same as IDC=1 */ 330 ctr_el0_cpu |= CTR_EL0_IDC; 331 } 332 333 /* 334 * if DIC==1, there is no need to icache sync. however, 335 * to calculate the minimum cacheline, in this case 336 * ICacheLine is treated as the maximum. 337 */ 338 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1) 339 ctr_el0_cpu |= CTR_EL0_IMIN_LINE; 340 341 if (cii == 0) { 342 ctr_el0_usr = ctr_el0_cpu; 343 continue; 344 } 345 346 /* keep minimum cache line size, and worst DIC/IDC */ 347 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_DIC) | ~CTR_EL0_DIC; 348 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_IDC) | ~CTR_EL0_IDC; 349 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DMIN_LINE) < 350 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) { 351 ctr_el0_usr &= ~CTR_EL0_DMIN_LINE; 352 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_DMIN_LINE; 353 } 354 if ((ctr_el0_cpu & CTR_EL0_DIC) == 0 && 355 (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_IMIN_LINE) < 356 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) { 357 ctr_el0_usr &= ~CTR_EL0_IMIN_LINE; 358 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_IMIN_LINE; 359 } 360 } 361 362 where = xc_broadcast(0, 363 (xcfunc_t)configure_cpu_traps0, NULL, NULL); 364 xc_wait(where); 365 } 366 367 static enum emul_arm_result 368 emul_aarch64_insn(struct trapframe *tf) 369 { 370 uint32_t insn; 371 372 if (ufetch_32((uint32_t *)tf->tf_pc, &insn)) 373 return EMUL_ARM_FAULT; 374 375 if ((insn & 0xffffffe0) == 0xd53b0020) { 376 /* mrs x?,ctr_el0 */ 377 unsigned int Xt = insn & 31; 378 if (Xt != 31) { /* !xzr */ 379 uint64_t ctr_el0 = reg_ctr_el0_read(); 380 ctr_el0 &= ~CTR_EL0_USR_MASK; 381 ctr_el0 |= (ctr_el0_usr & CTR_EL0_USR_MASK); 382 tf->tf_reg[Xt] = ctr_el0; 383 } 384 curcpu()->ci_uct_trap.ev_count++; 385 386 } else { 387 return EMUL_ARM_UNKNOWN; 388 } 389 390 tf->tf_pc += 4; 391 return EMUL_ARM_SUCCESS; 392 } 393 394 void 395 trap_el0_sync(struct trapframe *tf) 396 { 397 struct lwp * const l = curlwp; 398 const uint32_t esr = tf->tf_esr; 399 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 400 401 /* disable trace */ 402 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 403 /* enable traps and interrupts */ 404 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 405 406 switch (eclass) { 407 case ESR_EC_INSN_ABT_EL0: 408 case ESR_EC_DATA_ABT_EL0: 409 data_abort_handler(tf, eclass); 410 userret(l); 411 break; 412 413 case ESR_EC_SVC_A64: 414 (*l->l_proc->p_md.md_syscall)(tf); 415 break; 416 case ESR_EC_FP_ACCESS: 417 fpu_load(l); 418 userret(l); 419 break; 420 case ESR_EC_FP_TRAP_A64: 421 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 422 userret(l); 423 break; 424 425 case ESR_EC_PC_ALIGNMENT: 426 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 427 userret(l); 428 break; 429 case ESR_EC_SP_ALIGNMENT: 430 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr); 431 userret(l); 432 break; 433 434 case ESR_EC_BKPT_INSN_A64: 435 case ESR_EC_BRKPNT_EL0: 436 case ESR_EC_WTCHPNT_EL0: 437 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 438 userret(l); 439 break; 440 case ESR_EC_SW_STEP_EL0: 441 /* disable trace, and send trace trap */ 442 tf->tf_spsr &= ~SPSR_SS; 443 do_trapsignal(l, SIGTRAP, TRAP_TRACE, (void *)tf->tf_pc, esr); 444 userret(l); 445 break; 446 447 case ESR_EC_SYS_REG: 448 switch (emul_aarch64_insn(tf)) { 449 case EMUL_ARM_SUCCESS: 450 break; 451 case EMUL_ARM_UNKNOWN: 452 goto unknown; 453 case EMUL_ARM_FAULT: 454 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 455 (void *)tf->tf_pc, esr); 456 break; 457 } 458 userret(l); 459 break; 460 461 default: 462 case ESR_EC_UNKNOWN: 463 unknown: 464 #ifdef DDB 465 if (sigill_debug) { 466 /* show illegal instruction */ 467 printf("TRAP: pid %d (%s), uid %d: %s:" 468 " esr=0x%lx: pc=0x%lx: %s\n", 469 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 470 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 471 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 472 strdisasm(tf->tf_pc)); 473 } 474 #endif 475 /* illegal or not implemented instruction */ 476 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 477 userret(l); 478 break; 479 } 480 } 481 482 void 483 interrupt(struct trapframe *tf) 484 { 485 struct cpu_info * const ci = curcpu(); 486 487 #ifdef STACKCHECKS 488 struct lwp *l = curlwp; 489 void *sp = (void *)reg_sp_read(); 490 if (l->l_addr >= sp) { 491 panic("lwp/interrupt stack overflow detected." 492 " lwp=%p, sp=%p, l_addr=%p", l, sp, l->l_addr); 493 } 494 #endif 495 496 /* disable trace */ 497 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 498 499 /* enable traps */ 500 daif_enable(DAIF_D|DAIF_A); 501 502 ci->ci_intr_depth++; 503 ARM_IRQ_HANDLER(tf); 504 ci->ci_intr_depth--; 505 506 cpu_dosoftints(); 507 } 508 509 #ifdef COMPAT_NETBSD32 510 511 /* 512 * 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3. 513 */ 514 #define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && ((hi) & 0x1800)) 515 516 static int 517 fetch_arm_insn(struct trapframe *tf, uint32_t *insn) 518 { 519 520 /* THUMB? */ 521 if (tf->tf_spsr & SPSR_A32_T) { 522 uint16_t *pc = (uint16_t *)(tf->tf_pc & ~1UL); /* XXX */ 523 uint16_t hi, lo; 524 525 if (ufetch_16(pc, &hi)) 526 return -1; 527 528 if (!THUMB_32BIT(hi)) { 529 /* 16-bit Thumb instruction */ 530 *insn = hi; 531 return 2; 532 } 533 534 /* 32-bit Thumb instruction */ 535 if (ufetch_16(pc + 1, &lo)) 536 return -1; 537 538 *insn = ((uint32_t)hi << 16) | lo; 539 return 4; 540 } 541 542 if (ufetch_32((uint32_t *)tf->tf_pc, insn)) 543 return -1; 544 545 return 4; 546 } 547 548 static enum emul_arm_result 549 emul_arm_insn(struct trapframe *tf) 550 { 551 uint32_t insn; 552 int insn_size; 553 554 insn_size = fetch_arm_insn(tf, &insn); 555 556 switch (insn_size) { 557 case 2: 558 /* T32-16bit instruction */ 559 560 /* XXX: some T32 IT instruction deprecated should be emulated */ 561 break; 562 case 4: 563 /* T32-32bit instruction, or A32 instruction */ 564 565 /* 566 * Emulate ARMv6 instructions with cache operations 567 * register (c7), that can be used in user mode. 568 */ 569 switch (insn & 0x0fff0fff) { 570 case 0x0e070f95: 571 /* 572 * mcr p15, 0, <Rd>, c7, c5, 4 573 * (flush prefetch buffer) 574 */ 575 __asm __volatile("isb sy" ::: "memory"); 576 goto emulated; 577 case 0x0e070f9a: 578 /* 579 * mcr p15, 0, <Rd>, c7, c10, 4 580 * (data synchronization barrier) 581 */ 582 __asm __volatile("dsb sy" ::: "memory"); 583 goto emulated; 584 case 0x0e070fba: 585 /* 586 * mcr p15, 0, <Rd>, c7, c10, 5 587 * (data memory barrier) 588 */ 589 __asm __volatile("dmb sy" ::: "memory"); 590 goto emulated; 591 default: 592 break; 593 } 594 break; 595 default: 596 return EMUL_ARM_FAULT; 597 } 598 599 /* unknown, or unsupported instruction */ 600 return EMUL_ARM_UNKNOWN; 601 602 emulated: 603 tf->tf_pc += insn_size; 604 return EMUL_ARM_SUCCESS; 605 } 606 #endif /* COMPAT_NETBSD32 */ 607 608 void 609 trap_el0_32sync(struct trapframe *tf) 610 { 611 struct lwp * const l = curlwp; 612 const uint32_t esr = tf->tf_esr; 613 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 614 615 /* disable trace */ 616 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 617 /* enable traps and interrupts */ 618 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 619 620 switch (eclass) { 621 #ifdef COMPAT_NETBSD32 622 case ESR_EC_INSN_ABT_EL0: 623 case ESR_EC_DATA_ABT_EL0: 624 data_abort_handler(tf, eclass); 625 userret(l); 626 break; 627 628 case ESR_EC_SVC_A32: 629 (*l->l_proc->p_md.md_syscall)(tf); 630 break; 631 632 case ESR_EC_FP_ACCESS: 633 fpu_load(l); 634 userret(l); 635 break; 636 637 case ESR_EC_FP_TRAP_A32: 638 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 639 userret(l); 640 break; 641 642 case ESR_EC_PC_ALIGNMENT: 643 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 644 userret(l); 645 break; 646 647 case ESR_EC_SP_ALIGNMENT: 648 do_trapsignal(l, SIGBUS, BUS_ADRALN, 649 (void *)tf->tf_reg[13], esr); /* sp is r13 on AArch32 */ 650 userret(l); 651 break; 652 653 case ESR_EC_BKPT_INSN_A32: 654 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 655 userret(l); 656 break; 657 658 case ESR_EC_UNKNOWN: 659 switch (emul_arm_insn(tf)) { 660 case EMUL_ARM_SUCCESS: 661 break; 662 case EMUL_ARM_UNKNOWN: 663 goto unknown; 664 case EMUL_ARM_FAULT: 665 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 666 (void *)tf->tf_pc, esr); 667 break; 668 } 669 userret(l); 670 break; 671 672 case ESR_EC_CP15_RT: 673 case ESR_EC_CP15_RRT: 674 case ESR_EC_CP14_RT: 675 case ESR_EC_CP14_DT: 676 case ESR_EC_CP14_RRT: 677 unknown: 678 #endif /* COMPAT_NETBSD32 */ 679 default: 680 #ifdef DDB 681 if (sigill_debug) { 682 /* show illegal instruction */ 683 printf("TRAP: pid %d (%s), uid %d: %s:" 684 " esr=0x%lx: pc=0x%lx: %s\n", 685 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 686 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 687 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 688 strdisasm_aarch32(tf->tf_pc)); 689 } 690 #endif 691 /* illegal or not implemented instruction */ 692 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 693 userret(l); 694 break; 695 } 696 } 697 698 #define bad_trap_panic(trapfunc) \ 699 void \ 700 trapfunc(struct trapframe *tf) \ 701 { \ 702 panic("%s", __func__); \ 703 } 704 bad_trap_panic(trap_el1t_sync) 705 bad_trap_panic(trap_el1t_irq) 706 bad_trap_panic(trap_el1t_fiq) 707 bad_trap_panic(trap_el1t_error) 708 bad_trap_panic(trap_el1h_fiq) 709 bad_trap_panic(trap_el1h_error) 710 bad_trap_panic(trap_el0_fiq) 711 bad_trap_panic(trap_el0_error) 712 bad_trap_panic(trap_el0_32fiq) 713 bad_trap_panic(trap_el0_32error) 714 715 void 716 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int val) 717 { 718 tf->tf_reg[19] = fb->fb_reg[FB_X19]; 719 tf->tf_reg[20] = fb->fb_reg[FB_X20]; 720 tf->tf_reg[21] = fb->fb_reg[FB_X21]; 721 tf->tf_reg[22] = fb->fb_reg[FB_X22]; 722 tf->tf_reg[23] = fb->fb_reg[FB_X23]; 723 tf->tf_reg[24] = fb->fb_reg[FB_X24]; 724 tf->tf_reg[25] = fb->fb_reg[FB_X25]; 725 tf->tf_reg[26] = fb->fb_reg[FB_X26]; 726 tf->tf_reg[27] = fb->fb_reg[FB_X27]; 727 tf->tf_reg[28] = fb->fb_reg[FB_X28]; 728 tf->tf_reg[29] = fb->fb_reg[FB_X29]; 729 tf->tf_sp = fb->fb_reg[FB_SP]; 730 tf->tf_pc = fb->fb_reg[FB_LR]; 731 tf->tf_reg[0] = val; 732 } 733 734 #ifdef TRAP_SIGDEBUG 735 static void 736 frame_dump(const struct trapframe *tf) 737 { 738 const struct reg *r = &tf->tf_regs; 739 740 printf("trapframe %p\n", tf); 741 for (size_t i = 0; i < __arraycount(r->r_reg); i++) { 742 printf(" r%.2zu %#018" PRIx64 "%c", i, r->r_reg[i], 743 " \n"[i && (i & 1) == 0]); 744 } 745 746 printf("\n"); 747 printf(" sp %#018" PRIx64 " pc %#018" PRIx64 "\n", 748 r->r_sp, r->r_pc); 749 printf(" spsr %#018" PRIx64 " tpidr %#018" PRIx64 "\n", 750 r->r_spsr, r->r_tpidr); 751 printf(" esr %#018" PRIx64 " far %#018" PRIx64 "\n", 752 tf->tf_esr, tf->tf_far); 753 754 printf("\n"); 755 hexdump(printf, "Stack dump", tf, 256); 756 } 757 758 static void 759 sigdebug(const struct trapframe *tf, const ksiginfo_t *ksi) 760 { 761 struct lwp *l = curlwp; 762 struct proc *p = l->l_proc; 763 const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC); 764 765 printf("pid %d.%d (%s): signal %d (trap %#x) " 766 "@pc %#" PRIx64 ", addr %p, error=%s\n", 767 p->p_pid, l->l_lid, p->p_comm, ksi->ksi_signo, ksi->ksi_trap, 768 tf->tf_regs.r_pc, ksi->ksi_addr, eclass_trapname(eclass)); 769 frame_dump(tf); 770 } 771 #endif 772 773 void do_trapsignal1( 774 #ifdef TRAP_SIGDEBUG 775 const char *func, 776 size_t line, 777 struct trapframe *tf, 778 #endif 779 struct lwp *l, int signo, int code, void *addr, int trap) 780 { 781 ksiginfo_t ksi; 782 783 KSI_INIT_TRAP(&ksi); 784 ksi.ksi_signo = signo; 785 ksi.ksi_code = code; 786 ksi.ksi_addr = addr; 787 ksi.ksi_trap = trap; 788 #ifdef TRAP_SIGDEBUG 789 printf("%s, %zu: ", func, line); 790 sigdebug(tf, &ksi); 791 #endif 792 (*l->l_proc->p_emul->e_trapsignal)(l, &ksi); 793 } 794 795 bool 796 cpu_intr_p(void) 797 { 798 uint64_t ncsw; 799 int idepth; 800 lwp_t *l; 801 802 #ifdef __HAVE_PIC_FAST_SOFTINTS 803 /* XXX Copied from cpu.h. Looks incomplete - needs fixing. */ 804 if (ci->ci_cpl < IPL_VM) 805 return false; 806 #endif 807 808 l = curlwp; 809 if (__predict_false(l->l_cpu == NULL)) { 810 KASSERT(l == &lwp0); 811 return false; 812 } 813 do { 814 ncsw = l->l_ncsw; 815 __insn_barrier(); 816 idepth = l->l_cpu->ci_intr_depth; 817 __insn_barrier(); 818 } while (__predict_false(ncsw != l->l_ncsw)); 819 820 return idepth > 0; 821 } 822
Indexes created Sun Oct 19 02:09:48 GMT 2025