trap.c revision 1.44
1 /* $NetBSD: trap.c,v 1.44 2021/02/22 02:18:33 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.44 2021/02/22 02:18:33 jmcneill Exp $"); 35 36 #include "opt_arm_intr_impl.h" 37 #include "opt_compat_netbsd32.h" 38 #include "opt_dtrace.h" 39 40 #include <sys/param.h> 41 #include <sys/kauth.h> 42 #include <sys/types.h> 43 #include <sys/atomic.h> 44 #include <sys/cpu.h> 45 #include <sys/evcnt.h> 46 #ifdef KDB 47 #include <sys/kdb.h> 48 #endif 49 #include <sys/proc.h> 50 #include <sys/systm.h> 51 #include <sys/signal.h> 52 #include <sys/signalvar.h> 53 #include <sys/siginfo.h> 54 #include <sys/xcall.h> 55 56 #ifdef ARM_INTR_IMPL 57 #include ARM_INTR_IMPL 58 #else 59 #error ARM_INTR_IMPL not defined 60 #endif 61 62 #ifndef ARM_IRQ_HANDLER 63 #error ARM_IRQ_HANDLER not defined 64 #endif 65 66 #include <arm/cpufunc.h> 67 68 #include <aarch64/userret.h> 69 #include <aarch64/frame.h> 70 #include <aarch64/machdep.h> 71 #include <aarch64/armreg.h> 72 #include <aarch64/locore.h> 73 74 #include <arm/cpufunc.h> 75 76 #ifdef KDB 77 #include <machine/db_machdep.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/db_output.h> 81 #include <machine/db_machdep.h> 82 #endif 83 #ifdef KDTRACE_HOOKS 84 #include <sys/dtrace_bsd.h> 85 #endif 86 87 #ifdef DDB 88 int sigill_debug = 0; 89 #endif 90 91 #ifdef KDTRACE_HOOKS 92 dtrace_doubletrap_func_t dtrace_doubletrap_func = NULL; 93 dtrace_trap_func_t dtrace_trap_func = NULL; 94 int (*dtrace_invop_jump_addr)(struct trapframe *); 95 #endif 96 97 enum emul_arm_result { 98 EMUL_ARM_SUCCESS = 0, 99 EMUL_ARM_UNKNOWN, 100 EMUL_ARM_FAULT, 101 }; 102 103 const char * const trap_names[] = { 104 [ESR_EC_UNKNOWN] = "Unknown Reason (Illegal Instruction)", 105 [ESR_EC_SERROR] = "SError Interrupt", 106 [ESR_EC_WFX] = "WFI or WFE instruction execution", 107 [ESR_EC_ILL_STATE] = "Illegal Execution State", 108 109 [ESR_EC_BTE_A64] = "Branch Target Exception", 110 111 [ESR_EC_SYS_REG] = "MSR/MRS/SYS instruction", 112 [ESR_EC_SVC_A64] = "SVC Instruction Execution", 113 [ESR_EC_HVC_A64] = "HVC Instruction Execution", 114 [ESR_EC_SMC_A64] = "SMC Instruction Execution", 115 116 [ESR_EC_INSN_ABT_EL0] = "Instruction Abort (EL0)", 117 [ESR_EC_INSN_ABT_EL1] = "Instruction Abort (EL1)", 118 [ESR_EC_DATA_ABT_EL0] = "Data Abort (EL0)", 119 [ESR_EC_DATA_ABT_EL1] = "Data Abort (EL1)", 120 121 [ESR_EC_PC_ALIGNMENT] = "Misaligned PC", 122 [ESR_EC_SP_ALIGNMENT] = "Misaligned SP", 123 124 [ESR_EC_FP_ACCESS] = "Access to SIMD/FP Registers", 125 [ESR_EC_FP_TRAP_A64] = "FP Exception", 126 127 [ESR_EC_BRKPNT_EL0] = "Breakpoint Exception (EL0)", 128 [ESR_EC_BRKPNT_EL1] = "Breakpoint Exception (EL1)", 129 [ESR_EC_SW_STEP_EL0] = "Software Step (EL0)", 130 [ESR_EC_SW_STEP_EL1] = "Software Step (EL1)", 131 [ESR_EC_WTCHPNT_EL0] = "Watchpoint (EL0)", 132 [ESR_EC_WTCHPNT_EL1] = "Watchpoint (EL1)", 133 [ESR_EC_BKPT_INSN_A64] = "BKPT Instruction Execution", 134 135 [ESR_EC_CP15_RT] = "A32: MCR/MRC access to CP15", 136 [ESR_EC_CP15_RRT] = "A32: MCRR/MRRC access to CP15", 137 [ESR_EC_CP14_RT] = "A32: MCR/MRC access to CP14", 138 [ESR_EC_CP14_DT] = "A32: LDC/STC access to CP14", 139 [ESR_EC_CP14_RRT] = "A32: MRRC access to CP14", 140 [ESR_EC_SVC_A32] = "A32: SVC Instruction Execution", 141 [ESR_EC_HVC_A32] = "A32: HVC Instruction Execution", 142 [ESR_EC_SMC_A32] = "A32: SMC Instruction Execution", 143 [ESR_EC_FPID] = "A32: MCR/MRC access to CP10", 144 [ESR_EC_FP_TRAP_A32] = "A32: FP Exception", 145 [ESR_EC_BKPT_INSN_A32] = "A32: BKPT Instruction Execution", 146 [ESR_EC_VECTOR_CATCH] = "A32: Vector Catch Exception" 147 }; 148 149 const char * 150 eclass_trapname(uint32_t eclass) 151 { 152 static char trapnamebuf[sizeof("Unknown trap 0x????????")]; 153 154 if (eclass >= __arraycount(trap_names) || trap_names[eclass] == NULL) { 155 snprintf(trapnamebuf, sizeof(trapnamebuf), 156 "Unknown trap %#02x", eclass); 157 return trapnamebuf; 158 } 159 return trap_names[eclass]; 160 } 161 162 void 163 userret(struct lwp *l) 164 { 165 mi_userret(l); 166 } 167 168 void 169 trap_doast(struct trapframe *tf) 170 { 171 struct lwp * const l = curlwp; 172 173 /* 174 * allow to have a chance of context switch just prior to user 175 * exception return. 176 */ 177 #ifdef __HAVE_PREEMPTION 178 kpreempt_disable(); 179 #endif 180 struct cpu_info * const ci = curcpu(); 181 182 ci->ci_data.cpu_ntrap++; 183 184 KDASSERT(ci->ci_cpl == IPL_NONE); 185 #ifdef __HAVE_PREEMPTION 186 kpreempt_enable(); 187 #endif 188 189 if (l->l_pflag & LP_OWEUPC) { 190 l->l_pflag &= ~LP_OWEUPC; 191 ADDUPROF(l); 192 } 193 194 userret(l); 195 } 196 197 void 198 trap_el1h_sync(struct trapframe *tf) 199 { 200 const uint32_t esr = tf->tf_esr; 201 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 202 203 /* re-enable traps and interrupts */ 204 if (!(tf->tf_spsr & SPSR_I)) 205 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 206 else 207 daif_enable(DAIF_D|DAIF_A); 208 209 #ifdef KDTRACE_HOOKS 210 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(tf, eclass)) 211 return; 212 #endif 213 214 switch (eclass) { 215 case ESR_EC_INSN_ABT_EL1: 216 case ESR_EC_DATA_ABT_EL1: 217 data_abort_handler(tf, eclass); 218 break; 219 220 case ESR_EC_BKPT_INSN_A64: 221 #ifdef KDTRACE_HOOKS 222 if (__SHIFTOUT(esr, ESR_ISS) == 0x40d && 223 dtrace_invop_jump_addr != 0) { 224 (*dtrace_invop_jump_addr)(tf); 225 break; 226 } 227 /* FALLTHROUGH */ 228 #endif 229 case ESR_EC_BRKPNT_EL1: 230 case ESR_EC_SW_STEP_EL1: 231 case ESR_EC_WTCHPNT_EL1: 232 #ifdef DDB 233 if (eclass == ESR_EC_BRKPNT_EL1) 234 kdb_trap(DB_TRAP_BREAKPOINT, tf); 235 else if (eclass == ESR_EC_BKPT_INSN_A64) 236 kdb_trap(DB_TRAP_BKPT_INSN, tf); 237 else if (eclass == ESR_EC_WTCHPNT_EL1) 238 kdb_trap(DB_TRAP_WATCHPOINT, tf); 239 else if (eclass == ESR_EC_SW_STEP_EL1) 240 kdb_trap(DB_TRAP_SW_STEP, tf); 241 else 242 kdb_trap(DB_TRAP_UNKNOWN, tf); 243 #else 244 panic("No debugger in kernel"); 245 #endif 246 break; 247 248 case ESR_EC_FP_ACCESS: 249 if ((curlwp->l_flag & (LW_SYSTEM|LW_SYSTEM_FPU)) == 250 (LW_SYSTEM|LW_SYSTEM_FPU)) { 251 fpu_load(curlwp); 252 break; 253 } 254 /*FALLTHROUGH*/ 255 case ESR_EC_FP_TRAP_A64: 256 case ESR_EC_PC_ALIGNMENT: 257 case ESR_EC_SP_ALIGNMENT: 258 case ESR_EC_ILL_STATE: 259 case ESR_EC_BTE_A64: 260 default: 261 panic("Trap: fatal %s: pc=%016" PRIx64 " sp=%016" PRIx64 262 " esr=%08x", eclass_trapname(eclass), tf->tf_pc, tf->tf_sp, 263 esr); 264 break; 265 } 266 } 267 268 /* 269 * There are some systems with different cache line sizes for each cpu. 270 * Userland programs can be preempted between CPUs at any time, so in such 271 * a system, the minimum cache line size must be visible to userland. 272 */ 273 #define CTR_EL0_USR_MASK \ 274 (CTR_EL0_DIC | CTR_EL0_IDC | CTR_EL0_DMIN_LINE | CTR_EL0_IMIN_LINE) 275 uint64_t ctr_el0_usr __read_mostly; 276 277 static xcfunc_t 278 configure_cpu_traps0(void *arg1, void *arg2) 279 { 280 struct cpu_info * const ci = curcpu(); 281 uint64_t sctlr; 282 uint64_t ctr_el0_raw = reg_ctr_el0_read(); 283 284 #ifdef DEBUG_FORCE_TRAP_CTR_EL0 285 goto need_ctr_trap; 286 #endif 287 288 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DMIN_LINE) > 289 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) || 290 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IMIN_LINE) > 291 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) 292 goto need_ctr_trap; 293 294 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DIC) == 1 && 295 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DIC) == 0) || 296 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 1 && 297 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 0)) 298 goto need_ctr_trap; 299 300 #if 0 /* XXX: To do or not to do */ 301 /* 302 * IDC==0, but (LoC==0 || LoUIS==LoUU==0)? 303 * Would it be better to show IDC=1 to userland? 304 */ 305 if (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 0 && 306 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 1) 307 goto need_ctr_trap; 308 #endif 309 310 return 0; 311 312 need_ctr_trap: 313 evcnt_attach_dynamic(&ci->ci_uct_trap, EVCNT_TYPE_MISC, NULL, 314 ci->ci_cpuname, "ctr_el0 trap"); 315 316 /* trap CTR_EL0 access from EL0 on this cpu */ 317 sctlr = reg_sctlr_el1_read(); 318 sctlr &= ~SCTLR_UCT; 319 reg_sctlr_el1_write(sctlr); 320 321 return 0; 322 } 323 324 void 325 configure_cpu_traps(void) 326 { 327 CPU_INFO_ITERATOR cii; 328 struct cpu_info *ci; 329 uint64_t where; 330 331 /* remember minimum cache line size out of all CPUs */ 332 for (CPU_INFO_FOREACH(cii, ci)) { 333 uint64_t ctr_el0_cpu = ci->ci_id.ac_ctr; 334 uint64_t clidr = ci->ci_id.ac_clidr; 335 336 if (__SHIFTOUT(clidr, CLIDR_LOC) == 0 || 337 (__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 && 338 __SHIFTOUT(clidr, CLIDR_LOUU) == 0)) { 339 /* this means the same as IDC=1 */ 340 ctr_el0_cpu |= CTR_EL0_IDC; 341 } 342 343 /* 344 * if DIC==1, there is no need to icache sync. however, 345 * to calculate the minimum cacheline, in this case 346 * ICacheLine is treated as the maximum. 347 */ 348 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1) 349 ctr_el0_cpu |= CTR_EL0_IMIN_LINE; 350 351 /* Neoverse N1 erratum 1542419 */ 352 if (CPU_ID_NEOVERSEN1_P(ci->ci_id.ac_midr) && 353 __SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1) 354 ctr_el0_cpu &= ~CTR_EL0_DIC; 355 356 if (cii == 0) { 357 ctr_el0_usr = ctr_el0_cpu; 358 continue; 359 } 360 361 /* keep minimum cache line size, and worst DIC/IDC */ 362 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_DIC) | ~CTR_EL0_DIC; 363 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_IDC) | ~CTR_EL0_IDC; 364 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DMIN_LINE) < 365 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) { 366 ctr_el0_usr &= ~CTR_EL0_DMIN_LINE; 367 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_DMIN_LINE; 368 } 369 if ((ctr_el0_cpu & CTR_EL0_DIC) == 0 && 370 (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_IMIN_LINE) < 371 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) { 372 ctr_el0_usr &= ~CTR_EL0_IMIN_LINE; 373 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_IMIN_LINE; 374 } 375 } 376 377 where = xc_broadcast(0, 378 (xcfunc_t)configure_cpu_traps0, NULL, NULL); 379 xc_wait(where); 380 } 381 382 static enum emul_arm_result 383 emul_aarch64_insn(struct trapframe *tf) 384 { 385 uint32_t insn; 386 387 if (ufetch_32((uint32_t *)tf->tf_pc, &insn)) { 388 tf->tf_far = reg_far_el1_read(); 389 return EMUL_ARM_FAULT; 390 } 391 392 LE32TOH(insn); 393 if ((insn & 0xffffffe0) == 0xd53b0020) { 394 /* mrs x?,ctr_el0 */ 395 unsigned int Xt = insn & 31; 396 if (Xt != 31) { /* !xzr */ 397 uint64_t ctr_el0 = reg_ctr_el0_read(); 398 ctr_el0 &= ~CTR_EL0_USR_MASK; 399 ctr_el0 |= (ctr_el0_usr & CTR_EL0_USR_MASK); 400 tf->tf_reg[Xt] = ctr_el0; 401 } 402 curcpu()->ci_uct_trap.ev_count++; 403 404 } else { 405 return EMUL_ARM_UNKNOWN; 406 } 407 408 tf->tf_pc += 4; 409 return EMUL_ARM_SUCCESS; 410 } 411 412 void 413 trap_el0_sync(struct trapframe *tf) 414 { 415 struct lwp * const l = curlwp; 416 const uint32_t esr = tf->tf_esr; 417 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 418 419 /* disable trace */ 420 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 421 /* enable traps and interrupts */ 422 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 423 424 switch (eclass) { 425 case ESR_EC_INSN_ABT_EL0: 426 case ESR_EC_DATA_ABT_EL0: 427 data_abort_handler(tf, eclass); 428 userret(l); 429 break; 430 431 case ESR_EC_SVC_A64: 432 (*l->l_proc->p_md.md_syscall)(tf); 433 break; 434 case ESR_EC_FP_ACCESS: 435 fpu_load(l); 436 userret(l); 437 break; 438 case ESR_EC_FP_TRAP_A64: 439 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 440 userret(l); 441 break; 442 443 case ESR_EC_PC_ALIGNMENT: 444 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 445 userret(l); 446 break; 447 case ESR_EC_SP_ALIGNMENT: 448 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr); 449 userret(l); 450 break; 451 452 case ESR_EC_BKPT_INSN_A64: 453 case ESR_EC_BRKPNT_EL0: 454 case ESR_EC_WTCHPNT_EL0: 455 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 456 userret(l); 457 break; 458 case ESR_EC_SW_STEP_EL0: 459 /* disable trace, and send trace trap */ 460 tf->tf_spsr &= ~SPSR_SS; 461 do_trapsignal(l, SIGTRAP, TRAP_TRACE, (void *)tf->tf_pc, esr); 462 userret(l); 463 break; 464 465 case ESR_EC_SYS_REG: 466 switch (emul_aarch64_insn(tf)) { 467 case EMUL_ARM_SUCCESS: 468 break; 469 case EMUL_ARM_UNKNOWN: 470 goto unknown; 471 case EMUL_ARM_FAULT: 472 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 473 (void *)tf->tf_far, esr); 474 break; 475 } 476 userret(l); 477 break; 478 479 default: 480 case ESR_EC_UNKNOWN: 481 unknown: 482 #ifdef DDB 483 if (sigill_debug) { 484 /* show illegal instruction */ 485 printf("TRAP: pid %d (%s), uid %d: %s:" 486 " esr=0x%lx: pc=0x%lx: %s\n", 487 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 488 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 489 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 490 strdisasm(tf->tf_pc, tf->tf_spsr)); 491 } 492 #endif 493 /* illegal or not implemented instruction */ 494 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 495 userret(l); 496 break; 497 } 498 } 499 500 void 501 interrupt(struct trapframe *tf) 502 { 503 struct cpu_info * const ci = curcpu(); 504 505 #ifdef STACKCHECKS 506 struct lwp *l = curlwp; 507 void *sp = (void *)reg_sp_read(); 508 if (l->l_addr >= sp) { 509 panic("lwp/interrupt stack overflow detected." 510 " lwp=%p, sp=%p, l_addr=%p", l, sp, l->l_addr); 511 } 512 #endif 513 514 /* disable trace */ 515 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 516 517 /* enable traps */ 518 daif_enable(DAIF_D|DAIF_A); 519 520 ci->ci_intr_depth++; 521 ARM_IRQ_HANDLER(tf); 522 ci->ci_intr_depth--; 523 524 cpu_dosoftints(); 525 } 526 527 #ifdef COMPAT_NETBSD32 528 529 /* 530 * 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3. 531 */ 532 #define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && ((hi) & 0x1800)) 533 534 int 535 fetch_arm_insn(uint64_t pc, uint64_t spsr, uint32_t *insn) 536 { 537 538 /* 539 * Instructions are stored in little endian for BE8, 540 * only a valid binary format for ILP32EB. Therefore, 541 * we need byte-swapping before decoding on aarch64eb. 542 */ 543 544 /* THUMB? */ 545 if (spsr & SPSR_A32_T) { 546 uint16_t *p = (uint16_t *)(pc & ~1UL); /* XXX */ 547 uint16_t hi, lo; 548 549 if (ufetch_16(p, &hi)) 550 return -1; 551 LE16TOH(hi); 552 553 if (!THUMB_32BIT(hi)) { 554 /* 16-bit Thumb instruction */ 555 *insn = hi; 556 return 2; 557 } 558 559 /* 32-bit Thumb instruction */ 560 if (ufetch_16(p + 1, &lo)) 561 return -1; 562 LE16TOH(lo); 563 564 *insn = ((uint32_t)hi << 16) | lo; 565 return 4; 566 } 567 568 if (ufetch_32((uint32_t *)pc, insn)) 569 return -1; 570 LE32TOH(*insn); 571 572 return 4; 573 } 574 575 static bool 576 arm_cond_match(uint32_t insn, uint64_t spsr) 577 { 578 bool invert = (insn >> 28) & 1; 579 bool match; 580 581 switch (insn >> 29) { 582 case 0: /* EQ or NE */ 583 match = spsr & SPSR_Z; 584 break; 585 case 1: /* CS/HI or CC/LO */ 586 match = spsr & SPSR_C; 587 break; 588 case 2: /* MI or PL */ 589 match = spsr & SPSR_N; 590 break; 591 case 3: /* VS or VC */ 592 match = spsr & SPSR_V; 593 break; 594 case 4: /* HI or LS */ 595 match = ((spsr & (SPSR_C | SPSR_Z)) == SPSR_C); 596 break; 597 case 5: /* GE or LT */ 598 match = (!(spsr & SPSR_N) == !(spsr & SPSR_V)); 599 break; 600 case 6: /* GT or LE */ 601 match = !(spsr & SPSR_Z) && 602 (!(spsr & SPSR_N) == !(spsr & SPSR_V)); 603 break; 604 case 7: /* AL */ 605 match = true; 606 break; 607 } 608 return (!match != !invert); 609 } 610 611 uint8_t atomic_swap_8(volatile uint8_t *, uint8_t); 612 613 static int 614 emul_arm_swp(uint32_t insn, struct trapframe *tf) 615 { 616 struct faultbuf fb; 617 vaddr_t vaddr; 618 uint32_t val; 619 int Rn, Rd, Rm, error; 620 621 Rn = __SHIFTOUT(insn, 0x000f0000); 622 Rd = __SHIFTOUT(insn, 0x0000f000); 623 Rm = __SHIFTOUT(insn, 0x0000000f); 624 625 vaddr = tf->tf_reg[Rn] & 0xffffffff; 626 val = tf->tf_reg[Rm]; 627 628 /* fault if insn is swp, and unaligned access */ 629 if ((insn & 0x00400000) == 0 && (vaddr & 3) != 0) { 630 tf->tf_far = vaddr; 631 return EFAULT; 632 } 633 634 /* vaddr will always point to userspace, since it has only 32bit */ 635 if ((error = cpu_set_onfault(&fb)) == 0) { 636 if (aarch64_pan_enabled) 637 reg_pan_write(0); /* disable PAN */ 638 if (insn & 0x00400000) { 639 /* swpb */ 640 val = atomic_swap_8((uint8_t *)vaddr, val); 641 } else { 642 /* swp */ 643 val = atomic_swap_32((uint32_t *)vaddr, val); 644 } 645 cpu_unset_onfault(); 646 tf->tf_reg[Rd] = val; 647 } else { 648 tf->tf_far = reg_far_el1_read(); 649 } 650 if (aarch64_pan_enabled) 651 reg_pan_write(1); /* enable PAN */ 652 return error; 653 } 654 655 static enum emul_arm_result 656 emul_thumb_insn(struct trapframe *tf, uint32_t insn, int insn_size) 657 { 658 /* T32-16bit or 32bit instructions */ 659 switch (insn_size) { 660 case 2: 661 /* Breakpoint used by GDB */ 662 if (insn == 0xdefe) { 663 do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT, 664 (void *)tf->tf_pc, 0); 665 return EMUL_ARM_SUCCESS; 666 } 667 /* XXX: some T32 IT instruction deprecated should be emulated */ 668 break; 669 case 4: 670 break; 671 default: 672 return EMUL_ARM_FAULT; 673 } 674 return EMUL_ARM_UNKNOWN; 675 } 676 677 static enum emul_arm_result 678 emul_arm_insn(struct trapframe *tf) 679 { 680 uint32_t insn; 681 int insn_size; 682 683 insn_size = fetch_arm_insn(tf->tf_pc, tf->tf_spsr, &insn); 684 tf->tf_far = reg_far_el1_read(); 685 686 if (tf->tf_spsr & SPSR_A32_T) 687 return emul_thumb_insn(tf, insn, insn_size); 688 if (insn_size != 4) 689 return EMUL_ARM_FAULT; 690 691 /* Breakpoint used by GDB */ 692 if (insn == 0xe6000011 || insn == 0xe7ffdefe) { 693 do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT, 694 (void *)tf->tf_pc, 0); 695 return EMUL_ARM_SUCCESS; 696 } 697 698 /* Unconditional instruction extension space? */ 699 if ((insn & 0xf0000000) == 0xf0000000) 700 goto unknown_insn; 701 702 /* swp,swpb */ 703 if ((insn & 0x0fb00ff0) == 0x01000090) { 704 if (arm_cond_match(insn, tf->tf_spsr)) { 705 if (emul_arm_swp(insn, tf) != 0) 706 return EMUL_ARM_FAULT; 707 } 708 goto emulated; 709 } 710 711 /* 712 * Emulate ARMv6 instructions with cache operations 713 * register (c7), that can be used in user mode. 714 */ 715 switch (insn & 0x0fff0fff) { 716 case 0x0e070f95: 717 if (arm_cond_match(insn, tf->tf_spsr)) { 718 /* 719 * mcr p15, 0, <Rd>, c7, c5, 4 720 * (flush prefetch buffer) 721 */ 722 isb(); 723 } 724 goto emulated; 725 case 0x0e070f9a: 726 if (arm_cond_match(insn, tf->tf_spsr)) { 727 /* 728 * mcr p15, 0, <Rd>, c7, c10, 4 729 * (data synchronization barrier) 730 */ 731 dsb(sy); 732 } 733 goto emulated; 734 case 0x0e070fba: 735 if (arm_cond_match(insn, tf->tf_spsr)) { 736 /* 737 * mcr p15, 0, <Rd>, c7, c10, 5 738 * (data memory barrier) 739 */ 740 dmb(sy); 741 } 742 goto emulated; 743 default: 744 break; 745 } 746 747 unknown_insn: 748 /* unknown, or unsupported instruction */ 749 return EMUL_ARM_UNKNOWN; 750 751 emulated: 752 tf->tf_pc += insn_size; 753 return EMUL_ARM_SUCCESS; 754 } 755 #endif /* COMPAT_NETBSD32 */ 756 757 void 758 trap_el0_32sync(struct trapframe *tf) 759 { 760 struct lwp * const l = curlwp; 761 const uint32_t esr = tf->tf_esr; 762 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 763 764 /* disable trace */ 765 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 766 /* enable traps and interrupts */ 767 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 768 769 switch (eclass) { 770 #ifdef COMPAT_NETBSD32 771 case ESR_EC_INSN_ABT_EL0: 772 case ESR_EC_DATA_ABT_EL0: 773 data_abort_handler(tf, eclass); 774 userret(l); 775 break; 776 777 case ESR_EC_SVC_A32: 778 (*l->l_proc->p_md.md_syscall)(tf); 779 break; 780 781 case ESR_EC_FP_ACCESS: 782 fpu_load(l); 783 userret(l); 784 break; 785 786 case ESR_EC_FP_TRAP_A32: 787 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 788 userret(l); 789 break; 790 791 case ESR_EC_PC_ALIGNMENT: 792 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 793 userret(l); 794 break; 795 796 case ESR_EC_SP_ALIGNMENT: 797 do_trapsignal(l, SIGBUS, BUS_ADRALN, 798 (void *)tf->tf_reg[13], esr); /* sp is r13 on AArch32 */ 799 userret(l); 800 break; 801 802 case ESR_EC_BKPT_INSN_A32: 803 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 804 userret(l); 805 break; 806 807 case ESR_EC_UNKNOWN: 808 switch (emul_arm_insn(tf)) { 809 case EMUL_ARM_SUCCESS: 810 break; 811 case EMUL_ARM_UNKNOWN: 812 goto unknown; 813 case EMUL_ARM_FAULT: 814 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 815 (void *)tf->tf_far, esr); 816 break; 817 } 818 userret(l); 819 break; 820 821 case ESR_EC_CP15_RT: 822 case ESR_EC_CP15_RRT: 823 case ESR_EC_CP14_RT: 824 case ESR_EC_CP14_DT: 825 case ESR_EC_CP14_RRT: 826 unknown: 827 #endif /* COMPAT_NETBSD32 */ 828 default: 829 #ifdef DDB 830 if (sigill_debug) { 831 /* show illegal instruction */ 832 printf("TRAP: pid %d (%s), uid %d: %s:" 833 " esr=0x%lx: pc=0x%lx: %s\n", 834 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 835 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 836 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 837 strdisasm(tf->tf_pc, tf->tf_spsr)); 838 } 839 #endif 840 /* illegal or not implemented instruction */ 841 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 842 userret(l); 843 break; 844 } 845 } 846 847 #define bad_trap_panic(trapfunc) \ 848 void \ 849 trapfunc(struct trapframe *tf) \ 850 { \ 851 panic("%s", __func__); \ 852 } 853 bad_trap_panic(trap_el1t_sync) 854 bad_trap_panic(trap_el1t_irq) 855 bad_trap_panic(trap_el1t_fiq) 856 bad_trap_panic(trap_el1t_error) 857 bad_trap_panic(trap_el1h_fiq) 858 bad_trap_panic(trap_el1h_error) 859 bad_trap_panic(trap_el0_fiq) 860 bad_trap_panic(trap_el0_error) 861 bad_trap_panic(trap_el0_32fiq) 862 bad_trap_panic(trap_el0_32error) 863 864 void 865 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int val) 866 { 867 tf->tf_reg[19] = fb->fb_reg[FB_X19]; 868 tf->tf_reg[20] = fb->fb_reg[FB_X20]; 869 tf->tf_reg[21] = fb->fb_reg[FB_X21]; 870 tf->tf_reg[22] = fb->fb_reg[FB_X22]; 871 tf->tf_reg[23] = fb->fb_reg[FB_X23]; 872 tf->tf_reg[24] = fb->fb_reg[FB_X24]; 873 tf->tf_reg[25] = fb->fb_reg[FB_X25]; 874 tf->tf_reg[26] = fb->fb_reg[FB_X26]; 875 tf->tf_reg[27] = fb->fb_reg[FB_X27]; 876 tf->tf_reg[28] = fb->fb_reg[FB_X28]; 877 tf->tf_reg[29] = fb->fb_reg[FB_X29]; 878 tf->tf_sp = fb->fb_reg[FB_SP]; 879 tf->tf_pc = fb->fb_reg[FB_LR]; 880 tf->tf_reg[0] = val; 881 } 882 883 #ifdef TRAP_SIGDEBUG 884 static void 885 frame_dump(const struct trapframe *tf) 886 { 887 const struct reg *r = &tf->tf_regs; 888 889 printf("trapframe %p\n", tf); 890 for (size_t i = 0; i < __arraycount(r->r_reg); i++) { 891 printf(" r%.2zu %#018" PRIx64 "%c", i, r->r_reg[i], 892 " \n"[i && (i & 1) == 0]); 893 } 894 895 printf("\n"); 896 printf(" sp %#018" PRIx64 " pc %#018" PRIx64 "\n", 897 r->r_sp, r->r_pc); 898 printf(" spsr %#018" PRIx64 " tpidr %#018" PRIx64 "\n", 899 r->r_spsr, r->r_tpidr); 900 printf(" esr %#018" PRIx64 " far %#018" PRIx64 "\n", 901 tf->tf_esr, tf->tf_far); 902 903 printf("\n"); 904 hexdump(printf, "Stack dump", tf, 256); 905 } 906 907 static void 908 sigdebug(const struct trapframe *tf, const ksiginfo_t *ksi) 909 { 910 struct lwp *l = curlwp; 911 struct proc *p = l->l_proc; 912 const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC); 913 914 printf("pid %d.%d (%s): signal %d (trap %#x) " 915 "@pc %#" PRIx64 ", addr %p, error=%s\n", 916 p->p_pid, l->l_lid, p->p_comm, ksi->ksi_signo, ksi->ksi_trap, 917 tf->tf_regs.r_pc, ksi->ksi_addr, eclass_trapname(eclass)); 918 frame_dump(tf); 919 } 920 #endif 921 922 void 923 do_trapsignal1( 924 #ifdef TRAP_SIGDEBUG 925 const char *func, 926 size_t line, 927 struct trapframe *tf, 928 #endif 929 struct lwp *l, int signo, int code, void *addr, int trap) 930 { 931 ksiginfo_t ksi; 932 933 KSI_INIT_TRAP(&ksi); 934 ksi.ksi_signo = signo; 935 ksi.ksi_code = code; 936 ksi.ksi_addr = addr; 937 ksi.ksi_trap = trap; 938 #ifdef TRAP_SIGDEBUG 939 printf("%s, %zu: ", func, line); 940 sigdebug(tf, &ksi); 941 #endif 942 (*l->l_proc->p_emul->e_trapsignal)(l, &ksi); 943 } 944 945 bool 946 cpu_intr_p(void) 947 { 948 uint64_t ncsw; 949 int idepth; 950 lwp_t *l; 951 952 #ifdef __HAVE_PIC_FAST_SOFTINTS 953 /* XXX Copied from cpu.h. Looks incomplete - needs fixing. */ 954 if (ci->ci_cpl < IPL_VM) 955 return false; 956 #endif 957 958 l = curlwp; 959 if (__predict_false(l->l_cpu == NULL)) { 960 KASSERT(l == &lwp0); 961 return false; 962 } 963 do { 964 ncsw = l->l_ncsw; 965 __insn_barrier(); 966 idepth = l->l_cpu->ci_intr_depth; 967 __insn_barrier(); 968 } while (__predict_false(ncsw != l->l_ncsw)); 969 970 return idepth > 0; 971 } 972
Indexes created Wed Oct 15 16:09:53 GMT 2025