trap.c revision 1.47
1 /* $NetBSD: trap.c,v 1.47 2021/08/30 23:20:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.47 2021/08/30 23:20:00 jmcneill Exp $"); 35 36 #include "opt_arm_intr_impl.h" 37 #include "opt_compat_netbsd32.h" 38 #include "opt_dtrace.h" 39 40 #include <sys/param.h> 41 #include <sys/kauth.h> 42 #include <sys/types.h> 43 #include <sys/atomic.h> 44 #include <sys/cpu.h> 45 #include <sys/evcnt.h> 46 #ifdef KDB 47 #include <sys/kdb.h> 48 #endif 49 #include <sys/proc.h> 50 #include <sys/systm.h> 51 #include <sys/signal.h> 52 #include <sys/signalvar.h> 53 #include <sys/siginfo.h> 54 #include <sys/xcall.h> 55 56 #ifdef ARM_INTR_IMPL 57 #include ARM_INTR_IMPL 58 #else 59 #error ARM_INTR_IMPL not defined 60 #endif 61 62 #ifndef ARM_IRQ_HANDLER 63 #error ARM_IRQ_HANDLER not defined 64 #endif 65 66 #include <arm/cpufunc.h> 67 68 #include <aarch64/userret.h> 69 #include <aarch64/frame.h> 70 #include <aarch64/machdep.h> 71 #include <aarch64/armreg.h> 72 #include <aarch64/locore.h> 73 74 #include <arm/cpufunc.h> 75 76 #ifdef KDB 77 #include <machine/db_machdep.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/db_output.h> 81 #include <machine/db_machdep.h> 82 #endif 83 #ifdef KDTRACE_HOOKS 84 #include <sys/dtrace_bsd.h> 85 #endif 86 87 #ifdef DDB 88 int sigill_debug = 0; 89 #endif 90 91 #ifdef KDTRACE_HOOKS 92 dtrace_doubletrap_func_t dtrace_doubletrap_func = NULL; 93 dtrace_trap_func_t dtrace_trap_func = NULL; 94 int (*dtrace_invop_jump_addr)(struct trapframe *); 95 #endif 96 97 enum emul_arm_result { 98 EMUL_ARM_SUCCESS = 0, 99 EMUL_ARM_UNKNOWN, 100 EMUL_ARM_FAULT, 101 }; 102 103 const char * const trap_names[] = { 104 [ESR_EC_UNKNOWN] = "Unknown Reason (Illegal Instruction)", 105 [ESR_EC_SERROR] = "SError Interrupt", 106 [ESR_EC_WFX] = "WFI or WFE instruction execution", 107 [ESR_EC_ILL_STATE] = "Illegal Execution State", 108 109 [ESR_EC_BTE_A64] = "Branch Target Exception", 110 111 [ESR_EC_SYS_REG] = "MSR/MRS/SYS instruction", 112 [ESR_EC_SVC_A64] = "SVC Instruction Execution", 113 [ESR_EC_HVC_A64] = "HVC Instruction Execution", 114 [ESR_EC_SMC_A64] = "SMC Instruction Execution", 115 116 [ESR_EC_INSN_ABT_EL0] = "Instruction Abort (EL0)", 117 [ESR_EC_INSN_ABT_EL1] = "Instruction Abort (EL1)", 118 [ESR_EC_DATA_ABT_EL0] = "Data Abort (EL0)", 119 [ESR_EC_DATA_ABT_EL1] = "Data Abort (EL1)", 120 121 [ESR_EC_PC_ALIGNMENT] = "Misaligned PC", 122 [ESR_EC_SP_ALIGNMENT] = "Misaligned SP", 123 124 [ESR_EC_FP_ACCESS] = "Access to SIMD/FP Registers", 125 [ESR_EC_FP_TRAP_A64] = "FP Exception", 126 127 [ESR_EC_BRKPNT_EL0] = "Breakpoint Exception (EL0)", 128 [ESR_EC_BRKPNT_EL1] = "Breakpoint Exception (EL1)", 129 [ESR_EC_SW_STEP_EL0] = "Software Step (EL0)", 130 [ESR_EC_SW_STEP_EL1] = "Software Step (EL1)", 131 [ESR_EC_WTCHPNT_EL0] = "Watchpoint (EL0)", 132 [ESR_EC_WTCHPNT_EL1] = "Watchpoint (EL1)", 133 [ESR_EC_BKPT_INSN_A64] = "BKPT Instruction Execution", 134 135 [ESR_EC_CP15_RT] = "A32: MCR/MRC access to CP15", 136 [ESR_EC_CP15_RRT] = "A32: MCRR/MRRC access to CP15", 137 [ESR_EC_CP14_RT] = "A32: MCR/MRC access to CP14", 138 [ESR_EC_CP14_DT] = "A32: LDC/STC access to CP14", 139 [ESR_EC_CP14_RRT] = "A32: MRRC access to CP14", 140 [ESR_EC_SVC_A32] = "A32: SVC Instruction Execution", 141 [ESR_EC_HVC_A32] = "A32: HVC Instruction Execution", 142 [ESR_EC_SMC_A32] = "A32: SMC Instruction Execution", 143 [ESR_EC_FPID] = "A32: MCR/MRC access to CP10", 144 [ESR_EC_FP_TRAP_A32] = "A32: FP Exception", 145 [ESR_EC_BKPT_INSN_A32] = "A32: BKPT Instruction Execution", 146 [ESR_EC_VECTOR_CATCH] = "A32: Vector Catch Exception" 147 }; 148 149 const char * 150 eclass_trapname(uint32_t eclass) 151 { 152 static char trapnamebuf[sizeof("Unknown trap 0x????????")]; 153 154 if (eclass >= __arraycount(trap_names) || trap_names[eclass] == NULL) { 155 snprintf(trapnamebuf, sizeof(trapnamebuf), 156 "Unknown trap %#02x", eclass); 157 return trapnamebuf; 158 } 159 return trap_names[eclass]; 160 } 161 162 void 163 userret(struct lwp *l) 164 { 165 mi_userret(l); 166 } 167 168 void 169 trap_doast(struct trapframe *tf) 170 { 171 struct lwp * const l = curlwp; 172 173 /* 174 * allow to have a chance of context switch just prior to user 175 * exception return. 176 */ 177 #ifdef __HAVE_PREEMPTION 178 kpreempt_disable(); 179 #endif 180 struct cpu_info * const ci = curcpu(); 181 182 ci->ci_data.cpu_ntrap++; 183 184 KDASSERT(ci->ci_cpl == IPL_NONE); 185 #ifdef __HAVE_PREEMPTION 186 kpreempt_enable(); 187 #endif 188 189 if (l->l_pflag & LP_OWEUPC) { 190 l->l_pflag &= ~LP_OWEUPC; 191 ADDUPROF(l); 192 } 193 194 userret(l); 195 } 196 197 void 198 trap_el1h_sync(struct trapframe *tf) 199 { 200 const uint32_t esr = tf->tf_esr; 201 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 202 203 /* re-enable traps and interrupts */ 204 if (!(tf->tf_spsr & SPSR_I)) 205 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 206 else 207 daif_enable(DAIF_D|DAIF_A); 208 209 #ifdef KDTRACE_HOOKS 210 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(tf, eclass)) 211 return; 212 #endif 213 214 switch (eclass) { 215 case ESR_EC_INSN_ABT_EL1: 216 case ESR_EC_DATA_ABT_EL1: 217 data_abort_handler(tf, eclass); 218 break; 219 220 case ESR_EC_BKPT_INSN_A64: 221 #ifdef KDTRACE_HOOKS 222 if (__SHIFTOUT(esr, ESR_ISS) == 0x40d && 223 dtrace_invop_jump_addr != 0) { 224 (*dtrace_invop_jump_addr)(tf); 225 break; 226 } 227 /* FALLTHROUGH */ 228 #endif 229 case ESR_EC_BRKPNT_EL1: 230 case ESR_EC_SW_STEP_EL1: 231 case ESR_EC_WTCHPNT_EL1: 232 #ifdef DDB 233 if (eclass == ESR_EC_BRKPNT_EL1) 234 kdb_trap(DB_TRAP_BREAKPOINT, tf); 235 else if (eclass == ESR_EC_BKPT_INSN_A64) 236 kdb_trap(DB_TRAP_BKPT_INSN, tf); 237 else if (eclass == ESR_EC_WTCHPNT_EL1) 238 kdb_trap(DB_TRAP_WATCHPOINT, tf); 239 else if (eclass == ESR_EC_SW_STEP_EL1) 240 kdb_trap(DB_TRAP_SW_STEP, tf); 241 else 242 kdb_trap(DB_TRAP_UNKNOWN, tf); 243 #else 244 panic("No debugger in kernel"); 245 #endif 246 break; 247 248 case ESR_EC_FP_ACCESS: 249 if ((curlwp->l_flag & (LW_SYSTEM|LW_SYSTEM_FPU)) == 250 (LW_SYSTEM|LW_SYSTEM_FPU)) { 251 fpu_load(curlwp); 252 break; 253 } 254 /*FALLTHROUGH*/ 255 case ESR_EC_FP_TRAP_A64: 256 case ESR_EC_PC_ALIGNMENT: 257 case ESR_EC_SP_ALIGNMENT: 258 case ESR_EC_ILL_STATE: 259 case ESR_EC_BTE_A64: 260 default: 261 panic("Trap: fatal %s: pc=%016" PRIx64 " sp=%016" PRIx64 262 " esr=%08x", eclass_trapname(eclass), tf->tf_pc, tf->tf_sp, 263 esr); 264 break; 265 } 266 } 267 268 /* 269 * There are some systems with different cache line sizes for each cpu. 270 * Userland programs can be preempted between CPUs at any time, so in such 271 * a system, the minimum cache line size must be visible to userland. 272 */ 273 #define CTR_EL0_USR_MASK \ 274 (CTR_EL0_DIC | CTR_EL0_IDC | CTR_EL0_DMIN_LINE | CTR_EL0_IMIN_LINE) 275 uint64_t ctr_el0_usr __read_mostly; 276 277 static xcfunc_t 278 configure_cpu_traps0(void *arg1, void *arg2) 279 { 280 struct cpu_info * const ci = curcpu(); 281 uint64_t sctlr; 282 uint64_t ctr_el0_raw = reg_ctr_el0_read(); 283 284 #ifdef DEBUG_FORCE_TRAP_CTR_EL0 285 goto need_ctr_trap; 286 #endif 287 288 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DMIN_LINE) > 289 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) || 290 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IMIN_LINE) > 291 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) 292 goto need_ctr_trap; 293 294 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DIC) == 1 && 295 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DIC) == 0) || 296 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 1 && 297 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 0)) 298 goto need_ctr_trap; 299 300 #if 0 /* XXX: To do or not to do */ 301 /* 302 * IDC==0, but (LoC==0 || LoUIS==LoUU==0)? 303 * Would it be better to show IDC=1 to userland? 304 */ 305 if (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 0 && 306 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 1) 307 goto need_ctr_trap; 308 #endif 309 310 return 0; 311 312 need_ctr_trap: 313 evcnt_attach_dynamic(&ci->ci_uct_trap, EVCNT_TYPE_MISC, NULL, 314 ci->ci_cpuname, "ctr_el0 trap"); 315 316 /* trap CTR_EL0 access from EL0 on this cpu */ 317 sctlr = reg_sctlr_el1_read(); 318 sctlr &= ~SCTLR_UCT; 319 reg_sctlr_el1_write(sctlr); 320 321 return 0; 322 } 323 324 void 325 configure_cpu_traps(void) 326 { 327 CPU_INFO_ITERATOR cii; 328 struct cpu_info *ci; 329 uint64_t where; 330 331 /* remember minimum cache line size out of all CPUs */ 332 for (CPU_INFO_FOREACH(cii, ci)) { 333 uint64_t ctr_el0_cpu = ci->ci_id.ac_ctr; 334 uint64_t clidr = ci->ci_id.ac_clidr; 335 336 if (__SHIFTOUT(clidr, CLIDR_LOC) == 0 || 337 (__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 && 338 __SHIFTOUT(clidr, CLIDR_LOUU) == 0)) { 339 /* this means the same as IDC=1 */ 340 ctr_el0_cpu |= CTR_EL0_IDC; 341 } 342 343 /* 344 * if DIC==1, there is no need to icache sync. however, 345 * to calculate the minimum cacheline, in this case 346 * ICacheLine is treated as the maximum. 347 */ 348 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1) 349 ctr_el0_cpu |= CTR_EL0_IMIN_LINE; 350 351 /* Neoverse N1 erratum 1542419 */ 352 if (CPU_ID_NEOVERSEN1_P(ci->ci_id.ac_midr) && 353 __SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1) 354 ctr_el0_cpu &= ~CTR_EL0_DIC; 355 356 if (cii == 0) { 357 ctr_el0_usr = ctr_el0_cpu; 358 continue; 359 } 360 361 /* keep minimum cache line size, and worst DIC/IDC */ 362 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_DIC) | ~CTR_EL0_DIC; 363 ctr_el0_usr &= (ctr_el0_cpu & CTR_EL0_IDC) | ~CTR_EL0_IDC; 364 if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DMIN_LINE) < 365 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) { 366 ctr_el0_usr &= ~CTR_EL0_DMIN_LINE; 367 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_DMIN_LINE; 368 } 369 if ((ctr_el0_cpu & CTR_EL0_DIC) == 0 && 370 (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_IMIN_LINE) < 371 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) { 372 ctr_el0_usr &= ~CTR_EL0_IMIN_LINE; 373 ctr_el0_usr |= ctr_el0_cpu & CTR_EL0_IMIN_LINE; 374 } 375 } 376 377 where = xc_broadcast(0, 378 (xcfunc_t)configure_cpu_traps0, NULL, NULL); 379 xc_wait(where); 380 } 381 382 static enum emul_arm_result 383 emul_aarch64_insn(struct trapframe *tf) 384 { 385 uint32_t insn; 386 387 if (ufetch_32((uint32_t *)tf->tf_pc, &insn)) { 388 tf->tf_far = reg_far_el1_read(); 389 return EMUL_ARM_FAULT; 390 } 391 392 LE32TOH(insn); 393 if ((insn & 0xffffffe0) == 0xd53b0020) { 394 /* mrs x?,ctr_el0 */ 395 unsigned int Xt = insn & 31; 396 if (Xt != 31) { /* !xzr */ 397 uint64_t ctr_el0 = reg_ctr_el0_read(); 398 ctr_el0 &= ~CTR_EL0_USR_MASK; 399 ctr_el0 |= (ctr_el0_usr & CTR_EL0_USR_MASK); 400 tf->tf_reg[Xt] = ctr_el0; 401 } 402 curcpu()->ci_uct_trap.ev_count++; 403 404 } else { 405 return EMUL_ARM_UNKNOWN; 406 } 407 408 tf->tf_pc += 4; 409 return EMUL_ARM_SUCCESS; 410 } 411 412 void 413 trap_el0_sync(struct trapframe *tf) 414 { 415 struct lwp * const l = curlwp; 416 const uint32_t esr = tf->tf_esr; 417 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 418 419 #ifdef DDB 420 /* disable trace, and enable hardware breakpoint/watchpoint */ 421 reg_mdscr_el1_write( 422 (reg_mdscr_el1_read() & ~MDSCR_SS) | MDSCR_KDE); 423 #else 424 /* disable trace */ 425 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 426 #endif 427 /* enable traps and interrupts */ 428 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 429 430 switch (eclass) { 431 case ESR_EC_INSN_ABT_EL0: 432 case ESR_EC_DATA_ABT_EL0: 433 data_abort_handler(tf, eclass); 434 userret(l); 435 break; 436 437 case ESR_EC_SVC_A64: 438 (*l->l_proc->p_md.md_syscall)(tf); 439 break; 440 case ESR_EC_FP_ACCESS: 441 fpu_load(l); 442 userret(l); 443 break; 444 case ESR_EC_FP_TRAP_A64: 445 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 446 userret(l); 447 break; 448 449 case ESR_EC_PC_ALIGNMENT: 450 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 451 userret(l); 452 break; 453 case ESR_EC_SP_ALIGNMENT: 454 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr); 455 userret(l); 456 break; 457 458 case ESR_EC_BKPT_INSN_A64: 459 case ESR_EC_BRKPNT_EL0: 460 case ESR_EC_WTCHPNT_EL0: 461 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 462 userret(l); 463 break; 464 case ESR_EC_SW_STEP_EL0: 465 /* disable trace, and send trace trap */ 466 tf->tf_spsr &= ~SPSR_SS; 467 do_trapsignal(l, SIGTRAP, TRAP_TRACE, (void *)tf->tf_pc, esr); 468 userret(l); 469 break; 470 471 case ESR_EC_SYS_REG: 472 switch (emul_aarch64_insn(tf)) { 473 case EMUL_ARM_SUCCESS: 474 break; 475 case EMUL_ARM_UNKNOWN: 476 goto unknown; 477 case EMUL_ARM_FAULT: 478 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 479 (void *)tf->tf_far, esr); 480 break; 481 } 482 userret(l); 483 break; 484 485 default: 486 case ESR_EC_UNKNOWN: 487 unknown: 488 #ifdef DDB 489 if (sigill_debug) { 490 /* show illegal instruction */ 491 printf("TRAP: pid %d (%s), uid %d: %s:" 492 " esr=0x%lx: pc=0x%lx: %s\n", 493 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 494 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 495 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 496 strdisasm(tf->tf_pc, tf->tf_spsr)); 497 } 498 #endif 499 /* illegal or not implemented instruction */ 500 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 501 userret(l); 502 break; 503 } 504 } 505 506 void 507 cpu_irq(struct trapframe *tf) 508 { 509 struct cpu_info * const ci = curcpu(); 510 511 #ifdef STACKCHECKS 512 struct lwp *l = curlwp; 513 void *sp = (void *)reg_sp_read(); 514 if (l->l_addr >= sp) { 515 panic("lwp/interrupt stack overflow detected." 516 " lwp=%p, sp=%p, l_addr=%p", l, sp, l->l_addr); 517 } 518 #endif 519 520 #ifdef DDB 521 /* disable trace, and enable hardware breakpoint/watchpoint */ 522 reg_mdscr_el1_write( 523 (reg_mdscr_el1_read() & ~MDSCR_SS) | MDSCR_KDE); 524 #else 525 /* disable trace */ 526 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 527 #endif 528 /* enable traps */ 529 daif_enable(DAIF_D|DAIF_A); 530 531 ci->ci_intr_depth++; 532 ARM_IRQ_HANDLER(tf); 533 ci->ci_intr_depth--; 534 535 cpu_dosoftints(); 536 } 537 538 void 539 cpu_fiq(struct trapframe *tf) 540 { 541 struct cpu_info * const ci = curcpu(); 542 543 #ifdef STACKCHECKS 544 struct lwp *l = curlwp; 545 void *sp = (void *)reg_sp_read(); 546 if (l->l_addr >= sp) { 547 panic("lwp/interrupt stack overflow detected." 548 " lwp=%p, sp=%p, l_addr=%p", l, sp, l->l_addr); 549 } 550 #endif 551 552 /* disable trace */ 553 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 554 555 /* enable traps */ 556 daif_enable(DAIF_D|DAIF_A); 557 558 ci->ci_intr_depth++; 559 ARM_FIQ_HANDLER(tf); 560 ci->ci_intr_depth--; 561 562 cpu_dosoftints(); 563 } 564 565 #ifdef COMPAT_NETBSD32 566 567 /* 568 * 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3. 569 */ 570 #define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && ((hi) & 0x1800)) 571 572 int 573 fetch_arm_insn(uint64_t pc, uint64_t spsr, uint32_t *insn) 574 { 575 576 /* 577 * Instructions are stored in little endian for BE8, 578 * only a valid binary format for ILP32EB. Therefore, 579 * we need byte-swapping before decoding on aarch64eb. 580 */ 581 582 /* THUMB? */ 583 if (spsr & SPSR_A32_T) { 584 uint16_t *p = (uint16_t *)(pc & ~1UL); /* XXX */ 585 uint16_t hi, lo; 586 587 if (ufetch_16(p, &hi)) 588 return -1; 589 LE16TOH(hi); 590 591 if (!THUMB_32BIT(hi)) { 592 /* 16-bit Thumb instruction */ 593 *insn = hi; 594 return 2; 595 } 596 597 /* 32-bit Thumb instruction */ 598 if (ufetch_16(p + 1, &lo)) 599 return -1; 600 LE16TOH(lo); 601 602 *insn = ((uint32_t)hi << 16) | lo; 603 return 4; 604 } 605 606 if (ufetch_32((uint32_t *)pc, insn)) 607 return -1; 608 LE32TOH(*insn); 609 610 return 4; 611 } 612 613 static bool 614 arm_cond_match(uint32_t insn, uint64_t spsr) 615 { 616 bool invert = (insn >> 28) & 1; 617 bool match; 618 619 switch (insn >> 29) { 620 case 0: /* EQ or NE */ 621 match = spsr & SPSR_Z; 622 break; 623 case 1: /* CS/HI or CC/LO */ 624 match = spsr & SPSR_C; 625 break; 626 case 2: /* MI or PL */ 627 match = spsr & SPSR_N; 628 break; 629 case 3: /* VS or VC */ 630 match = spsr & SPSR_V; 631 break; 632 case 4: /* HI or LS */ 633 match = ((spsr & (SPSR_C | SPSR_Z)) == SPSR_C); 634 break; 635 case 5: /* GE or LT */ 636 match = (!(spsr & SPSR_N) == !(spsr & SPSR_V)); 637 break; 638 case 6: /* GT or LE */ 639 match = !(spsr & SPSR_Z) && 640 (!(spsr & SPSR_N) == !(spsr & SPSR_V)); 641 break; 642 case 7: /* AL */ 643 match = true; 644 break; 645 } 646 return (!match != !invert); 647 } 648 649 uint8_t atomic_swap_8(volatile uint8_t *, uint8_t); 650 651 static int 652 emul_arm_swp(uint32_t insn, struct trapframe *tf) 653 { 654 struct faultbuf fb; 655 vaddr_t vaddr; 656 uint32_t val; 657 int Rn, Rd, Rm, error; 658 659 Rn = __SHIFTOUT(insn, 0x000f0000); 660 Rd = __SHIFTOUT(insn, 0x0000f000); 661 Rm = __SHIFTOUT(insn, 0x0000000f); 662 663 vaddr = tf->tf_reg[Rn] & 0xffffffff; 664 val = tf->tf_reg[Rm]; 665 666 /* fault if insn is swp, and unaligned access */ 667 if ((insn & 0x00400000) == 0 && (vaddr & 3) != 0) { 668 tf->tf_far = vaddr; 669 return EFAULT; 670 } 671 672 /* vaddr will always point to userspace, since it has only 32bit */ 673 if ((error = cpu_set_onfault(&fb)) == 0) { 674 if (aarch64_pan_enabled) 675 reg_pan_write(0); /* disable PAN */ 676 if (insn & 0x00400000) { 677 /* swpb */ 678 val = atomic_swap_8((uint8_t *)vaddr, val); 679 } else { 680 /* swp */ 681 val = atomic_swap_32((uint32_t *)vaddr, val); 682 } 683 cpu_unset_onfault(); 684 tf->tf_reg[Rd] = val; 685 } else { 686 tf->tf_far = reg_far_el1_read(); 687 } 688 if (aarch64_pan_enabled) 689 reg_pan_write(1); /* enable PAN */ 690 return error; 691 } 692 693 static enum emul_arm_result 694 emul_thumb_insn(struct trapframe *tf, uint32_t insn, int insn_size) 695 { 696 /* T32-16bit or 32bit instructions */ 697 switch (insn_size) { 698 case 2: 699 /* Breakpoint used by GDB */ 700 if (insn == 0xdefe) { 701 do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT, 702 (void *)tf->tf_pc, 0); 703 return EMUL_ARM_SUCCESS; 704 } 705 /* XXX: some T32 IT instruction deprecated should be emulated */ 706 break; 707 case 4: 708 break; 709 default: 710 return EMUL_ARM_FAULT; 711 } 712 return EMUL_ARM_UNKNOWN; 713 } 714 715 static enum emul_arm_result 716 emul_arm_insn(struct trapframe *tf) 717 { 718 uint32_t insn; 719 int insn_size; 720 721 insn_size = fetch_arm_insn(tf->tf_pc, tf->tf_spsr, &insn); 722 tf->tf_far = reg_far_el1_read(); 723 724 if (tf->tf_spsr & SPSR_A32_T) 725 return emul_thumb_insn(tf, insn, insn_size); 726 if (insn_size != 4) 727 return EMUL_ARM_FAULT; 728 729 /* Breakpoint used by GDB */ 730 if (insn == 0xe6000011 || insn == 0xe7ffdefe) { 731 do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT, 732 (void *)tf->tf_pc, 0); 733 return EMUL_ARM_SUCCESS; 734 } 735 736 /* Unconditional instruction extension space? */ 737 if ((insn & 0xf0000000) == 0xf0000000) 738 goto unknown_insn; 739 740 /* swp,swpb */ 741 if ((insn & 0x0fb00ff0) == 0x01000090) { 742 if (arm_cond_match(insn, tf->tf_spsr)) { 743 if (emul_arm_swp(insn, tf) != 0) 744 return EMUL_ARM_FAULT; 745 } 746 goto emulated; 747 } 748 749 /* 750 * Emulate ARMv6 instructions with cache operations 751 * register (c7), that can be used in user mode. 752 */ 753 switch (insn & 0x0fff0fff) { 754 case 0x0e070f95: 755 if (arm_cond_match(insn, tf->tf_spsr)) { 756 /* 757 * mcr p15, 0, <Rd>, c7, c5, 4 758 * (flush prefetch buffer) 759 */ 760 isb(); 761 } 762 goto emulated; 763 case 0x0e070f9a: 764 if (arm_cond_match(insn, tf->tf_spsr)) { 765 /* 766 * mcr p15, 0, <Rd>, c7, c10, 4 767 * (data synchronization barrier) 768 */ 769 dsb(sy); 770 } 771 goto emulated; 772 case 0x0e070fba: 773 if (arm_cond_match(insn, tf->tf_spsr)) { 774 /* 775 * mcr p15, 0, <Rd>, c7, c10, 5 776 * (data memory barrier) 777 */ 778 dmb(sy); 779 } 780 goto emulated; 781 default: 782 break; 783 } 784 785 unknown_insn: 786 /* unknown, or unsupported instruction */ 787 return EMUL_ARM_UNKNOWN; 788 789 emulated: 790 tf->tf_pc += insn_size; 791 return EMUL_ARM_SUCCESS; 792 } 793 #endif /* COMPAT_NETBSD32 */ 794 795 void 796 trap_el0_32sync(struct trapframe *tf) 797 { 798 struct lwp * const l = curlwp; 799 const uint32_t esr = tf->tf_esr; 800 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 801 802 #ifdef DDB 803 /* disable trace, and enable hardware breakpoint/watchpoint */ 804 reg_mdscr_el1_write( 805 (reg_mdscr_el1_read() & ~MDSCR_SS) | MDSCR_KDE); 806 #else 807 /* disable trace */ 808 reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS); 809 #endif 810 /* enable traps and interrupts */ 811 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 812 813 switch (eclass) { 814 #ifdef COMPAT_NETBSD32 815 case ESR_EC_INSN_ABT_EL0: 816 case ESR_EC_DATA_ABT_EL0: 817 data_abort_handler(tf, eclass); 818 userret(l); 819 break; 820 821 case ESR_EC_SVC_A32: 822 (*l->l_proc->p_md.md_syscall)(tf); 823 break; 824 825 case ESR_EC_FP_ACCESS: 826 fpu_load(l); 827 userret(l); 828 break; 829 830 case ESR_EC_FP_TRAP_A32: 831 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 832 userret(l); 833 break; 834 835 case ESR_EC_PC_ALIGNMENT: 836 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 837 userret(l); 838 break; 839 840 case ESR_EC_SP_ALIGNMENT: 841 do_trapsignal(l, SIGBUS, BUS_ADRALN, 842 (void *)tf->tf_reg[13], esr); /* sp is r13 on AArch32 */ 843 userret(l); 844 break; 845 846 case ESR_EC_BKPT_INSN_A32: 847 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 848 userret(l); 849 break; 850 851 case ESR_EC_UNKNOWN: 852 switch (emul_arm_insn(tf)) { 853 case EMUL_ARM_SUCCESS: 854 break; 855 case EMUL_ARM_UNKNOWN: 856 goto unknown; 857 case EMUL_ARM_FAULT: 858 do_trapsignal(l, SIGSEGV, SEGV_MAPERR, 859 (void *)tf->tf_far, esr); 860 break; 861 } 862 userret(l); 863 break; 864 865 case ESR_EC_CP15_RT: 866 case ESR_EC_CP15_RRT: 867 case ESR_EC_CP14_RT: 868 case ESR_EC_CP14_DT: 869 case ESR_EC_CP14_RRT: 870 unknown: 871 #endif /* COMPAT_NETBSD32 */ 872 default: 873 #ifdef DDB 874 if (sigill_debug) { 875 /* show illegal instruction */ 876 printf("TRAP: pid %d (%s), uid %d: %s:" 877 " esr=0x%lx: pc=0x%lx: %s\n", 878 curlwp->l_proc->p_pid, curlwp->l_proc->p_comm, 879 l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1, 880 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 881 strdisasm(tf->tf_pc, tf->tf_spsr)); 882 } 883 #endif 884 /* illegal or not implemented instruction */ 885 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 886 userret(l); 887 break; 888 } 889 } 890 891 void 892 trap_el1h_error(struct trapframe *tf) 893 { 894 /* 895 * Normally, we should panic unconditionally, 896 * but SError interrupt may occur when accessing to unmapped(?) I/O 897 * spaces. bus_space_{peek,poke}_{1,2,4,8}() should trap these case. 898 */ 899 struct faultbuf *fb; 900 901 if (curcpu()->ci_intr_depth == 0) { 902 fb = cpu_disable_onfault(); 903 if (fb != NULL) { 904 cpu_jump_onfault(tf, fb, EFAULT); 905 return; 906 } 907 } 908 panic("%s", __func__); 909 } 910 911 #define bad_trap_panic(trapfunc) \ 912 void \ 913 trapfunc(struct trapframe *tf) \ 914 { \ 915 panic("%s", __func__); \ 916 } 917 bad_trap_panic(trap_el1t_sync) 918 bad_trap_panic(trap_el1t_irq) 919 bad_trap_panic(trap_el1t_fiq) 920 bad_trap_panic(trap_el1t_error) 921 bad_trap_panic(trap_el1h_fiq) 922 bad_trap_panic(trap_el0_fiq) 923 bad_trap_panic(trap_el0_error) 924 bad_trap_panic(trap_el0_32fiq) 925 bad_trap_panic(trap_el0_32error) 926 927 void 928 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int val) 929 { 930 tf->tf_reg[19] = fb->fb_reg[FB_X19]; 931 tf->tf_reg[20] = fb->fb_reg[FB_X20]; 932 tf->tf_reg[21] = fb->fb_reg[FB_X21]; 933 tf->tf_reg[22] = fb->fb_reg[FB_X22]; 934 tf->tf_reg[23] = fb->fb_reg[FB_X23]; 935 tf->tf_reg[24] = fb->fb_reg[FB_X24]; 936 tf->tf_reg[25] = fb->fb_reg[FB_X25]; 937 tf->tf_reg[26] = fb->fb_reg[FB_X26]; 938 tf->tf_reg[27] = fb->fb_reg[FB_X27]; 939 tf->tf_reg[28] = fb->fb_reg[FB_X28]; 940 tf->tf_reg[29] = fb->fb_reg[FB_X29]; 941 tf->tf_sp = fb->fb_reg[FB_SP]; 942 tf->tf_pc = fb->fb_reg[FB_LR]; 943 tf->tf_reg[0] = val; 944 } 945 946 #ifdef TRAP_SIGDEBUG 947 static void 948 frame_dump(const struct trapframe *tf) 949 { 950 const struct reg *r = &tf->tf_regs; 951 952 printf("trapframe %p\n", tf); 953 for (size_t i = 0; i < __arraycount(r->r_reg); i++) { 954 printf(" r%.2zu %#018" PRIx64 "%c", i, r->r_reg[i], 955 " \n"[i && (i & 1) == 0]); 956 } 957 958 printf("\n"); 959 printf(" sp %#018" PRIx64 " pc %#018" PRIx64 "\n", 960 r->r_sp, r->r_pc); 961 printf(" spsr %#018" PRIx64 " tpidr %#018" PRIx64 "\n", 962 r->r_spsr, r->r_tpidr); 963 printf(" esr %#018" PRIx64 " far %#018" PRIx64 "\n", 964 tf->tf_esr, tf->tf_far); 965 966 printf("\n"); 967 hexdump(printf, "Stack dump", tf, 256); 968 } 969 970 static void 971 sigdebug(const struct trapframe *tf, const ksiginfo_t *ksi) 972 { 973 struct lwp *l = curlwp; 974 struct proc *p = l->l_proc; 975 const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC); 976 977 printf("pid %d.%d (%s): signal %d (trap %#x) " 978 "@pc %#" PRIx64 ", addr %p, error=%s\n", 979 p->p_pid, l->l_lid, p->p_comm, ksi->ksi_signo, ksi->ksi_trap, 980 tf->tf_regs.r_pc, ksi->ksi_addr, eclass_trapname(eclass)); 981 frame_dump(tf); 982 } 983 #endif 984 985 void 986 do_trapsignal1( 987 #ifdef TRAP_SIGDEBUG 988 const char *func, 989 size_t line, 990 struct trapframe *tf, 991 #endif 992 struct lwp *l, int signo, int code, void *addr, int trap) 993 { 994 ksiginfo_t ksi; 995 996 KSI_INIT_TRAP(&ksi); 997 ksi.ksi_signo = signo; 998 ksi.ksi_code = code; 999 ksi.ksi_addr = addr; 1000 ksi.ksi_trap = trap; 1001 #ifdef TRAP_SIGDEBUG 1002 printf("%s, %zu: ", func, line); 1003 sigdebug(tf, &ksi); 1004 #endif 1005 (*l->l_proc->p_emul->e_trapsignal)(l, &ksi); 1006 } 1007 1008 bool 1009 cpu_intr_p(void) 1010 { 1011 uint64_t ncsw; 1012 int idepth; 1013 lwp_t *l; 1014 1015 #ifdef __HAVE_PIC_FAST_SOFTINTS 1016 /* XXX Copied from cpu.h. Looks incomplete - needs fixing. */ 1017 if (ci->ci_cpl < IPL_VM) 1018 return false; 1019 #endif 1020 1021 l = curlwp; 1022 if (__predict_false(l->l_cpu == NULL)) { 1023 KASSERT(l == &lwp0); 1024 return false; 1025 } 1026 do { 1027 ncsw = l->l_ncsw; 1028 __insn_barrier(); 1029 idepth = l->l_cpu->ci_intr_depth; 1030 __insn_barrier(); 1031 } while (__predict_false(ncsw != l->l_ncsw)); 1032 1033 return idepth > 0; 1034 } 1035
Indexes created Fri Oct 17 17:09:57 GMT 2025