trap.c revision 1.6
1 /* $NetBSD: trap.c,v 1.6 2018/07/19 18:27:26 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.6 2018/07/19 18:27:26 christos Exp $"); 35 36 #include "opt_arm_intr_impl.h" 37 #include "opt_compat_netbsd32.h" 38 39 #include <sys/param.h> 40 #include <sys/types.h> 41 #include <sys/atomic.h> 42 #include <sys/cpu.h> 43 #ifdef KDB 44 #include <sys/kdb.h> 45 #endif 46 #include <sys/proc.h> 47 #include <sys/systm.h> 48 #include <sys/signal.h> 49 #include <sys/signalvar.h> 50 #include <sys/siginfo.h> 51 52 #ifdef ARM_INTR_IMPL 53 #include ARM_INTR_IMPL 54 #else 55 #error ARM_INTR_IMPL not defined 56 #endif 57 58 #ifndef ARM_IRQ_HANDLER 59 #error ARM_IRQ_HANDLER not defined 60 #endif 61 62 #include <aarch64/userret.h> 63 #include <aarch64/frame.h> 64 #include <aarch64/machdep.h> 65 #include <aarch64/armreg.h> 66 #include <aarch64/locore.h> 67 68 #ifdef KDB 69 #include <machine/db_machdep.h> 70 #endif 71 #ifdef DDB 72 #include <ddb/db_output.h> 73 #include <machine/db_machdep.h> 74 #endif 75 76 77 const char * const trap_names[] = { 78 [ESR_EC_UNKNOWN] = "Unknown Reason (Illegal Instruction)", 79 [ESR_EC_SERROR] = "SError Interrupt", 80 [ESR_EC_WFX] = "WFI or WFE instruction execution", 81 [ESR_EC_ILL_STATE] = "Illegal Execution State", 82 83 [ESR_EC_SYS_REG] = "MSR/MRS/SYS instruction", 84 [ESR_EC_SVC_A64] = "SVC Instruction Execution", 85 [ESR_EC_HVC_A64] = "HVC Instruction Execution", 86 [ESR_EC_SMC_A64] = "SMC Instruction Execution", 87 88 [ESR_EC_INSN_ABT_EL0] = "Instruction Abort (EL0)", 89 [ESR_EC_INSN_ABT_EL1] = "Instruction Abort (EL1)", 90 [ESR_EC_DATA_ABT_EL0] = "Data Abort (EL0)", 91 [ESR_EC_DATA_ABT_EL1] = "Data Abort (EL1)", 92 93 [ESR_EC_PC_ALIGNMENT] = "Misaligned PC", 94 [ESR_EC_SP_ALIGNMENT] = "Misaligned SP", 95 96 [ESR_EC_FP_ACCESS] = "Access to SIMD/FP Registers", 97 [ESR_EC_FP_TRAP_A64] = "FP Exception", 98 99 [ESR_EC_BRKPNT_EL0] = "Breakpoint Exception (EL0)", 100 [ESR_EC_BRKPNT_EL1] = "Breakpoint Exception (EL1)", 101 [ESR_EC_SW_STEP_EL0] = "Software Step (EL0)", 102 [ESR_EC_SW_STEP_EL1] = "Software Step (EL1)", 103 [ESR_EC_WTCHPNT_EL0] = "Watchpoint (EL0)", 104 [ESR_EC_WTCHPNT_EL1] = "Watchpoint (EL1)", 105 [ESR_EC_BKPT_INSN_A64] = "BKPT Instruction Execution", 106 107 [ESR_EC_CP15_RT] = "A32: MCR/MRC access to CP15", 108 [ESR_EC_CP15_RRT] = "A32: MCRR/MRRC access to CP15", 109 [ESR_EC_CP14_RT] = "A32: MCR/MRC access to CP14", 110 [ESR_EC_CP14_DT] = "A32: LDC/STC access to CP14", 111 [ESR_EC_CP14_RRT] = "A32: MRRC access to CP14", 112 [ESR_EC_SVC_A32] = "A32: SVC Instruction Execution", 113 [ESR_EC_HVC_A32] = "A32: HVC Instruction Execution", 114 [ESR_EC_SMC_A32] = "A32: SMC Instruction Execution", 115 [ESR_EC_FPID] = "A32: MCR/MRC access to CP10", 116 [ESR_EC_FP_TRAP_A32] = "A32: FP Exception", 117 [ESR_EC_BKPT_INSN_A32] = "A32: BKPT Instruction Execution", 118 [ESR_EC_VECTOR_CATCH] = "A32: Vector Catch Exception" 119 }; 120 121 const char * 122 eclass_trapname(uint32_t eclass) 123 { 124 static char trapnamebuf[sizeof("Unknown trap 0x????????")]; 125 126 if (eclass >= __arraycount(trap_names) || trap_names[eclass] == NULL) { 127 snprintf(trapnamebuf, sizeof(trapnamebuf), 128 "Unknown trap %#02x", eclass); 129 return trapnamebuf; 130 } 131 return trap_names[eclass]; 132 } 133 134 void 135 userret(struct lwp *l) 136 { 137 mi_userret(l); 138 } 139 140 void 141 trap_doast(struct trapframe *tf) 142 { 143 struct lwp * const l = curlwp; 144 145 /* 146 * allow to have a chance of context switch just prior to user 147 * exception return. 148 */ 149 #ifdef __HAVE_PREEMPTION 150 kpreempt_disable(); 151 #endif 152 struct cpu_info * const ci = curcpu(); 153 154 ci->ci_data.cpu_ntrap++; 155 156 KDASSERT(ci->ci_cpl == IPL_NONE); 157 const int want_resched = ci->ci_want_resched; 158 #ifdef __HAVE_PREEMPTION 159 kpreempt_enable(); 160 #endif 161 162 if (l->l_pflag & LP_OWEUPC) { 163 l->l_pflag &= ~LP_OWEUPC; 164 ADDUPROF(l); 165 } 166 167 /* Allow a forced task switch. */ 168 if (want_resched) 169 preempt(); 170 userret(l); 171 } 172 173 void 174 trap_el1h_sync(struct trapframe *tf) 175 { 176 const uint32_t esr = tf->tf_esr; 177 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 178 179 /* re-enable traps and interrupts */ 180 if (!(tf->tf_spsr & SPSR_I)) 181 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 182 else 183 daif_enable(DAIF_D|DAIF_A); 184 185 switch (eclass) { 186 case ESR_EC_INSN_ABT_EL1: 187 case ESR_EC_DATA_ABT_EL1: 188 data_abort_handler(tf, eclass); 189 break; 190 191 case ESR_EC_BRKPNT_EL1: 192 case ESR_EC_SW_STEP_EL1: 193 case ESR_EC_WTCHPNT_EL1: 194 case ESR_EC_BKPT_INSN_A64: 195 #ifdef DDB 196 if (eclass == ESR_EC_BRKPNT_EL1) 197 kdb_trap(DB_TRAP_BREAKPOINT, tf); 198 else if (eclass == ESR_EC_BKPT_INSN_A64) 199 kdb_trap(DB_TRAP_BKPT_INSN, tf); 200 else if (eclass == ESR_EC_WTCHPNT_EL1) 201 kdb_trap(DB_TRAP_WATCHPOINT, tf); 202 else if (eclass == ESR_EC_SW_STEP_EL1) 203 kdb_trap(DB_TRAP_SW_STEP, tf); 204 else 205 kdb_trap(DB_TRAP_UNKNOWN, tf); 206 #else 207 panic("No debugger in kernel"); 208 #endif 209 break; 210 211 case ESR_EC_FP_ACCESS: 212 case ESR_EC_FP_TRAP_A64: 213 case ESR_EC_PC_ALIGNMENT: 214 case ESR_EC_SP_ALIGNMENT: 215 case ESR_EC_ILL_STATE: 216 default: 217 panic("Trap: fatal %s: pc=%016" PRIx64 "sp=%016" PRIx64 218 "esr=%08x", eclass_trapname(eclass), tf->tf_pc, tf->tf_sp, 219 esr); 220 break; 221 } 222 } 223 224 void 225 trap_el0_sync(struct trapframe *tf) 226 { 227 struct lwp * const l = curlwp; 228 const uint32_t esr = tf->tf_esr; 229 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 230 231 /* enable traps and interrupts */ 232 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 233 234 switch (eclass) { 235 case ESR_EC_INSN_ABT_EL0: 236 case ESR_EC_DATA_ABT_EL0: 237 data_abort_handler(tf, eclass); 238 userret(l); 239 break; 240 241 case ESR_EC_SVC_A64: 242 (*l->l_proc->p_md.md_syscall)(tf); 243 break; 244 case ESR_EC_FP_ACCESS: 245 fpu_load(l); 246 userret(l); 247 break; 248 case ESR_EC_FP_TRAP_A64: 249 do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */ 250 userret(l); 251 break; 252 253 case ESR_EC_PC_ALIGNMENT: 254 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 255 userret(l); 256 break; 257 case ESR_EC_SP_ALIGNMENT: 258 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr); 259 userret(l); 260 break; 261 262 case ESR_EC_BKPT_INSN_A64: 263 case ESR_EC_BRKPNT_EL0: 264 case ESR_EC_SW_STEP_EL0: 265 case ESR_EC_WTCHPNT_EL0: 266 /* XXX notyet */ 267 do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr); 268 userret(l); 269 break; 270 271 default: 272 /* XXX notyet */ 273 case ESR_EC_UNKNOWN: 274 /* illegal or not implemented instruction */ 275 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 276 userret(l); 277 break; 278 } 279 } 280 281 void 282 interrupt(struct trapframe *tf) 283 { 284 struct cpu_info * const ci = curcpu(); 285 286 /* enable traps */ 287 daif_enable(DAIF_D|DAIF_A); 288 289 ci->ci_intr_depth++; 290 ARM_IRQ_HANDLER(tf); 291 ci->ci_intr_depth--; 292 293 cpu_dosoftints(); 294 } 295 296 void 297 trap_el0_32sync(struct trapframe *tf) 298 { 299 struct lwp * const l = curlwp; 300 const uint32_t esr = tf->tf_esr; 301 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ 302 303 /* enable traps and interrupts */ 304 daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F); 305 306 switch (eclass) { 307 case ESR_EC_FP_ACCESS: 308 fpu_load(l); 309 userret(l); 310 break; 311 312 case ESR_EC_INSN_ABT_EL0: 313 case ESR_EC_DATA_ABT_EL0: 314 data_abort_handler(tf, eclass); 315 userret(l); 316 break; 317 318 case ESR_EC_PC_ALIGNMENT: 319 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr); 320 userret(l); 321 break; 322 case ESR_EC_SP_ALIGNMENT: 323 do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr); 324 userret(l); 325 break; 326 327 #ifdef COMPAT_NETBSD32 328 case ESR_EC_SVC_A32: 329 (*l->l_proc->p_md.md_syscall)(tf); 330 break; 331 case ESR_EC_CP15_RT: 332 case ESR_EC_CP15_RRT: 333 case ESR_EC_CP14_RT: 334 case ESR_EC_CP14_DT: 335 case ESR_EC_CP14_RRT: 336 case ESR_EC_FP_TRAP_A32: 337 case ESR_EC_BKPT_INSN_A32: 338 /* XXX notyet */ 339 printf("%s:%d: %s\n", __func__, __LINE__, 340 eclass_trapname(eclass)); 341 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 342 userret(l); 343 break; 344 #endif /* COMPAT_NETBSD32 */ 345 default: 346 /* XXX notyet */ 347 printf("%s:%d: %s\n", __func__, __LINE__, 348 eclass_trapname(eclass)); 349 do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr); 350 userret(l); 351 break; 352 } 353 } 354 355 #define bad_trap_panic(trapfunc) \ 356 void \ 357 trapfunc(struct trapframe *tf) \ 358 { \ 359 panic("%s", __func__); \ 360 } 361 bad_trap_panic(trap_el1t_sync) 362 bad_trap_panic(trap_el1t_irq) 363 bad_trap_panic(trap_el1t_fiq) 364 bad_trap_panic(trap_el1t_error) 365 bad_trap_panic(trap_el1h_fiq) 366 bad_trap_panic(trap_el1h_error) 367 bad_trap_panic(trap_el0_fiq) 368 bad_trap_panic(trap_el0_error) 369 bad_trap_panic(trap_el0_32fiq) 370 bad_trap_panic(trap_el0_32error) 371 372 void 373 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int val) 374 { 375 tf->tf_reg[19] = fb->fb_reg[FB_X19]; 376 tf->tf_reg[20] = fb->fb_reg[FB_X20]; 377 tf->tf_reg[21] = fb->fb_reg[FB_X21]; 378 tf->tf_reg[22] = fb->fb_reg[FB_X22]; 379 tf->tf_reg[23] = fb->fb_reg[FB_X23]; 380 tf->tf_reg[24] = fb->fb_reg[FB_X24]; 381 tf->tf_reg[25] = fb->fb_reg[FB_X25]; 382 tf->tf_reg[26] = fb->fb_reg[FB_X26]; 383 tf->tf_reg[27] = fb->fb_reg[FB_X27]; 384 tf->tf_reg[28] = fb->fb_reg[FB_X28]; 385 tf->tf_reg[29] = fb->fb_reg[FB_X29]; 386 tf->tf_sp = fb->fb_reg[FB_SP]; 387 tf->tf_pc = fb->fb_reg[FB_LR]; 388 tf->tf_reg[0] = val; 389 } 390 391 void 392 ucas_ras_check(struct trapframe *tf) 393 { 394 #if 0 /* XXX notyet */ 395 extern char ucas_32_ras_start[]; 396 extern char ucas_32_ras_end[]; 397 extern char ucas_64_ras_start[]; 398 extern char ucas_64_ras_end[]; 399 400 if (tf->tf_pc > (vaddr_t)ucas_32_ras_start && 401 tf->tf_pc < (vaddr_t)ucas_32_ras_end) { 402 tf->tf_pc = (vaddr_t)ucas_32_ras_start; 403 } else if (tf->tf_pc > (vaddr_t)ucas_64_ras_start && 404 tf->tf_pc < (vaddr_t)ucas_64_ras_end) { 405 tf->tf_pc = (vaddr_t)ucas_64_ras_start; 406 } 407 #endif 408 } 409 410 int 411 kcopy(const void *src, void *dst, size_t len) 412 { 413 struct faultbuf fb; 414 int error; 415 416 if ((error = cpu_set_onfault(&fb)) == 0) { 417 memcpy(dst, src, len); 418 cpu_unset_onfault(); 419 } 420 return error; 421 } 422 423 int 424 copystr(const void *kfaddr, void *kdaddr, size_t len, size_t *done) 425 { 426 struct faultbuf fb; 427 size_t i; 428 int error; 429 const char *src = kfaddr; 430 char *dst = kdaddr; 431 432 if ((error = cpu_set_onfault(&fb)) == 0) { 433 for (i = 0; i < len; i++) { 434 if ((*dst++ = *src++) == '\0') { 435 i++; 436 error = 0; 437 goto done; 438 } 439 } 440 error = ENAMETOOLONG; 441 done: 442 if (done != NULL) 443 *done = i; 444 cpu_unset_onfault(); 445 } 446 return error; 447 } 448 449 #ifdef TRAP_SIGDEBUG 450 static void 451 frame_dump(const struct trapframe *tf) 452 { 453 const struct reg *r = &tf->tf_regs; 454 455 printf("trapframe %p\n", tf); 456 for (size_t i = 0; i < __arraycount(r->r_reg); i++) { 457 printf(" r%.2zu %#018%s" PRIx64, i, r->r_reg[i], 458 " \n"[i && (i & 1) == 0]); 459 } 460 461 printf("\n"); 462 printf(" sp %#018" PRIx64 " pc %#018" PRIx64 "\n", 463 r->r_sp, r->r_pc); 464 printf(" spsr %#018" PRIx64 " tpidr %#018" PRIx64 "\n", 465 r->r_spsr, r->r_tpidr); 466 printf(" esr %#018" PRIx64 " far %#018" PRIx64 "\n", 467 tf->tf_esr, tf->tf_far); 468 469 printf("\n"); 470 hexdump(printf, "Stack dump", tf, 256); 471 } 472 473 static void 474 sigdebug(const struct trapframe *tf, const ksiginfo_t *ksi) 475 { 476 struct lwp *l = curlwp; 477 struct proc *p = l->l_proc; 478 const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC); 479 480 printf("pid %d.%d (%s): signal %d (trap %#x) " 481 "@pc %#" PRIx64 ", addr %p, error=%s\n", 482 p->p_pid, l->l_lid, p->p_comm, ksi->ksi_signo, ksi->ksi_trap, 483 tf->tf_regs.r_pc, ksi->ksi_addr, eclass_trapname(eclass)); 484 frame_dump(tf); 485 } 486 #endif 487 488 void do_trapsignal1( 489 #ifdef TRAP_SIGDEBUG 490 const char *func, 491 size_t line, 492 struct trapframe *tf, 493 #endif 494 struct lwp *l, int signo, int code, void *addr, int trap) 495 { 496 ksiginfo_t ksi; 497 498 KSI_INIT_TRAP(&ksi); 499 ksi.ksi_signo = signo; 500 ksi.ksi_code = code; 501 ksi.ksi_addr = addr; 502 ksi.ksi_trap = trap; 503 #ifdef TRAP_SIGDEBUG 504 printf("%s, %zu: ", func, line); 505 sigdebug(tf, &ksi); 506 #endif 507 (*l->l_proc->p_emul->e_trapsignal)(l, &ksi); 508 } 509
Indexes created Wed Oct 15 07:09:58 GMT 2025