cpu.h revision 1.45
1 /* $NetBSD: cpu.h,v 1.45 2021/11/02 11:26:03 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_CPU_H_ 33 #define _AARCH64_CPU_H_ 34 35 #include <arm/cpu.h> 36 37 #ifdef __aarch64__ 38 39 #ifdef _KERNEL_OPT 40 #include "opt_gprof.h" 41 #include "opt_multiprocessor.h" 42 #endif 43 44 #include <sys/param.h> 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #include <sys/evcnt.h> 48 49 #include <aarch64/armreg.h> 50 #include <aarch64/frame.h> 51 52 struct clockframe { 53 struct trapframe cf_tf; 54 }; 55 56 /* (spsr & 15) == SPSR_M_EL0T(64bit,0) or USER(32bit,0) */ 57 #define CLKF_USERMODE(cf) ((((cf)->cf_tf.tf_spsr) & 0x0f) == 0) 58 #define CLKF_PC(cf) ((cf)->cf_tf.tf_pc) 59 #define CLKF_INTR(cf) ((void)(cf), curcpu()->ci_intr_depth > 1) 60 61 /* 62 * LWP_PC: Find out the program counter for the given lwp. 63 */ 64 #define LWP_PC(l) ((l)->l_md.md_utf->tf_pc) 65 66 #include <sys/cpu_data.h> 67 #include <sys/device_if.h> 68 #include <sys/intr.h> 69 70 struct aarch64_cpufuncs { 71 void (*cf_set_ttbr0)(uint64_t); 72 void (*cf_icache_sync_range)(vaddr_t, vsize_t); 73 }; 74 75 #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 76 77 struct aarch64_cache_unit { 78 u_int cache_type; 79 #define CACHE_TYPE_VPIPT 0 /* VMID-aware PIPT */ 80 #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 81 #define CACHE_TYPE_VIPT 2 82 #define CACHE_TYPE_PIPT 3 83 u_int cache_line_size; 84 u_int cache_ways; 85 u_int cache_sets; 86 u_int cache_way_size; 87 u_int cache_size; 88 }; 89 90 struct aarch64_cache_info { 91 u_int cacheable; 92 #define CACHE_CACHEABLE_NONE 0 93 #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 94 #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 95 #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 96 #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 97 struct aarch64_cache_unit icache; 98 struct aarch64_cache_unit dcache; 99 }; 100 101 struct cpu_info { 102 struct cpu_data ci_data; 103 device_t ci_dev; 104 cpuid_t ci_cpuid; 105 106 /* 107 * the following are in their own cache line, as they are stored to 108 * regularly by remote CPUs; when they were mixed with other fields 109 * we observed frequent cache misses. 110 */ 111 int ci_want_resched __aligned(COHERENCY_UNIT); 112 /* XXX pending IPIs? */ 113 114 /* 115 * this is stored frequently, and is fetched by remote CPUs. 116 */ 117 struct lwp *ci_curlwp __aligned(COHERENCY_UNIT); 118 struct lwp *ci_onproc; 119 120 /* 121 * largely CPU-private. 122 */ 123 struct lwp *ci_softlwps[SOFTINT_COUNT] __aligned(COHERENCY_UNIT); 124 125 uint64_t ci_lastintr; 126 127 int ci_mtx_oldspl; 128 int ci_mtx_count; 129 130 int ci_cpl; /* current processor level (spl) */ 131 int ci_hwpl; /* current hardware priority */ 132 volatile u_int ci_softints; 133 volatile u_int ci_intr_depth; 134 volatile uint32_t ci_blocked_pics; 135 volatile uint32_t ci_pending_pics; 136 volatile uint32_t ci_pending_ipls; 137 void *ci_splx_restart; 138 int ci_splx_savedipl; 139 140 int ci_kfpu_spl; 141 142 /* ASID of current pmap */ 143 tlb_asid_t ci_pmap_asid_cur; 144 145 /* event counters */ 146 struct evcnt ci_vfp_use; 147 struct evcnt ci_vfp_reuse; 148 struct evcnt ci_vfp_save; 149 struct evcnt ci_vfp_release; 150 struct evcnt ci_uct_trap; 151 struct evcnt ci_intr_preempt; 152 153 /* FDT or similar supplied "cpu capacity" */ 154 uint32_t ci_capacity_dmips_mhz; 155 156 /* interrupt controller */ 157 u_int ci_gic_redist; /* GICv3 redistributor index */ 158 uint64_t ci_gic_sgir; /* GICv3 SGIR target */ 159 160 /* ACPI */ 161 uint32_t ci_acpiid; /* ACPI Processor Unique ID */ 162 163 /* cached system registers */ 164 uint64_t ci_sctlr_el1; 165 uint64_t ci_sctlr_el2; 166 167 /* sysctl(9) exposed system registers */ 168 struct aarch64_sysctl_cpu_id ci_id; 169 170 /* cache information and function pointers */ 171 struct aarch64_cache_info ci_cacheinfo[MAX_CACHE_LEVEL]; 172 struct aarch64_cpufuncs ci_cpufuncs; 173 174 #if defined(GPROF) && defined(MULTIPROCESSOR) 175 struct gmonparam *ci_gmon; /* MI per-cpu GPROF */ 176 #endif 177 } __aligned(COHERENCY_UNIT); 178 179 #ifdef _KERNEL 180 static inline __always_inline struct lwp * __attribute__ ((const)) 181 aarch64_curlwp(void) 182 { 183 struct lwp *l; 184 __asm("mrs %0, tpidr_el1" : "=r"(l)); 185 return l; 186 } 187 188 /* forward declaration; defined in sys/lwp.h. */ 189 static __inline struct cpu_info *lwp_getcpu(struct lwp *); 190 191 #define curcpu() (lwp_getcpu(aarch64_curlwp())) 192 #define setsoftast(ci) (cpu_signotify((ci)->ci_onproc)) 193 #undef curlwp 194 #define curlwp (aarch64_curlwp()) 195 196 void cpu_signotify(struct lwp *l); 197 void cpu_need_proftick(struct lwp *l); 198 199 void cpu_hatch(struct cpu_info *); 200 201 extern struct cpu_info *cpu_info[]; 202 extern struct cpu_info cpu_info_store[]; 203 204 #define CPU_INFO_ITERATOR int 205 #if defined(MULTIPROCESSOR) || defined(_MODULE) 206 #define cpu_number() (curcpu()->ci_index) 207 #define CPU_IS_PRIMARY(ci) ((ci)->ci_index == 0) 208 #define CPU_INFO_FOREACH(cii, ci) \ 209 cii = 0, ci = cpu_info[0]; \ 210 cii < (ncpu ? ncpu : 1) && (ci = cpu_info[cii]) != NULL; \ 211 cii++ 212 #else /* MULTIPROCESSOR */ 213 #define cpu_number() 0 214 #define CPU_IS_PRIMARY(ci) true 215 #define CPU_INFO_FOREACH(cii, ci) \ 216 cii = 0, __USE(cii), ci = curcpu(); ci != NULL; ci = NULL 217 #endif /* MULTIPROCESSOR */ 218 219 #define LWP0_CPU_INFO (&cpu_info_store[0]) 220 221 #define __HAVE_CPU_DOSOFTINTS_CI 222 223 static inline void 224 cpu_dosoftints_ci(struct cpu_info *ci) 225 { 226 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 227 void dosoftints(void); 228 229 if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) { 230 dosoftints(); 231 } 232 #endif 233 } 234 235 static inline void 236 cpu_dosoftints(void) 237 { 238 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 239 cpu_dosoftints_ci(curcpu()); 240 #endif 241 } 242 243 244 #endif /* _KERNEL */ 245 246 #endif /* _KERNEL || _KMEMUSER */ 247 248 #endif 249 250 #endif /* _AARCH64_CPU_H_ */ 251
Indexes created Tue Sep 30 20:09:53 GMT 2025