cpufunc.h revision 1.1.2.4
1 1.1.2.4 pgoyette /* $NetBSD: cpufunc.h,v 1.1.2.4 2018/09/06 06:55:23 pgoyette Exp $ */ 2 1.1.2.2 pgoyette 3 1.1.2.2 pgoyette /* 4 1.1.2.2 pgoyette * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 1.1.2.2 pgoyette * All rights reserved. 6 1.1.2.2 pgoyette * 7 1.1.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.1.2.2 pgoyette * are met: 10 1.1.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.1.2.2 pgoyette * 16 1.1.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 pgoyette * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 1.1.2.2 pgoyette * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 1.1.2.2 pgoyette * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 1.1.2.2 pgoyette * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 1.1.2.2 pgoyette * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 1.1.2.2 pgoyette * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 pgoyette * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 1.1.2.2 pgoyette * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 1.1.2.2 pgoyette * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1.2.2 pgoyette * POSSIBILITY OF SUCH DAMAGE. 27 1.1.2.2 pgoyette */ 28 1.1.2.2 pgoyette 29 1.1.2.2 pgoyette #ifndef _AARCH64_CPUFUNC_H_ 30 1.1.2.2 pgoyette #define _AARCH64_CPUFUNC_H_ 31 1.1.2.2 pgoyette 32 1.1.2.2 pgoyette #ifdef _KERNEL 33 1.1.2.2 pgoyette 34 1.1.2.2 pgoyette #include <arm/armreg.h> 35 1.1.2.2 pgoyette 36 1.1.2.2 pgoyette static inline int 37 1.1.2.2 pgoyette set_cpufuncs(void) 38 1.1.2.2 pgoyette { 39 1.1.2.2 pgoyette return 0; 40 1.1.2.2 pgoyette } 41 1.1.2.2 pgoyette 42 1.1.2.2 pgoyette struct aarch64_cache_unit { 43 1.1.2.2 pgoyette u_int cache_type; 44 1.1.2.2 pgoyette #define CACHE_TYPE_UNKNOWN 0 45 1.1.2.2 pgoyette #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 46 1.1.2.2 pgoyette #define CACHE_TYPE_VIPT 2 47 1.1.2.2 pgoyette #define CACHE_TYPE_PIPT 3 48 1.1.2.2 pgoyette u_int cache_line_size; 49 1.1.2.2 pgoyette u_int cache_ways; 50 1.1.2.2 pgoyette u_int cache_sets; 51 1.1.2.2 pgoyette u_int cache_way_size; 52 1.1.2.2 pgoyette u_int cache_size; 53 1.1.2.2 pgoyette u_int cache_purging; 54 1.1.2.2 pgoyette #define CACHE_PURGING_WB 0x01 55 1.1.2.2 pgoyette #define CACHE_PURGING_WT 0x02 56 1.1.2.2 pgoyette #define CACHE_PURGING_RA 0x04 57 1.1.2.2 pgoyette #define CACHE_PURGING_WA 0x08 58 1.1.2.2 pgoyette }; 59 1.1.2.2 pgoyette 60 1.1.2.2 pgoyette struct aarch64_cache_info { 61 1.1.2.2 pgoyette u_int cacheable; 62 1.1.2.2 pgoyette #define CACHE_CACHEABLE_NONE 0 63 1.1.2.2 pgoyette #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 64 1.1.2.2 pgoyette #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 65 1.1.2.2 pgoyette #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 66 1.1.2.2 pgoyette #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 67 1.1.2.2 pgoyette struct aarch64_cache_unit icache; 68 1.1.2.2 pgoyette struct aarch64_cache_unit dcache; 69 1.1.2.2 pgoyette }; 70 1.1.2.2 pgoyette 71 1.1.2.2 pgoyette #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 72 1.1.2.2 pgoyette extern struct aarch64_cache_info aarch64_cache_info[MAX_CACHE_LEVEL]; 73 1.1.2.2 pgoyette extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 74 1.1.2.2 pgoyette extern u_int aarch64_cache_prefer_mask; 75 1.1.2.2 pgoyette extern u_int cputype; /* compat arm */ 76 1.1.2.2 pgoyette 77 1.1.2.4 pgoyette void aarch64_getcacheinfo(void); 78 1.1.2.4 pgoyette void aarch64_printcacheinfo(device_t); 79 1.1.2.2 pgoyette 80 1.1.2.2 pgoyette void aarch64_dcache_wbinv_all(void); 81 1.1.2.2 pgoyette void aarch64_dcache_inv_all(void); 82 1.1.2.2 pgoyette void aarch64_dcache_wb_all(void); 83 1.1.2.2 pgoyette void aarch64_icache_inv_all(void); 84 1.1.2.2 pgoyette 85 1.1.2.2 pgoyette /* cache op in cpufunc_asm_armv8.S */ 86 1.1.2.2 pgoyette void aarch64_nullop(void); 87 1.1.2.2 pgoyette uint32_t aarch64_cpuid(void); 88 1.1.2.2 pgoyette void aarch64_icache_sync_range(vaddr_t, vsize_t); 89 1.1.2.2 pgoyette void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 90 1.1.2.2 pgoyette void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 91 1.1.2.2 pgoyette void aarch64_dcache_inv_range(vaddr_t, vsize_t); 92 1.1.2.2 pgoyette void aarch64_dcache_wb_range(vaddr_t, vsize_t); 93 1.1.2.3 pgoyette void aarch64_icache_inv_all(void); 94 1.1.2.2 pgoyette void aarch64_drain_writebuf(void); 95 1.1.2.2 pgoyette 96 1.1.2.2 pgoyette /* tlb op in cpufunc_asm_armv8.S */ 97 1.1.2.2 pgoyette void aarch64_set_ttbr0(uint64_t); 98 1.1.2.2 pgoyette void aarch64_tlbi_all(void); /* all ASID, all VA */ 99 1.1.2.2 pgoyette void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 100 1.1.2.2 pgoyette void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 101 1.1.2.2 pgoyette void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 102 1.1.2.2 pgoyette void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 103 1.1.2.2 pgoyette void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 104 1.1.2.2 pgoyette 105 1.1.2.2 pgoyette 106 1.1.2.2 pgoyette /* misc */ 107 1.1.2.2 pgoyette #define cpu_idnum() aarch64_cpuid() 108 1.1.2.2 pgoyette 109 1.1.2.2 pgoyette /* cache op */ 110 1.1.2.2 pgoyette 111 1.1.2.2 pgoyette #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 112 1.1.2.2 pgoyette #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 113 1.1.2.2 pgoyette #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 114 1.1.2.2 pgoyette #define cpu_idcache_wbinv_all() \ 115 1.1.2.2 pgoyette (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 116 1.1.2.2 pgoyette #define cpu_icache_sync_all() \ 117 1.1.2.2 pgoyette (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 118 1.1.2.3 pgoyette #define cpu_icache_inv_all() aarch64_icache_inv_all() 119 1.1.2.2 pgoyette 120 1.1.2.2 pgoyette #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 121 1.1.2.2 pgoyette #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 122 1.1.2.2 pgoyette #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 123 1.1.2.2 pgoyette #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 124 1.1.2.2 pgoyette #define cpu_icache_sync_range(v,s) aarch64_icache_sync_range((v),(s)) 125 1.1.2.2 pgoyette 126 1.1.2.2 pgoyette #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 127 1.1.2.2 pgoyette #define cpu_sdcache_inv_range(v,p,s) ((void)0) 128 1.1.2.2 pgoyette #define cpu_sdcache_wb_range(v,p,s) ((void)0) 129 1.1.2.2 pgoyette 130 1.1.2.2 pgoyette /* others */ 131 1.1.2.2 pgoyette #define cpu_drain_writebuf() aarch64_drain_writebuf() 132 1.1.2.2 pgoyette 133 1.1.2.2 pgoyette extern u_int arm_dcache_align; 134 1.1.2.2 pgoyette extern u_int arm_dcache_align_mask; 135 1.1.2.2 pgoyette 136 1.1.2.2 pgoyette static inline bool 137 1.1.2.2 pgoyette cpu_gtmr_exists_p(void) 138 1.1.2.2 pgoyette { 139 1.1.2.2 pgoyette 140 1.1.2.2 pgoyette return true; 141 1.1.2.2 pgoyette } 142 1.1.2.2 pgoyette 143 1.1.2.2 pgoyette static inline u_int 144 1.1.2.2 pgoyette cpu_clusterid(void) 145 1.1.2.2 pgoyette { 146 1.1.2.2 pgoyette 147 1.1.2.2 pgoyette return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 148 1.1.2.2 pgoyette } 149 1.1.2.2 pgoyette 150 1.1.2.2 pgoyette static inline bool 151 1.1.2.2 pgoyette cpu_earlydevice_va_p(void) 152 1.1.2.2 pgoyette { 153 1.1.2.2 pgoyette 154 1.1.2.2 pgoyette return false; 155 1.1.2.2 pgoyette } 156 1.1.2.2 pgoyette 157 1.1.2.2 pgoyette #endif /* _KERNEL */ 158 1.1.2.2 pgoyette 159 1.1.2.2 pgoyette #endif /* _AARCH64_CPUFUNC_H_ */ 160
Indexes created Thu Oct 23 22:10:10 GMT 2025