cpufunc.h revision 1.1
1 /* $NetBSD: cpufunc.h,v 1.1 2018/04/01 04:35:03 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 36 static inline int 37 set_cpufuncs(void) 38 { 39 return 0; 40 } 41 42 struct aarch64_cache_unit { 43 u_int cache_type; 44 #define CACHE_TYPE_UNKNOWN 0 45 #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 46 #define CACHE_TYPE_VIPT 2 47 #define CACHE_TYPE_PIPT 3 48 u_int cache_line_size; 49 u_int cache_ways; 50 u_int cache_sets; 51 u_int cache_way_size; 52 u_int cache_size; 53 u_int cache_purging; 54 #define CACHE_PURGING_WB 0x01 55 #define CACHE_PURGING_WT 0x02 56 #define CACHE_PURGING_RA 0x04 57 #define CACHE_PURGING_WA 0x08 58 }; 59 60 struct aarch64_cache_info { 61 u_int cacheable; 62 #define CACHE_CACHEABLE_NONE 0 63 #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 64 #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 65 #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 66 #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 67 struct aarch64_cache_unit icache; 68 struct aarch64_cache_unit dcache; 69 }; 70 71 #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 72 extern struct aarch64_cache_info aarch64_cache_info[MAX_CACHE_LEVEL]; 73 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 74 extern u_int aarch64_cache_prefer_mask; 75 extern u_int cputype; /* compat arm */ 76 77 int aarch64_getcacheinfo(void); 78 79 void aarch64_dcache_wbinv_all(void); 80 void aarch64_dcache_inv_all(void); 81 void aarch64_dcache_wb_all(void); 82 void aarch64_icache_inv_all(void); 83 84 /* cache op in cpufunc_asm_armv8.S */ 85 void aarch64_nullop(void); 86 uint32_t aarch64_cpuid(void); 87 void aarch64_icache_sync_range(vaddr_t, vsize_t); 88 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 89 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 90 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 91 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 92 void aarch64_drain_writebuf(void); 93 94 /* tlb op in cpufunc_asm_armv8.S */ 95 void aarch64_set_ttbr0(uint64_t); 96 void aarch64_tlbi_all(void); /* all ASID, all VA */ 97 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 98 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 99 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 100 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 101 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 102 103 104 /* misc */ 105 #define cpu_idnum() aarch64_cpuid() 106 107 /* cache op */ 108 109 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 110 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 111 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 112 #define cpu_idcache_wbinv_all() \ 113 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 114 #define cpu_icache_sync_all() \ 115 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 116 117 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 118 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 119 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 120 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 121 #define cpu_icache_sync_range(v,s) aarch64_icache_sync_range((v),(s)) 122 123 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 124 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 125 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 126 127 /* others */ 128 #define cpu_drain_writebuf() aarch64_drain_writebuf() 129 130 extern u_int arm_dcache_align; 131 extern u_int arm_dcache_align_mask; 132 133 static inline bool 134 cpu_gtmr_exists_p(void) 135 { 136 137 return true; 138 } 139 140 static inline u_int 141 cpu_clusterid(void) 142 { 143 144 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 145 } 146 147 static inline bool 148 cpu_earlydevice_va_p(void) 149 { 150 151 return false; 152 } 153 154 #endif /* _KERNEL */ 155 156 #endif /* _AARCH64_CPUFUNC_H_ */ 157
Indexes created Wed Oct 01 15:09:59 GMT 2025