cpufunc.h revision 1.12
1 /* $NetBSD: cpufunc.h,v 1.12 2020/04/12 07:49:58 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 struct aarch64_cache_unit { 38 u_int cache_type; 39 #define CACHE_TYPE_UNKNOWN 0 40 #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 41 #define CACHE_TYPE_VIPT 2 42 #define CACHE_TYPE_PIPT 3 43 u_int cache_line_size; 44 u_int cache_ways; 45 u_int cache_sets; 46 u_int cache_way_size; 47 u_int cache_size; 48 u_int cache_purging; 49 #define CACHE_PURGING_WB 0x01 50 #define CACHE_PURGING_WT 0x02 51 #define CACHE_PURGING_RA 0x04 52 #define CACHE_PURGING_WA 0x08 53 }; 54 55 struct aarch64_cache_info { 56 u_int cacheable; 57 #define CACHE_CACHEABLE_NONE 0 58 #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 59 #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 60 #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 61 #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 62 struct aarch64_cache_unit icache; 63 struct aarch64_cache_unit dcache; 64 }; 65 66 #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 67 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 68 extern u_int aarch64_cache_prefer_mask; 69 extern u_int cputype; /* compat arm */ 70 71 extern int aarch64_pac_enabled; 72 73 void aarch64_pac_init(int); 74 75 int set_cpufuncs(void); 76 void aarch64_getcacheinfo(int); 77 void aarch64_printcacheinfo(device_t); 78 79 void aarch64_dcache_wbinv_all(void); 80 void aarch64_dcache_inv_all(void); 81 void aarch64_dcache_wb_all(void); 82 void aarch64_icache_inv_all(void); 83 84 /* cache op in cpufunc_asm_armv8.S */ 85 void aarch64_nullop(void); 86 uint32_t aarch64_cpuid(void); 87 void aarch64_icache_sync_range(vaddr_t, vsize_t); 88 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 89 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 90 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 91 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 92 void aarch64_icache_inv_all(void); 93 void aarch64_drain_writebuf(void); 94 95 /* tlb op in cpufunc_asm_armv8.S */ 96 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 97 void aarch64_set_ttbr0(uint64_t); 98 void aarch64_set_ttbr0_thunderx(uint64_t); 99 void aarch64_tlbi_all(void); /* all ASID, all VA */ 100 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 101 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 102 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 103 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 104 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 105 106 107 /* misc */ 108 #define cpu_idnum() aarch64_cpuid() 109 110 /* cache op */ 111 112 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 113 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 114 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 115 #define cpu_idcache_wbinv_all() \ 116 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 117 #define cpu_icache_sync_all() \ 118 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 119 #define cpu_icache_inv_all() aarch64_icache_inv_all() 120 121 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 122 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 123 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 124 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 125 #define cpu_icache_sync_range(v,s) aarch64_icache_sync_range((v),(s)) 126 127 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 128 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 129 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 130 131 /* others */ 132 #define cpu_drain_writebuf() aarch64_drain_writebuf() 133 134 extern u_int arm_dcache_align; 135 extern u_int arm_dcache_align_mask; 136 137 static inline bool 138 cpu_gtmr_exists_p(void) 139 { 140 141 return true; 142 } 143 144 static inline u_int 145 cpu_clusterid(void) 146 { 147 148 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 149 } 150 151 static inline bool 152 cpu_earlydevice_va_p(void) 153 { 154 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 155 156 /* This function may be called before enabling MMU, or mapping KVA */ 157 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 158 return false; 159 160 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 161 if (!pmap_devmap_bootstrap_done) 162 return false; 163 164 return true; 165 } 166 167 #endif /* _KERNEL */ 168 169 #endif /* _AARCH64_CPUFUNC_H_ */ 170
Indexes created Thu Oct 02 01:09:59 GMT 2025