cpufunc.h revision 1.16
1 /* $NetBSD: cpufunc.h,v 1.16 2020/07/01 07:59:16 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 struct aarch64_cache_unit { 38 u_int cache_type; 39 #define CACHE_TYPE_VPIPT 0 /* VMID-aware PIPT */ 40 #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 41 #define CACHE_TYPE_VIPT 2 42 #define CACHE_TYPE_PIPT 3 43 u_int cache_line_size; 44 u_int cache_ways; 45 u_int cache_sets; 46 u_int cache_way_size; 47 u_int cache_size; 48 }; 49 50 struct aarch64_cache_info { 51 u_int cacheable; 52 #define CACHE_CACHEABLE_NONE 0 53 #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 54 #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 55 #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 56 #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 57 struct aarch64_cache_unit icache; 58 struct aarch64_cache_unit dcache; 59 }; 60 61 #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 62 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 63 extern u_int aarch64_cache_prefer_mask; 64 extern u_int cputype; /* compat arm */ 65 66 extern int aarch64_pac_enabled; 67 68 int aarch64_pac_init(int); 69 70 int set_cpufuncs(void); 71 void aarch64_getcacheinfo(int); 72 void aarch64_printcacheinfo(device_t); 73 74 void aarch64_dcache_wbinv_all(void); 75 void aarch64_dcache_inv_all(void); 76 void aarch64_dcache_wb_all(void); 77 void aarch64_icache_inv_all(void); 78 79 /* cache op in cpufunc_asm_armv8.S */ 80 void aarch64_nullop(void); 81 uint32_t aarch64_cpuid(void); 82 void aarch64_icache_sync_range(vaddr_t, vsize_t); 83 void aarch64_icache_inv_range(vaddr_t, vsize_t); 84 void aarch64_icache_barrier_range(vaddr_t, vsize_t); 85 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 86 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 87 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 88 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 89 void aarch64_icache_inv_all(void); 90 void aarch64_drain_writebuf(void); 91 92 /* tlb op in cpufunc_asm_armv8.S */ 93 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 94 void aarch64_set_ttbr0(uint64_t); 95 void aarch64_set_ttbr0_thunderx(uint64_t); 96 void aarch64_tlbi_all(void); /* all ASID, all VA */ 97 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 98 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 99 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 100 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 101 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 102 103 104 /* misc */ 105 #define cpu_idnum() aarch64_cpuid() 106 107 /* cache op */ 108 109 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 110 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 111 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 112 #define cpu_idcache_wbinv_all() \ 113 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 114 #define cpu_icache_sync_all() \ 115 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 116 #define cpu_icache_inv_all() aarch64_icache_inv_all() 117 118 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 119 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 120 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 121 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 122 #define cpu_icache_sync_range(v,s) \ 123 curcpu()->ci_cpufuncs.cf_icache_sync_range((v),(s)) 124 125 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 126 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 127 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 128 129 /* others */ 130 #define cpu_drain_writebuf() aarch64_drain_writebuf() 131 132 extern u_int arm_dcache_align; 133 extern u_int arm_dcache_align_mask; 134 135 static inline bool 136 cpu_gtmr_exists_p(void) 137 { 138 139 return true; 140 } 141 142 static inline u_int 143 cpu_clusterid(void) 144 { 145 146 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 147 } 148 149 static inline bool 150 cpu_earlydevice_va_p(void) 151 { 152 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 153 154 /* This function may be called before enabling MMU, or mapping KVA */ 155 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 156 return false; 157 158 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 159 if (!pmap_devmap_bootstrap_done) 160 return false; 161 162 return true; 163 } 164 165 #endif /* _KERNEL */ 166 167 /* definitions of TAG and PAC in pointers */ 168 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 169 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 170 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 171 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 172 #define AARCH64_ADDRESS_TAGPAC_MASK \ 173 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 174 175 #ifdef _KERNEL 176 /* 177 * Which is the address space of this VA? 178 * return the space considering TBI. (PAC is not yet) 179 * 180 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 181 */ 182 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 183 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 184 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 185 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 186 static inline int 187 aarch64_addressspace(vaddr_t va) 188 { 189 uint64_t addrtop, tbi; 190 191 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 192 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 193 if (reg_tcr_el1_read() & tbi) { 194 if (addrtop == 0) { 195 /* lower address, and TBI0 enabled */ 196 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 197 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 198 return AARCH64_ADDRSPACE_LOWER; 199 } 200 /* upper address, and TBI1 enabled */ 201 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 202 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 203 return AARCH64_ADDRSPACE_UPPER; 204 } 205 206 addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB; 207 if (addrtop == 0) { 208 /* lower address, and TBI0 disabled */ 209 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 210 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 211 return AARCH64_ADDRSPACE_LOWER; 212 } 213 /* upper address, and TBI1 disabled */ 214 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 215 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 216 return AARCH64_ADDRSPACE_UPPER; 217 } 218 219 static inline vaddr_t 220 aarch64_untag_address(vaddr_t va) 221 { 222 uint64_t addrtop, tbi; 223 224 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 225 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 226 if (reg_tcr_el1_read() & tbi) { 227 if (addrtop == 0) { 228 /* lower address, and TBI0 enabled */ 229 return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK; 230 } 231 /* upper address, and TBI1 enabled */ 232 return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK; 233 } 234 235 /* TBI[01] is disabled, nothing to do */ 236 return va; 237 } 238 239 #endif /* _KERNEL */ 240 241 static __inline uint64_t 242 aarch64_strip_pac(uint64_t __val) 243 { 244 if (__val & AARCH64_ADDRTOP_TAG) 245 return __val | AARCH64_ADDRESS_TAGPAC_MASK; 246 return __val & ~AARCH64_ADDRESS_TAGPAC_MASK; 247 } 248 249 #endif /* _AARCH64_CPUFUNC_H_ */ 250
Indexes created Wed Oct 01 19:09:53 GMT 2025