cpufunc.h revision 1.22
1 /* $NetBSD: cpufunc.h,v 1.22 2021/10/31 16:23:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 38 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 39 extern u_int aarch64_cache_prefer_mask; 40 extern u_int cputype; /* compat arm */ 41 42 extern int aarch64_bti_enabled; 43 extern int aarch64_pan_enabled; 44 extern int aarch64_pac_enabled; 45 46 void aarch64_pan_init(int); 47 int aarch64_pac_init(int); 48 49 int set_cpufuncs(void); 50 int aarch64_setcpufuncs(struct cpu_info *); 51 void aarch64_getcacheinfo(struct cpu_info *); 52 void aarch64_parsecacheinfo(struct cpu_info *); 53 void aarch64_printcacheinfo(device_t, struct cpu_info *); 54 55 void aarch64_dcache_wbinv_all(void); 56 void aarch64_dcache_inv_all(void); 57 void aarch64_dcache_wb_all(void); 58 void aarch64_icache_inv_all(void); 59 60 /* cache op in cpufunc_asm_armv8.S */ 61 void aarch64_nullop(void); 62 uint32_t aarch64_cpuid(void); 63 void aarch64_icache_sync_range(vaddr_t, vsize_t); 64 void aarch64_icache_inv_range(vaddr_t, vsize_t); 65 void aarch64_icache_barrier_range(vaddr_t, vsize_t); 66 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 67 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 68 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 69 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 70 void aarch64_icache_inv_all(void); 71 void aarch64_drain_writebuf(void); 72 73 /* tlb op in cpufunc_asm_armv8.S */ 74 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 75 void aarch64_set_ttbr0(uint64_t); 76 void aarch64_set_ttbr0_thunderx(uint64_t); 77 void aarch64_tlbi_all(void); /* all ASID, all VA */ 78 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 79 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 80 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 81 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 82 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 83 84 /* misc */ 85 #define cpu_idnum() aarch64_cpuid() 86 87 /* cache op */ 88 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 89 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 90 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 91 #define cpu_idcache_wbinv_all() \ 92 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 93 #define cpu_icache_sync_all() \ 94 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 95 #define cpu_icache_inv_all() aarch64_icache_inv_all() 96 97 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 98 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 99 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 100 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 101 #define cpu_icache_sync_range(v,s) \ 102 curcpu()->ci_cpufuncs.cf_icache_sync_range((v),(s)) 103 104 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 105 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 106 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 107 108 /* others */ 109 #define cpu_drain_writebuf() aarch64_drain_writebuf() 110 111 extern u_int arm_dcache_align; 112 extern u_int arm_dcache_align_mask; 113 114 static inline bool 115 cpu_gtmr_exists_p(void) 116 { 117 118 return true; 119 } 120 121 static inline u_int 122 cpu_clusterid(void) 123 { 124 125 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 126 } 127 128 static inline bool 129 cpu_earlydevice_va_p(void) 130 { 131 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 132 133 /* This function may be called before enabling MMU, or mapping KVA */ 134 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 135 return false; 136 137 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 138 if (!pmap_devmap_bootstrap_done) 139 return false; 140 141 return true; 142 } 143 144 #endif /* _KERNEL */ 145 146 /* definitions of TAG and PAC in pointers */ 147 #define AARCH64_ADDRTOP_TAG_BIT 55 148 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 149 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 150 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 151 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 152 #define AARCH64_ADDRESS_TAGPAC_MASK \ 153 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 154 155 #ifdef _KERNEL 156 /* 157 * Which is the address space of this VA? 158 * return the space considering TBI. (PAC is not yet) 159 * 160 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 161 */ 162 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 163 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 164 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 165 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 166 static inline int 167 aarch64_addressspace(vaddr_t va) 168 { 169 uint64_t addrtop, tbi; 170 171 addrtop = va & AARCH64_ADDRTOP_TAG; 172 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 173 if (reg_tcr_el1_read() & tbi) { 174 if (addrtop == 0) { 175 /* lower address, and TBI0 enabled */ 176 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 177 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 178 return AARCH64_ADDRSPACE_LOWER; 179 } 180 /* upper address, and TBI1 enabled */ 181 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 182 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 183 return AARCH64_ADDRSPACE_UPPER; 184 } 185 186 addrtop = va & AARCH64_ADDRTOP_MSB; 187 if (addrtop == 0) { 188 /* lower address, and TBI0 disabled */ 189 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 190 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 191 return AARCH64_ADDRSPACE_LOWER; 192 } 193 /* upper address, and TBI1 disabled */ 194 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 195 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 196 return AARCH64_ADDRSPACE_UPPER; 197 } 198 199 static inline vaddr_t 200 aarch64_untag_address(vaddr_t va) 201 { 202 uint64_t addrtop, tbi; 203 204 addrtop = va & AARCH64_ADDRTOP_TAG; 205 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 206 if (reg_tcr_el1_read() & tbi) { 207 if (addrtop == 0) { 208 /* lower address, and TBI0 enabled */ 209 return va & ~AARCH64_ADDRESS_TAG_MASK; 210 } 211 /* upper address, and TBI1 enabled */ 212 return va | AARCH64_ADDRESS_TAG_MASK; 213 } 214 215 /* TBI[01] is disabled, nothing to do */ 216 return va; 217 } 218 219 #endif /* _KERNEL */ 220 221 static __inline uint64_t 222 aarch64_strip_pac(uint64_t __val) 223 { 224 if (__val & AARCH64_ADDRTOP_TAG) 225 return __val | AARCH64_ADDRESS_TAGPAC_MASK; 226 return __val & ~AARCH64_ADDRESS_TAGPAC_MASK; 227 } 228 229 #endif /* _AARCH64_CPUFUNC_H_ */ 230
Indexes created Wed Oct 01 15:09:59 GMT 2025