cpufunc.h revision 1.24
1 /* $NetBSD: cpufunc.h,v 1.24 2022/07/20 01:35:25 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 #include <sys/cpu.h> 38 39 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 40 extern u_int aarch64_cache_prefer_mask; 41 extern u_int cputype; /* compat arm */ 42 43 extern int aarch64_bti_enabled; 44 extern int aarch64_hafdbs_enabled; 45 extern int aarch64_pan_enabled; 46 extern int aarch64_pac_enabled; 47 48 void aarch64_hafdbs_init(int); 49 void aarch64_pan_init(int); 50 int aarch64_pac_init(int); 51 52 int set_cpufuncs(void); 53 int aarch64_setcpufuncs(struct cpu_info *); 54 void aarch64_getcacheinfo(struct cpu_info *); 55 void aarch64_parsecacheinfo(struct cpu_info *); 56 void aarch64_printcacheinfo(device_t, struct cpu_info *); 57 58 void aarch64_dcache_wbinv_all(void); 59 void aarch64_dcache_inv_all(void); 60 void aarch64_dcache_wb_all(void); 61 void aarch64_icache_inv_all(void); 62 63 /* cache op in cpufunc_asm_armv8.S */ 64 void aarch64_nullop(void); 65 uint32_t aarch64_cpuid(void); 66 void aarch64_icache_sync_range(vaddr_t, vsize_t); 67 void aarch64_icache_inv_range(vaddr_t, vsize_t); 68 void aarch64_icache_barrier_range(vaddr_t, vsize_t); 69 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 70 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 71 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 72 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 73 void aarch64_icache_inv_all(void); 74 void aarch64_drain_writebuf(void); 75 76 /* tlb op in cpufunc_asm_armv8.S */ 77 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 78 void aarch64_set_ttbr0(uint64_t); 79 void aarch64_set_ttbr0_thunderx(uint64_t); 80 void aarch64_tlbi_all(void); /* all ASID, all VA */ 81 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 82 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 83 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 84 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 85 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 86 87 /* misc */ 88 #define cpu_idnum() aarch64_cpuid() 89 90 /* cache op */ 91 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 92 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 93 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 94 #define cpu_idcache_wbinv_all() \ 95 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 96 #define cpu_icache_sync_all() \ 97 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 98 #define cpu_icache_inv_all() aarch64_icache_inv_all() 99 100 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 101 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 102 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 103 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 104 #define cpu_icache_sync_range(v,s) \ 105 curcpu()->ci_cpufuncs.cf_icache_sync_range((v),(s)) 106 107 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 108 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 109 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 110 111 /* others */ 112 #define cpu_drain_writebuf() aarch64_drain_writebuf() 113 114 extern u_int arm_dcache_align; 115 extern u_int arm_dcache_align_mask; 116 117 static inline bool 118 cpu_gtmr_exists_p(void) 119 { 120 121 return true; 122 } 123 124 static inline u_int 125 cpu_clusterid(void) 126 { 127 128 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 129 } 130 131 static inline bool 132 cpu_earlydevice_va_p(void) 133 { 134 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 135 136 /* This function may be called before enabling MMU, or mapping KVA */ 137 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 138 return false; 139 140 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 141 if (!pmap_devmap_bootstrap_done) 142 return false; 143 144 return true; 145 } 146 147 #endif /* _KERNEL */ 148 149 /* definitions of TAG and PAC in pointers */ 150 #define AARCH64_ADDRTOP_TAG_BIT 55 151 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 152 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 153 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 154 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 155 #define AARCH64_ADDRESS_TAGPAC_MASK \ 156 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 157 158 #ifdef _KERNEL 159 /* 160 * Which is the address space of this VA? 161 * return the space considering TBI. (PAC is not yet) 162 * 163 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 164 */ 165 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 166 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 167 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 168 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 169 static inline int 170 aarch64_addressspace(vaddr_t va) 171 { 172 uint64_t addrtop, tbi; 173 174 addrtop = va & AARCH64_ADDRTOP_TAG; 175 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 176 if (reg_tcr_el1_read() & tbi) { 177 if (addrtop == 0) { 178 /* lower address, and TBI0 enabled */ 179 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 180 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 181 return AARCH64_ADDRSPACE_LOWER; 182 } 183 /* upper address, and TBI1 enabled */ 184 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 185 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 186 return AARCH64_ADDRSPACE_UPPER; 187 } 188 189 addrtop = va & AARCH64_ADDRTOP_MSB; 190 if (addrtop == 0) { 191 /* lower address, and TBI0 disabled */ 192 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 193 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 194 return AARCH64_ADDRSPACE_LOWER; 195 } 196 /* upper address, and TBI1 disabled */ 197 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 198 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 199 return AARCH64_ADDRSPACE_UPPER; 200 } 201 202 static inline vaddr_t 203 aarch64_untag_address(vaddr_t va) 204 { 205 uint64_t addrtop, tbi; 206 207 addrtop = va & AARCH64_ADDRTOP_TAG; 208 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 209 if (reg_tcr_el1_read() & tbi) { 210 if (addrtop == 0) { 211 /* lower address, and TBI0 enabled */ 212 return va & ~AARCH64_ADDRESS_TAG_MASK; 213 } 214 /* upper address, and TBI1 enabled */ 215 return va | AARCH64_ADDRESS_TAG_MASK; 216 } 217 218 /* TBI[01] is disabled, nothing to do */ 219 return va; 220 } 221 222 #endif /* _KERNEL */ 223 224 static __inline uint64_t 225 aarch64_strip_pac(uint64_t __val) 226 { 227 if (__val & AARCH64_ADDRTOP_TAG) 228 return __val | AARCH64_ADDRESS_TAGPAC_MASK; 229 return __val & ~AARCH64_ADDRESS_TAGPAC_MASK; 230 } 231 232 #endif /* _AARCH64_CPUFUNC_H_ */ 233
Indexes created Wed Oct 01 19:09:53 GMT 2025