cpufunc.h revision 1.7
1 /* $NetBSD: cpufunc.h,v 1.7 2019/09/13 18:07:30 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 struct aarch64_cache_unit { 38 u_int cache_type; 39 #define CACHE_TYPE_UNKNOWN 0 40 #define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */ 41 #define CACHE_TYPE_VIPT 2 42 #define CACHE_TYPE_PIPT 3 43 u_int cache_line_size; 44 u_int cache_ways; 45 u_int cache_sets; 46 u_int cache_way_size; 47 u_int cache_size; 48 u_int cache_purging; 49 #define CACHE_PURGING_WB 0x01 50 #define CACHE_PURGING_WT 0x02 51 #define CACHE_PURGING_RA 0x04 52 #define CACHE_PURGING_WA 0x08 53 }; 54 55 struct aarch64_cache_info { 56 u_int cacheable; 57 #define CACHE_CACHEABLE_NONE 0 58 #define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 59 #define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 60 #define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 61 #define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 62 struct aarch64_cache_unit icache; 63 struct aarch64_cache_unit dcache; 64 }; 65 66 #define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 67 extern struct aarch64_cache_info aarch64_cache_info[MAX_CACHE_LEVEL]; 68 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 69 extern u_int aarch64_cache_prefer_mask; 70 extern u_int cputype; /* compat arm */ 71 72 int set_cpufuncs(void); 73 void aarch64_getcacheinfo(void); 74 void aarch64_printcacheinfo(device_t); 75 76 void aarch64_dcache_wbinv_all(void); 77 void aarch64_dcache_inv_all(void); 78 void aarch64_dcache_wb_all(void); 79 void aarch64_icache_inv_all(void); 80 81 /* cache op in cpufunc_asm_armv8.S */ 82 void aarch64_nullop(void); 83 uint32_t aarch64_cpuid(void); 84 void aarch64_icache_sync_range(vaddr_t, vsize_t); 85 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 86 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 87 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 88 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 89 void aarch64_icache_inv_all(void); 90 void aarch64_drain_writebuf(void); 91 92 /* tlb op in cpufunc_asm_armv8.S */ 93 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 94 void aarch64_set_ttbr0(uint64_t); 95 void aarch64_set_ttbr0_thunderx(uint64_t); 96 void aarch64_tlbi_all(void); /* all ASID, all VA */ 97 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 98 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 99 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 100 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 101 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 102 103 104 /* misc */ 105 #define cpu_idnum() aarch64_cpuid() 106 107 /* cache op */ 108 109 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 110 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 111 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 112 #define cpu_idcache_wbinv_all() \ 113 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 114 #define cpu_icache_sync_all() \ 115 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 116 #define cpu_icache_inv_all() aarch64_icache_inv_all() 117 118 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 119 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 120 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 121 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 122 #define cpu_icache_sync_range(v,s) aarch64_icache_sync_range((v),(s)) 123 124 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 125 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 126 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 127 128 /* others */ 129 #define cpu_drain_writebuf() aarch64_drain_writebuf() 130 131 extern u_int arm_dcache_align; 132 extern u_int arm_dcache_align_mask; 133 134 static inline bool 135 cpu_gtmr_exists_p(void) 136 { 137 138 return true; 139 } 140 141 static inline u_int 142 cpu_clusterid(void) 143 { 144 145 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 146 } 147 148 static inline bool 149 cpu_earlydevice_va_p(void) 150 { 151 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 152 153 /* This function may be called before enabling MMU, or mapping KVA */ 154 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 155 return false; 156 157 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 158 if (!pmap_devmap_bootstrap_done) 159 return false; 160 161 return true; 162 } 163 164 #endif /* _KERNEL */ 165 166 #endif /* _AARCH64_CPUFUNC_H_ */ 167
Indexes created Tue Sep 30 20:09:53 GMT 2025