ascreg.h revision 1.1
1 /* $NetBSD: ascreg.h,v 1.1 2001/10/05 22:27:54 reinoud Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from:ahscreg.h,v 1.2 1994/10/26 02:02:46 38 */ 39 40 #ifndef _ASCREG_H_ 41 #define _ASCREG_H_ 42 43 /* 44 * Hardware layout of the A3000 SDMAC. This also contains the 45 * registers for the sbic chip, but in favor of separating DMA and 46 * scsi, the scsi-driver doesn't make use of this dependency 47 */ 48 49 #define v_char volatile char 50 #define v_int volatile int 51 #define vu_char volatile u_char 52 #define vu_short volatile u_short 53 #define vu_int volatile u_int 54 55 struct sdmac { 56 short pad0; 57 vu_short DAWR; /* DACK Width Register WO */ 58 vu_int WTC; /* Word Transfer Count Register RW */ 59 short pad1; 60 vu_short CNTR; /* Control Register RW */ 61 vu_int ACR; /* Address Count Register RW */ 62 short pad2; 63 vu_short ST_DMA; /* Start DMA Transfers RW-Strobe */ 64 short pad3; 65 vu_short FLUSH; /* Flush FIFO RW-Strobe */ 66 short pad4; 67 vu_short CINT; /* Clear Interrupts RW-Strobe */ 68 short pad5; 69 vu_short ISTR; /* Interrupt Status Register RO */ 70 int pad6[7]; 71 short pad7; 72 vu_short SP_DMA; /* Stop DMA Transfers RW-Strobe */ 73 char pad8; 74 vu_char SASR; /* sbic asr */ 75 char pad9; 76 vu_char SCMD; /* sbic data */ 77 }; 78 79 /* 80 * value to go into DAWR 81 */ 82 #define DAWR_AHSC 3 /* according to A3000T service-manual */ 83 84 /* 85 * bits defined for CNTR 86 */ 87 #define CNTR_TCEN (1<<5) /* Terminal Count Enable */ 88 #define CNTR_PREST (1<<4) /* Perp Reset (not implemented :-((( ) */ 89 #define CNTR_PDMD (1<<3) /* Perp Device Mode Select (1=SCSI,0=XT/AT) */ 90 #define CNTR_INTEN (1<<2) /* Interrupt Enable */ 91 #define CNTR_DDIR (1<<1) /* Device Direction. 1==rd host, wr perp */ 92 #define CNTR_IO_DX (1<<0) /* IORDY & CSX1 Polarity Select */ 93 94 /* 95 * bits defined for ISTR 96 */ 97 #define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */ 98 #define ISTR_INT_F (1<<7) /* Interrupt Follow */ 99 #define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */ 100 #define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */ 101 #define ISTR_INT_P (1<<4) /* Interrupt Pending */ 102 #define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */ 103 #define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */ 104 #define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */ 105 #define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */ 106 107 #define DMAGO_READ 0x01 108 109 110 /* Addresses relative to podule base */ 111 112 #define ASC_INTSTATUS 0x2000 113 #define ASC_CLRINT 0x2000 114 #define ASC_PAGEREG 0x3000 115 116 /* Addresses relative to module base */ 117 118 #define ASC_DMAC 0x3000 119 #define ASC_SBIC 0x2000 120 #define ASC_SRAM 0x0000 121 122 #define ASC_SBIC_SPACE 8 123 124 #define ASC_SRAM_BLKSIZE 0x1000 125 126 #define IS_IRQREQ 0x01 127 #define IS_DMAC_IRQ 0x02 128 #define IS_SBIC_IRQ 0x08 129 130 #if 0 131 /* SBIC Commands */ 132 133 #define SBIC_CMD_Reset 0x00 /* Reset the SBIC */ 134 #define SBIC_Abort 0x01 /* Abort command */ 135 #define SBIC_Sel_tx_wATN 0x08 /* Select and Transfer with ATN */ 136 #define SBIC_Sel_tx_woATN 0x09 /* Select and Transfer without ATN */ 137 138 /* SBIC status codes */ 139 140 #define SBIC_ResetOk 0x00 141 #define SBIC_ResetAFOk 0x01 142 143 /* SBIC registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 */ 144 145 #define SBIC_OWNID 0x00 /* RW FS1 FS0 0 EHP EAF ID2 ID1 ID0 */ 146 #define SBIC_CONTROL 0x01 /* RW DM2 DM1 DM0 HHP EDI IDI HA HSP */ 147 #define SBIC_TIMEREG 0x02 /* RW timeout period value = Tper*Ficlk/80d */ 148 #define SBIC_CDB1TSECT 0x03 /* RW CDB byte 1 & Total sectors per track */ 149 #define SBIC_CDB2THEAD 0x04 /* RW CDB byte 2 & Total number of heads */ 150 #define SBIC_CDB3TCYL1 0x05 /* RW CDB byte 3 & Total no. of cylinders MSB */ 151 #define SBIC_CDB4TCYL2 0x06 /* RW CDB byte 4 & Total no. of cylinders LSB */ 152 #define SBIC_CDB5LADR1 0x07 /* RW CDB byte 5 & Logical addr to translate */ 153 #define SBIC_CBD6LADR2 0x08 /* RW CDB byte 6 & Logical addr to translate */ 154 #define SBIC_CDB7LADR3 0x09 /* RW CDB byte 7 & Logical addr to translate */ 155 #define SBIC_CDB8LADR4 0x0A /* RW CDB byte 8 & Logical addr to translate */ 156 #define SBIC_CDB9SECT 0x0B /* RW CDB byte 9 & Translation sector result */ 157 #define SBIC_CDB10HEAD 0x0C /* RW CDB byte 10 & Translation head result */ 158 #define SBIC_CDB11CYL1 0x0D /* RW CDB byte 11 & Translation cyl result MSB*/ 159 #define SBIC_CDB12CYL2 0x0E /* RW CDB byte 12 & Translation cyl result LSB*/ 160 #define SBIC_TARGETLUN 0x0F /* RW TLV DOK 0 0 0 TL2 TL1 TL0 */ 161 #define SBIC_COMPHASE 0x10 /* RW Command Phase Register for multi-phase */ 162 #define SBIC_SYNCTX 0x11 /* RW 0 TP2 TP1 TP0 OF3 OF2 OF1 OF0 */ 163 #define SBIC_TXCOUNT1 0x12 /* RW Transfer count MSB */ 164 #define SBIC_TXCOUNT2 0x13 /* RW Transfer count */ 165 #define SBIC_TXCOUNT3 0x14 /* RW Transfer count LSB */ 166 #define SBIC_DESTID 0x15 /* RW SCC DPD 0 0 0 DI2 DI1 DI0 */ 167 #define SBIC_SOURCEID 0x16 /* RW ER ES DSP 0 SIV SI2 SI1 SI0 */ 168 #define SBIC_SCSISTAT 0x17 /* RO **Interrupt type*** **Int. qualifier** */ 169 #define SBIC_COMMAND 0x18 /* RW SBT *********Command code************* */ 170 #define SBIC_DATA 0x19 /* RW Access to data i/o FIFO for polled use */ 171 172 #define SBIC_ADDRREG 0x00 173 #define SBIC_DATAREG 0x04 174 #define SBIC_AUX_STATUS 0x00 175 176 /* 177 * My ID register, and/or CDB Size 178 */ 179 180 #define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */ 181 /* 11 Mhz is invalid */ 182 #define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */ 183 #define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */ 184 #define SBIC_ID_EHP 0x10 /* Enable host parity */ 185 #define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ 186 #define SBIC_ID_MASK 0x07 187 #define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ 188 189 /* 190 * Control register 191 */ 192 193 #define SBIC_CTL_DMA 0x80 /* Single byte dma */ 194 #define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/ 195 #define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ 196 #define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ 197 #define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ 198 #define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ 199 #define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ 200 #define SBIC_CTL_HA 0x02 /* Halt on ATN */ 201 #define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */ 202 203 /* 204 * Destination ID register 205 */ 206 207 #define SBIC_DID_DPD 0x40 /* Data Phase Direction */ 208 209 /* 210 * Auxiliary Status Register 211 */ 212 213 #define SBIC_ASR_INT 0x80 /* Interrupt pending */ 214 #define SBIC_ASR_LCI 0x40 /* Last command ignored */ 215 #define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ 216 #define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ 217 #define SBIC_ASR_xxx 0x0c 218 #define SBIC_ASR_PE 0x02 /* Parity error (even) */ 219 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ 220 221 /* DMAC constants */ 222 223 #define DMAC_Bits 0x01 224 #define DMAC_Ctrl1 0x60 225 #define DMAC_Ctrl2 0x01 226 #define DMAC_CLEAR_MASK 0x0E 227 #define DMAC_SET_MASK 0x0F 228 #define DMAC_DMA_RD_MODE 0x04 229 #define DMAC_DMA_WR_MODE 0x08 230 231 /* DMAC registers */ 232 233 #define DMAC_INITIALISE 0x0000 /* WO ---- ---- ---- ---- ---- ---- 16B RES */ 234 #define DMAC_CHANNEL 0x0200 /* R ---- ---- ---- BASE SEL3 SEL2 SEL1 SEL0 */ 235 /* W ---- ---- ---- ---- ---- BASE *SELECT** */ 236 #define DMAC_TXCNTLO 0x0004 /* RW C7 C6 C5 C4 C3 C2 C1 C0 */ 237 #define DMAC_TXCNTHI 0x0204 /* RW C15 C14 C13 C12 C11 C10 C9 C8 */ 238 #define DMAC_TXADRLO 0x0008 /* RW A7 A6 A5 A4 A3 A2 A1 A0 */ 239 #define DMAC_TXADRMD 0x0208 /* RW A15 A14 A13 A12 A11 A10 A9 A8 */ 240 #define DMAC_TXADRHI 0x000C /* RW A23 A22 A21 A20 A19 A18 A17 A16 */ 241 #define DMAC_DEVCON1 0x0010 /* RW AKL RQL EXW ROT CMP DDMA AHLD MTM */ 242 #define DMAC_DEVCON2 0x0210 /* RW ---- ---- ---- ---- ---- ---- WEV BHLD */ 243 #define DMAC_MODECON 0x0014 /* RW **TMODE** ADIR AUTI **TDIR*** ---- WORD */ 244 #define DMAC_STATUS 0x0214 /* RO RQ3 RQ2 RQ1 RQ0 TC3 TC2 TC1 TC0 */ 245 #if 0 246 templo = dmac + 0x0018;/* RO T7 T6 T5 T4 T3 T2 T1 T0 */ 247 temphi = dmac + 0x0218;/* RO T15 T14 T13 T12 T11 T10 T9 T8 */ 248 #endif 249 #define DMAC_REQREG 0x001C /* RW ---- ---- ---- ---- SRQ3 SRQ2 SRQ1 SRQ0 */ 250 #define DMAC_MASKREG 0x021C /* RW ---- ---- ---- ---- M3 M2 M1 M0 */ 251 252 #ifndef _LOCORE 253 #define WriteSBIC(a, d) \ 254 WriteByte(sbic_base + SBIC_ADDRREG, a); \ 255 WriteByte(sbic_base + SBIC_DATAREG, d); 256 257 /* 258 #define ReadSBIC(a) \ 259 (WriteByte(sbic_base, a), ReadWord(sbic_base + 4) & 0xff) 260 */ 261 #define ReadSBIC(a) \ 262 ReadSBIC1(sbic_base, a) 263 264 265 static __inline int 266 ReadSBIC1(sbic_base, a) 267 u_int sbic_base; 268 int a; 269 { 270 WriteByte(sbic_base + SBIC_ADDRREG, a); 271 return(ReadByte(sbic_base + SBIC_DATAREG)); 272 } 273 274 275 #define WriteDMAC(a, d) WriteByte(dmac_base + a, d) 276 #define ReadDMAC(a) ReadByte(dmac_base + a) 277 #endif 278 279 280 #endif 281 #endif /* _ASCREG_H_ */ 282
Indexes created Tue Sep 30 20:09:53 GMT 2025