sbic.c revision 1.1
1 /* $NetBSD: sbic.c,v 1.1 2001/10/05 22:27:58 reinoud Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Richard Earnshaw 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * 29 * Copyright (c) 1994 Christian E. Hopps 30 * Copyright (c) 1990 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to Berkeley by 34 * Van Jacobson of Lawrence Berkeley Laboratory. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the University of 47 * California, Berkeley and its contributors. 48 * 4. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * from: sbic.c,v 1.21 1996/01/07 22:01:54 65 */ 66 67 /* 68 * WD 33C93 scsi adaptor driver 69 */ 70 71 #if 0 72 /* 73 * The UPROTECTED_CSR code is bogus. It can read the csr (SCSI Status 74 * register) at times when an interrupt may be pending. Doing this will 75 * clear the interrupt, so we won't see it at times when we really need 76 * to. 77 */ 78 #define UNPROTECTED_CSR 79 #endif 80 81 #define DEBUG 82 /* #define SBIC_DEBUG(a) a */ 83 84 #include "opt_ddb.h" 85 86 #include <sys/types.h> 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/kernel.h> /* For hz */ 91 #include <sys/device.h> 92 #include <sys/buf.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/scsipi/scsi_all.h> 100 #include <dev/scsipi/scsipi_all.h> 101 #include <dev/scsipi/scsiconf.h> 102 103 #include <acorn32/podulebus/sbicreg.h> 104 #include <acorn32/podulebus/sbicvar.h> 105 106 /* 107 * SCSI delays 108 * In u-seconds, primarily for state changes on the SPC. 109 */ 110 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 111 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 112 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 113 114 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 115 116 static int sbicicmd (struct sbic_softc *, int, int, 117 struct sbic_acb *); 118 static int sbicgo (struct sbic_softc *, struct scsipi_xfer *); 119 static int sbicwait (sbic_regmap_p, char, int , int); 120 static int sbicselectbus (struct sbic_softc *, sbic_regmap_p, u_char, 121 u_char, u_char); 122 static int sbicxfstart (sbic_regmap_p, int, u_char, int); 123 static int sbicxfout (sbic_regmap_p regs, int, void *, int); 124 static int sbicfromscsiperiod (struct sbic_softc *, sbic_regmap_p, int); 125 static int sbictoscsiperiod (struct sbic_softc *, sbic_regmap_p, int); 126 static int sbicpoll (struct sbic_softc *); 127 static int sbicnextstate (struct sbic_softc *, u_char, u_char); 128 static int sbicmsgin (struct sbic_softc *); 129 static int sbicxfin (sbic_regmap_p regs, int, void *); 130 static int sbicabort (struct sbic_softc *, sbic_regmap_p, char *); 131 static void sbicxfdone (struct sbic_softc *, sbic_regmap_p, int); 132 static void sbicerror (struct sbic_softc *, sbic_regmap_p, u_char); 133 static void sbicreset (struct sbic_softc *); 134 static void sbic_scsidone (struct sbic_acb *, int); 135 static void sbic_sched (struct sbic_softc *); 136 static void sbic_save_ptrs (struct sbic_softc *, sbic_regmap_p); 137 138 /* 139 * Synch xfer parameters, and timing conversions 140 */ 141 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 142 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 143 144 int sbic_cmd_wait = SBIC_CMD_WAIT; 145 int sbic_data_wait = SBIC_DATA_WAIT; 146 int sbic_init_wait = SBIC_INIT_WAIT; 147 148 /* 149 * was broken before.. now if you want this you get it for all drives 150 * on sbic controllers. 151 */ 152 u_char sbic_inhibit_sync[8]; 153 int sbic_enable_reselect = 1; 154 int sbic_clock_override = 0; 155 int sbic_no_dma = 1; /* was 0 */ 156 int sbic_parallel_operations = 1; 157 158 #ifdef DEBUG 159 sbic_regmap_p debug_sbic_regs; 160 int sbicdma_ops = 0; /* total DMA operations */ 161 int sbicdma_saves = 0; 162 #define QPRINTF(a) if (sbic_debug > 1) printf a 163 #define DBGPRINTF(x,p) if (p) printf x 164 #define DBG(x) x 165 int sbic_debug = 0; 166 int sync_debug = 0; 167 int sbic_dma_debug = 0; 168 int reselect_debug = 0; 169 int data_pointer_debug = 0; 170 u_char debug_asr, debug_csr, routine; 171 172 void sbictimeout (struct sbic_softc *); 173 void sbic_dump (struct sbic_softc *); 174 void sbic_dump_acb (struct sbic_acb *); 175 176 #define CSR_TRACE_SIZE 32 177 #if CSR_TRACE_SIZE 178 #define CSR_TRACE(w,c,a,x) do { \ 179 int s = splbio(); \ 180 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 181 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 182 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 183 splx(s); \ 184 } while (0) 185 int csr_traceptr; 186 int csr_tracesize = CSR_TRACE_SIZE; 187 struct { 188 u_char whr; 189 u_char csr; 190 u_char asr; 191 u_char xtn; 192 } csr_trace[CSR_TRACE_SIZE]; 193 #else 194 #define CSR_TRACE 195 #endif 196 197 #define SBIC_TRACE_SIZE 0 198 #if SBIC_TRACE_SIZE 199 #define SBIC_TRACE(dev) do { \ 200 int s = splbio(); \ 201 sbic_trace[sbic_traceptr].sp = &s; \ 202 sbic_trace[sbic_traceptr].line = __LINE__; \ 203 sbic_trace[sbic_traceptr].sr = s; \ 204 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 205 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 206 splx(s); \ 207 } while (0) 208 int sbic_traceptr; 209 int sbic_tracesize = SBIC_TRACE_SIZE; 210 struct { 211 void *sp; 212 u_short line; 213 u_short sr; 214 int csr; 215 } sbic_trace[SBIC_TRACE_SIZE]; 216 #else 217 #define SBIC_TRACE(dev) 218 #endif 219 220 #else 221 #define QPRINTF(a) 222 #define DBGPRINTF(x,p) 223 #define DBG(x) 224 #define CSR_TRACE 225 #define SBIC_TRACE 226 #endif 227 228 #ifndef SBIC_DEBUG 229 #define SBIC_DEBUG(x) 230 #endif 231 232 /* 233 * default minphys routine for sbic based controllers 234 */ 235 void 236 sbic_minphys(struct buf *bp) 237 { 238 /* 239 * No max transfer at this level. 240 */ 241 minphys(bp); 242 } 243 244 /* 245 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 246 */ 247 static void 248 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_p regs) 249 { 250 int count, asr, s; 251 struct sbic_acb* acb; 252 253 SBIC_TRACE(dev); 254 if (!(dev->sc_flags & SBICF_INDMA)) 255 return; /* DMA not active */ 256 257 s = splbio(); 258 259 acb = dev->sc_nexus; 260 if (acb == NULL) { 261 splx(s); 262 return; 263 } 264 count = -1; 265 do { 266 GET_SBIC_asr(regs, asr); 267 if (asr & SBIC_ASR_DBR) { 268 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 269 splx(s); 270 SBIC_TRACE(dev); 271 return; 272 } 273 } while (asr & (SBIC_ASR_BSY | SBIC_ASR_CIP)); 274 275 /* Save important state */ 276 /* must be done before dmastop */ 277 SBIC_TC_GET(regs, count); 278 279 /* Shut down DMA ====CAREFUL==== */ 280 dev->sc_dmastop(dev->sc_dmah, dev->sc_dmat, acb); 281 dev->sc_flags &= ~SBICF_INDMA; 282 #ifdef DIAGNOSTIC 283 { 284 int count2; 285 286 SBIC_TC_GET(regs, count2); 287 if (count2 != count) 288 panic("sbic_save_ptrs: DMA was still active(%d,%d)", 289 count, count2); 290 } 291 #endif 292 /* Note where we got to before stopping. We need this to resume 293 later. */ 294 acb->offset += acb->sc_tcnt - count; 295 SBIC_TC_PUT(regs, 0); 296 297 DBGPRINTF(("SBIC saving tgt %d data pointers: Offset now %d ASR:%02x", 298 dev->target, acb->offset, asr), data_pointer_debug >= 1); 299 300 acb->sc_tcnt = 0; 301 302 DBG(sbicdma_saves++); 303 splx(s); 304 SBIC_TRACE(dev); 305 } 306 307 /* 308 * used by specific sbic controller 309 * 310 * it appears that the higher level code does nothing with LUN's 311 * so I will too. I could plug it in, however so could they 312 * in scsi_scsi_cmd(). 313 */ 314 void 315 sbic_scsi_request(struct scsipi_channel *chan, 316 scsipi_adapter_req_t req, void *arg) 317 { 318 struct scsipi_xfer *xs; 319 struct sbic_acb *acb; 320 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 321 struct scsipi_periph *periph; 322 int flags, s, stat; 323 324 switch (req) { 325 case ADAPTER_REQ_RUN_XFER: 326 xs = arg; 327 periph = xs->xs_periph; 328 SBIC_TRACE(dev); 329 flags = xs->xs_control; 330 331 if (flags & XS_CTL_DATA_UIO) 332 panic("sbic: scsi data uio requested"); 333 334 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 335 panic("sbic_scsicmd: busy"); 336 337 s = splbio(); 338 acb = dev->free_list.tqh_first; 339 if (acb) 340 TAILQ_REMOVE(&dev->free_list, acb, chain); 341 splx(s); 342 343 if (acb == NULL) { 344 DBG(printf("sbic_scsicmd: unable to queue request for " 345 "target %d\n", periph->periph_target)); 346 #if defined(DDB) && defined(DEBUG) 347 Debugger(); 348 #endif 349 xs->error = XS_RESOURCE_SHORTAGE; 350 SBIC_TRACE(dev); 351 scsipi_done(xs); 352 return; 353 } 354 355 acb->flags = ACB_ACTIVE; 356 if (flags & XS_CTL_DATA_IN) 357 acb->flags |= ACB_DATAIN; 358 acb->xs = xs; 359 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 360 acb->clen = xs->cmdlen; 361 acb->data = xs->data; 362 acb->datalen = xs->datalen; 363 364 QPRINTF(("sbic_scsi_request: Cmd %02x (len %d), Data %p(%d)\n", 365 (unsigned) acb->cmd.opcode, acb->clen, xs->data, 366 xs->datalen)); 367 if (flags & XS_CTL_POLL) { 368 s = splbio(); 369 /* 370 * This has major side effects -- it locks up the 371 * machine. 372 */ 373 374 dev->sc_flags |= SBICF_ICMD; 375 do { 376 while (dev->sc_nexus) 377 sbicpoll(dev); 378 dev->sc_nexus = acb; 379 dev->sc_stat[0] = -1; 380 dev->target = periph->periph_target; 381 dev->lun = periph->periph_lun; 382 stat = sbicicmd(dev, periph->periph_target, 383 periph->periph_lun, acb); 384 } while (dev->sc_nexus != acb); 385 386 sbic_scsidone(acb, stat); 387 splx(s); 388 SBIC_TRACE(dev); 389 return; 390 } 391 392 s = splbio(); 393 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 394 395 if (dev->sc_nexus) { 396 splx(s); 397 SBIC_TRACE(dev); 398 return; 399 } 400 401 /* 402 * Nothing is active, try to start it now. 403 */ 404 sbic_sched(dev); 405 splx(s); 406 407 SBIC_TRACE(dev); 408 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 409 return; 410 411 case ADAPTER_REQ_GROW_RESOURCES: 412 case ADAPTER_REQ_SET_XFER_MODE: 413 /* XXX Not supported. */ 414 return; 415 } 416 } 417 418 /* 419 * attempt to start the next available command 420 */ 421 static void 422 sbic_sched(struct sbic_softc *dev) 423 { 424 struct scsipi_xfer *xs; 425 struct scsipi_periph *periph; 426 struct sbic_acb *acb; 427 int flags, /*phase,*/ stat, i; 428 429 SBIC_TRACE(dev); 430 if (dev->sc_nexus) 431 return; /* a command is current active */ 432 433 SBIC_TRACE(dev); 434 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 435 periph = acb->xs->xs_periph; 436 i = periph->periph_target; 437 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 438 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 439 440 TAILQ_REMOVE(&dev->ready_list, acb, chain); 441 dev->sc_nexus = acb; 442 periph = acb->xs->xs_periph; 443 ti = &dev->sc_tinfo[periph->periph_target]; 444 ti->lubusy |= (1 << periph->periph_lun); 445 break; 446 } 447 } 448 449 SBIC_TRACE(dev); 450 if (acb == NULL) 451 return; /* did not find an available command */ 452 453 xs = acb->xs; 454 periph = xs->xs_periph; 455 flags = xs->xs_control; 456 457 if (flags & XS_CTL_RESET) 458 sbicreset(dev); 459 460 DBGPRINTF(("sbic_sched(%d,%d)\n", periph->periph_target, 461 periph->periph_lun), data_pointer_debug > 1); 462 DBG(if (data_pointer_debug > 1) sbic_dump_acb(acb)); 463 dev->sc_stat[0] = -1; 464 dev->target = periph->periph_target; 465 dev->lun = periph->periph_lun; 466 467 /* Decide if we can use DMA for this transfer. */ 468 if ((flags & XS_CTL_POLL) == 0 469 && !sbic_no_dma 470 && dev->sc_dmaok(dev->sc_dmah, dev->sc_dmat, acb)) 471 acb->flags |= ACB_DMA; 472 473 if ((flags & XS_CTL_POLL) || 474 (!sbic_parallel_operations && (acb->flags & ACB_DMA) == 0)) 475 stat = sbicicmd(dev, periph->periph_target, 476 periph->periph_lun, acb); 477 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 478 SBIC_TRACE(dev); 479 return; 480 } else 481 stat = dev->sc_stat[0]; 482 483 sbic_scsidone(acb, stat); 484 SBIC_TRACE(dev); 485 } 486 487 static void 488 sbic_scsidone(struct sbic_acb *acb, int stat) 489 { 490 struct scsipi_xfer *xs; 491 struct scsipi_periph *periph; 492 struct sbic_softc *dev; 493 /* int s;*/ 494 int dosched = 0; 495 496 xs = acb->xs; 497 periph = xs->xs_periph; 498 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 499 SBIC_TRACE(dev); 500 #ifdef DIAGNOSTIC 501 if (acb == NULL || xs == NULL) { 502 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", 503 dev->target, dev->lun); 504 #ifdef DDB 505 Debugger(); 506 #endif 507 return; 508 } 509 #endif 510 511 DBGPRINTF(("scsidone: (%d,%d)->(%d,%d)%02x acbfl=%x\n", 512 periph->periph_target, periph->periph_lun, 513 dev->target, dev->lun, stat, acb->flags), 514 data_pointer_debug > 1); 515 DBG(if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) 516 panic("target == hostid")); 517 518 xs->status = stat; 519 xs->resid = 0; 520 if (xs->error == XS_NOERROR) { 521 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 522 xs->error = XS_BUSY; 523 } 524 525 /* 526 * Remove the ACB from whatever queue it's on. We have to do a bit of 527 * a hack to figure out which queue it's on. Note that it is *not* 528 * necessary to cdr down the ready queue, but we must cdr down the 529 * nexus queue and see if it's there, so we can mark the unit as no 530 * longer busy. This code is sickening, but it works. 531 */ 532 if (acb == dev->sc_nexus) { 533 dev->sc_nexus = NULL; 534 dev->sc_tinfo[periph->periph_target].lubusy &= 535 ~(1 << periph->periph_lun); 536 if (dev->ready_list.tqh_first) 537 dosched = 1; /* start next command */ 538 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 539 TAILQ_REMOVE(&dev->ready_list, acb, chain); 540 } else { 541 register struct sbic_acb *acb2; 542 for (acb2 = dev->nexus_list.tqh_first; acb2; 543 acb2 = acb2->chain.tqe_next) { 544 if (acb2 == acb) { 545 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 546 dev->sc_tinfo[periph->periph_target].lubusy 547 &= ~(1 << periph->periph_lun); 548 break; 549 } 550 } 551 if (acb2) 552 ; 553 else if (acb->chain.tqe_next) { 554 TAILQ_REMOVE(&dev->ready_list, acb, chain); 555 } else { 556 printf("%s: can't find matching acb\n", 557 dev->sc_dev.dv_xname); 558 #ifdef DDB 559 Debugger(); 560 #endif 561 } 562 } 563 /* Put it on the free list. */ 564 acb->flags = ACB_FREE; 565 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 566 567 dev->sc_tinfo[periph->periph_target].cmds++; 568 569 scsipi_done(xs); 570 571 if (dosched) 572 sbic_sched(dev); 573 SBIC_TRACE(dev); 574 } 575 576 static int 577 sbicwait(sbic_regmap_p regs, char until, int timeo, int line) 578 { 579 u_char val; 580 int csr; 581 582 SBIC_TRACE((struct sbic_softc *)0); 583 if (timeo == 0) 584 timeo = 1000000; /* some large value.. */ 585 586 GET_SBIC_asr(regs,val); 587 while ((val & until) == 0) { 588 if (timeo-- == 0) { 589 GET_SBIC_csr(regs, csr); 590 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 591 line, val, csr); 592 #if defined(DDB) && defined(DEBUG) 593 Debugger(); 594 #endif 595 return val; /* Maybe I should abort */ 596 break; 597 } 598 DELAY(1); 599 GET_SBIC_asr(regs,val); 600 } 601 SBIC_TRACE((struct sbic_softc *)0); 602 return val; 603 } 604 605 static int 606 sbicabort(struct sbic_softc *dev, sbic_regmap_p regs, char *where) 607 { 608 u_char csr, asr; 609 610 GET_SBIC_asr(regs, asr); 611 GET_SBIC_csr(regs, csr); 612 613 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 614 dev->sc_dev.dv_xname, where, csr, asr); 615 616 617 #if 0 618 /* Clean up running command */ 619 if (dev->sc_nexus != NULL) { 620 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 621 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 622 } 623 while (acb = dev->nexus_list.tqh_first) { 624 acb->xs->error = XS_DRIVER_STUFFUP; 625 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 626 } 627 #endif 628 629 /* Clean up chip itself */ 630 if (dev->sc_flags & SBICF_SELECTED) { 631 while (asr & SBIC_ASR_DBR) { 632 /* sbic is jammed w/data. need to clear it */ 633 /* But we don't know what direction it needs to go */ 634 GET_SBIC_data(regs, asr); 635 printf("%s: abort %s: clearing data buffer 0x%02x\n", 636 dev->sc_dev.dv_xname, where, asr); 637 GET_SBIC_asr(regs, asr); 638 /* Not the read direction, then */ 639 if (asr & SBIC_ASR_DBR) 640 SET_SBIC_data(regs, asr); 641 GET_SBIC_asr(regs, asr); 642 } 643 WAIT_CIP(regs); 644 printf("%s: sbicabort - sending ABORT command\n", 645 dev->sc_dev.dv_xname); 646 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 647 WAIT_CIP(regs); 648 649 GET_SBIC_asr(regs, asr); 650 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI)) { 651 /* ok, get more drastic.. */ 652 653 printf("%s: sbicabort - asr %x, trying to reset\n", 654 dev->sc_dev.dv_xname, asr); 655 sbicreset(dev); 656 dev->sc_flags &= ~SBICF_SELECTED; 657 return -1; 658 } 659 printf("%s: sbicabort - sending DISC command\n", 660 dev->sc_dev.dv_xname); 661 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 662 663 do { 664 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 665 GET_SBIC_csr (regs, csr); 666 CSR_TRACE('a',csr,asr,0); 667 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 668 && (csr != SBIC_CSR_CMD_INVALID)); 669 670 /* lets just hope it worked.. */ 671 dev->sc_flags &= ~SBICF_SELECTED; 672 } 673 return -1; 674 } 675 676 677 /* 678 * Initialize driver-private structures 679 */ 680 681 int 682 sbicinit(struct sbic_softc *dev) 683 { 684 sbic_regmap_p regs; 685 u_int i; 686 /* u_int my_id, s;*/ 687 /* u_char csr;*/ 688 struct sbic_acb *acb; 689 u_int inhibit_sync; 690 691 extern u_long scsi_nosync; 692 extern int shift_nosync; 693 694 SBIC_DEBUG(printf("sbicinit:\n")); 695 696 regs = &dev->sc_sbicp; 697 698 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 699 TAILQ_INIT(&dev->ready_list); 700 TAILQ_INIT(&dev->nexus_list); 701 TAILQ_INIT(&dev->free_list); 702 callout_init(&dev->sc_timo_ch); 703 dev->sc_nexus = NULL; 704 acb = dev->sc_acb; 705 memset(acb, 0, sizeof(dev->sc_acb)); 706 707 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 708 709 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 710 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 711 acb++; 712 } 713 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 714 /* make sure timeout is really not needed */ 715 DBG(callout_reset(&dev->sc_timo_ch, 30 * hz, 716 (void *)sbictimeout, dev)); 717 } else 718 panic("sbic: reinitializing driver!"); 719 720 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 721 722 dev->sc_flags |= SBICF_ALIVE; 723 dev->sc_flags &= ~SBICF_SELECTED; 724 725 /* initialize inhibit array */ 726 if (scsi_nosync) { 727 728 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 729 730 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 731 shift_nosync += 8; 732 733 DBGPRINTF(("%s: Inhibiting synchronous transfer %02x\n", 734 dev->sc_dev.dv_xname, inhibit_sync), inhibit_sync); 735 736 for (i = 0; i < 8; ++i) 737 if (inhibit_sync & (1 << i)) 738 sbic_inhibit_sync[i] = 1; 739 } 740 741 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 742 743 sbicreset(dev); 744 return 0; 745 } 746 747 static void 748 sbicreset(struct sbic_softc *dev) 749 { 750 sbic_regmap_p regs; 751 u_int my_id, s; 752 /* u_int i;*/ 753 u_char csr; 754 /* struct sbic_acb *acb;*/ 755 756 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 757 758 regs = &dev->sc_sbicp; 759 760 SBIC_DEBUG(printf("sbicreset: regs = %08x\n", regs)); 761 762 #if 0 763 if (dev->sc_flags & SBICF_ALIVE) { 764 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 765 WAIT_CIP(regs); 766 } 767 #else 768 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 769 770 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 771 772 WAIT_CIP(regs); 773 774 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 775 #endif 776 s = splbio(); 777 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 778 779 /* Enable advanced mode */ 780 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 781 SET_SBIC_myid(regs, my_id); 782 783 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 784 785 /* 786 * Disable interrupts (in dmainit) then reset the chip 787 */ 788 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 789 DELAY(25); 790 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 791 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 792 793 if (dev->sc_clkfreq < 110) 794 my_id |= SBIC_ID_FS_8_10; 795 else if (dev->sc_clkfreq < 160) 796 my_id |= SBIC_ID_FS_12_15; 797 else if (dev->sc_clkfreq < 210) 798 my_id |= SBIC_ID_FS_16_20; 799 800 SET_SBIC_myid(regs, my_id); 801 802 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 803 804 /* 805 * Set up various chip parameters 806 */ 807 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 808 | dev->sc_dmamode); 809 /* 810 * don't allow (re)selection (SBIC_RID_ES) 811 * until we can handle target mode!! 812 */ 813 SET_SBIC_rselid(regs, SBIC_RID_ER); 814 SET_SBIC_syn(regs, 0); /* asynch for now */ 815 816 /* 817 * anything else was zeroed by reset 818 */ 819 splx(s); 820 821 #if 0 822 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 823 TAILQ_INIT(&dev->ready_list); 824 TAILQ_INIT(&dev->nexus_list); 825 TAILQ_INIT(&dev->free_list); 826 dev->sc_nexus = NULL; 827 acb = dev->sc_acb; 828 memset(acb, 0, sizeof(dev->sc_acb)); 829 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 830 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 831 acb++; 832 } 833 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 834 } else { 835 if (dev->sc_nexus != NULL) { 836 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 837 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 838 } 839 while (acb = dev->nexus_list.tqh_first) { 840 acb->xs->error = XS_DRIVER_STUFFUP; 841 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 842 } 843 } 844 845 dev->sc_flags |= SBICF_ALIVE; 846 #endif 847 dev->sc_flags &= ~SBICF_SELECTED; 848 } 849 850 static void 851 sbicerror(struct sbic_softc *dev, sbic_regmap_p regs, u_char csr) 852 { 853 #ifdef DIAGNOSTIC 854 if (dev->sc_nexus == NULL) 855 panic("sbicerror"); 856 #endif 857 if (dev->sc_nexus->xs->xs_control & XS_CTL_SILENT) 858 return; 859 860 printf("%s: ", dev->sc_dev.dv_xname); 861 printf("csr == 0x%02x\n", csr); /* XXX */ 862 } 863 864 /* 865 * select the bus, return when selected or error. 866 */ 867 static int 868 sbicselectbus(struct sbic_softc *dev, sbic_regmap_p regs, u_char target, 869 u_char lun, u_char our_addr) 870 { 871 u_char asr, csr, id; 872 873 SBIC_TRACE(dev); 874 QPRINTF(("sbicselectbus %d\n", target)); 875 876 /* 877 * if we're already selected, return (XXXX panic maybe?) 878 */ 879 if (dev->sc_flags & SBICF_SELECTED) { 880 SBIC_TRACE(dev); 881 return 1; 882 } 883 884 /* 885 * issue select 886 */ 887 SBIC_TC_PUT(regs, 0); 888 SET_SBIC_selid(regs, target); 889 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 890 891 /* 892 * set sync or async 893 */ 894 if (dev->sc_sync[target].state == SYNC_DONE) 895 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 896 dev->sc_sync[target].period)); 897 else 898 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 899 900 GET_SBIC_asr(regs, asr); 901 if (asr & (SBIC_ASR_INT | SBIC_ASR_BSY)) { 902 /* This means we got ourselves reselected upon */ 903 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 904 #ifdef DDB 905 /* Debugger();*/ 906 #endif 907 SBIC_TRACE(dev); 908 return 1; 909 } 910 911 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 912 913 /* 914 * wait for select (merged from separate function may need 915 * cleanup) 916 */ 917 WAIT_CIP(regs); 918 do { 919 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 920 if (asr & SBIC_ASR_LCI) { 921 922 DBGPRINTF(("sbicselectbus: late LCI asr %02x\n", asr), 923 reselect_debug); 924 925 SBIC_TRACE(dev); 926 return 1; 927 } 928 GET_SBIC_csr (regs, csr); 929 CSR_TRACE('s',csr,asr,target); 930 QPRINTF(("%02x ", csr)); 931 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 932 933 DBGPRINTF(("sbicselectbus: reselected asr %02x\n", 934 asr), reselect_debug); 935 936 /* We need to handle this now so we don't lock 937 up later */ 938 sbicnextstate(dev, csr, asr); 939 SBIC_TRACE(dev); 940 return 1; 941 } 942 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 943 panic("sbicselectbus: target issued select!"); 944 return 1; 945 } 946 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 947 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 948 csr != SBIC_CSR_SEL_TIMEO); 949 950 /* Enable (or not) reselection */ 951 if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 952 SET_SBIC_rselid (regs, 0); 953 else 954 SET_SBIC_rselid (regs, SBIC_RID_ER); 955 956 if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) { 957 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 958 GET_SBIC_selid(regs, id); 959 dev->target = id; 960 GET_SBIC_tlun(regs,dev->lun); 961 if (dev->lun & SBIC_TLUN_VALID) 962 dev->lun &= SBIC_TLUN_MASK; 963 else 964 dev->lun = lun; 965 } else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 966 /* 967 * Send identify message 968 * (SCSI-2 requires an identify msg (?)) 969 */ 970 GET_SBIC_selid(regs, id); 971 dev->target = id; 972 GET_SBIC_tlun(regs,dev->lun); 973 if (dev->lun & SBIC_TLUN_VALID) 974 dev->lun &= SBIC_TLUN_MASK; 975 else 976 dev->lun = lun; 977 /* 978 * handle drives that don't want to be asked 979 * whether to go sync at all. 980 */ 981 if (sbic_inhibit_sync[id] 982 && dev->sc_sync[id].state == SYNC_START) { 983 DBGPRINTF(("Forcing target %d asynchronous.\n", id), 984 sync_debug); 985 986 dev->sc_sync[id].offset = 0; 987 dev->sc_sync[id].period = sbic_min_period; 988 dev->sc_sync[id].state = SYNC_DONE; 989 } 990 991 992 if (dev->sc_sync[id].state != SYNC_START){ 993 if ((dev->sc_nexus->xs->xs_control & XS_CTL_POLL) 994 || (dev->sc_flags & SBICF_ICMD) 995 || !sbic_enable_reselect) 996 SEND_BYTE(regs, MSG_IDENTIFY | lun); 997 else 998 SEND_BYTE(regs, MSG_IDENTIFY_DR | lun); 999 } else { 1000 /* 1001 * try to initiate a sync transfer. 1002 * So compose the sync message we're going 1003 * to send to the target 1004 */ 1005 1006 DBGPRINTF(("Sending sync request to target %d ... ", 1007 id), sync_debug); 1008 1009 /* 1010 * setup scsi message sync message request 1011 */ 1012 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1013 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1014 dev->sc_msg[2] = 3; 1015 dev->sc_msg[3] = MSG_SYNC_REQ; 1016 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1017 sbic_min_period); 1018 dev->sc_msg[5] = sbic_max_offset; 1019 1020 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, 1021 sbic_cmd_wait)) 1022 sbicxfout(regs, 6, dev->sc_msg, 1023 MESG_OUT_PHASE); 1024 1025 dev->sc_sync[id].state = SYNC_SENT; 1026 1027 DBGPRINTF(("sent\n"), sync_debug); 1028 } 1029 1030 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1031 GET_SBIC_csr (regs, csr); 1032 CSR_TRACE('y',csr,asr,target); 1033 QPRINTF(("[%02x]", csr)); 1034 1035 DBGPRINTF(("csr-result of last msgout: 0x%x\n", csr), 1036 sync_debug && dev->sc_sync[id].state == SYNC_SENT); 1037 1038 if (csr != SBIC_CSR_SEL_TIMEO) 1039 dev->sc_flags |= SBICF_SELECTED; 1040 } 1041 if (csr == SBIC_CSR_SEL_TIMEO) 1042 dev->sc_nexus->xs->error = XS_SELTIMEOUT; 1043 1044 QPRINTF(("\n")); 1045 1046 SBIC_TRACE(dev); 1047 return csr == SBIC_CSR_SEL_TIMEO; 1048 } 1049 1050 static int 1051 sbicxfstart(sbic_regmap_p regs, int len, u_char phase, int wait) 1052 { 1053 u_char id; 1054 1055 switch (phase) { 1056 case DATA_IN_PHASE: 1057 case MESG_IN_PHASE: 1058 GET_SBIC_selid (regs, id); 1059 id |= SBIC_SID_FROM_SCSI; 1060 SET_SBIC_selid (regs, id); 1061 SBIC_TC_PUT (regs, (unsigned)len); 1062 break; 1063 case DATA_OUT_PHASE: 1064 case MESG_OUT_PHASE: 1065 case CMD_PHASE: 1066 GET_SBIC_selid (regs, id); 1067 id &= ~SBIC_SID_FROM_SCSI; 1068 SET_SBIC_selid (regs, id); 1069 SBIC_TC_PUT (regs, (unsigned)len); 1070 break; 1071 default: 1072 SBIC_TC_PUT (regs, 0); 1073 } 1074 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1075 1076 return 1; 1077 } 1078 1079 static int 1080 sbicxfout(sbic_regmap_p regs, int len, void *bp, int phase) 1081 { 1082 #ifdef UNPROTECTED_CSR 1083 u_char orig_csr 1084 #endif 1085 u_char asr, *buf; 1086 /* u_char csr;*/ 1087 int wait; 1088 1089 buf = bp; 1090 wait = sbic_data_wait; 1091 1092 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1093 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1094 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1095 1096 #ifdef UNPROTECTED_CSR 1097 GET_SBIC_csr (regs, orig_csr); 1098 CSR_TRACE('>',orig_csr,0,0); 1099 #endif 1100 1101 /* 1102 * sigh.. WD-PROTO strikes again.. sending the command in one go 1103 * causes the chip to lock up if talking to certain (misbehaving?) 1104 * targets. Anyway, this procedure should work for all targets, but 1105 * it's slightly slower due to the overhead 1106 */ 1107 WAIT_CIP (regs); 1108 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1109 for (;len > 0; len--) { 1110 GET_SBIC_asr (regs, asr); 1111 while ((asr & SBIC_ASR_DBR) == 0) { 1112 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1113 1114 DBGPRINTF(("sbicxfout fail: l%d i%x w%d\n", 1115 len, asr, wait), sbic_debug); 1116 1117 return len; 1118 } 1119 /* DELAY(1);*/ 1120 GET_SBIC_asr (regs, asr); 1121 } 1122 1123 SET_SBIC_data (regs, *buf); 1124 buf++; 1125 } 1126 SBIC_TC_GET(regs, len); 1127 QPRINTF(("sbicxfout done %d bytes\n", len)); 1128 /* 1129 * this leaves with one csr to be read 1130 */ 1131 return 0; 1132 } 1133 1134 /* returns # bytes left to read */ 1135 static int 1136 sbicxfin(sbic_regmap_p regs, int len, void *bp) 1137 { 1138 int wait; 1139 /* int read;*/ 1140 u_char *obp, *buf; 1141 #ifdef UNPROTECTED_CSR 1142 u_char orig_csr, csr; 1143 #endif 1144 u_char asr; 1145 1146 wait = sbic_data_wait; 1147 obp = bp; 1148 buf = bp; 1149 1150 #ifdef UNPROTECTED_CSR 1151 GET_SBIC_csr (regs, orig_csr); 1152 CSR_TRACE('<',orig_csr,0,0); 1153 1154 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1155 #endif 1156 1157 WAIT_CIP (regs); 1158 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1159 for (;len > 0; len--) { 1160 GET_SBIC_asr (regs, asr); 1161 if ((asr & SBIC_ASR_PE)) { 1162 DBG(printf("sbicxfin parity error: l%d i%x w%d\n", 1163 len, asr, wait)); 1164 #if defined(DDB) && defined(DEBUG) 1165 Debugger(); 1166 #endif 1167 DBG(return ((unsigned long)buf - (unsigned long)bp)); 1168 } 1169 while ((asr & SBIC_ASR_DBR) == 0) { 1170 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1171 1172 DBG(if (sbic_debug) { 1173 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1174 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1175 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1176 printf("sbicxfin fail: l%d i%x w%d\n", len, asr, wait); }); 1177 1178 return len; 1179 } 1180 1181 #ifdef UNPROTECTED_CSR 1182 if (!(asr & SBIC_ASR_BSY)) { 1183 GET_SBIC_csr(regs, csr); 1184 CSR_TRACE('<',csr,asr,len); 1185 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1186 } 1187 #endif 1188 1189 /* DELAY(1);*/ 1190 GET_SBIC_asr (regs, asr); 1191 } 1192 1193 GET_SBIC_data (regs, *buf); 1194 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1195 buf++; 1196 } 1197 1198 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1199 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1200 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1201 1202 /* this leaves with one csr to be read */ 1203 return len; 1204 } 1205 1206 /* 1207 * SCSI 'immediate' command: issue a command to some SCSI device 1208 * and get back an 'immediate' response (i.e., do programmed xfer 1209 * to get the response data). 'cbuf' is a buffer containing a scsi 1210 * command of length clen bytes. 'buf' is a buffer of length 'len' 1211 * bytes for data. The transfer direction is determined by the device 1212 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1213 * command must supply no data. 1214 */ 1215 static int 1216 sbicicmd(struct sbic_softc *dev, int target, int lun, struct sbic_acb *acb) 1217 { 1218 sbic_regmap_p regs; 1219 u_char phase, csr, asr; 1220 int wait; 1221 /* int newtarget, cmd_sent, parity_err;*/ 1222 1223 /* int discon;*/ 1224 int i; 1225 1226 void *cbuf, *buf; 1227 int clen, len; 1228 1229 #define CSR_LOG_BUF_SIZE 0 1230 #if CSR_LOG_BUF_SIZE 1231 int bufptr; 1232 int csrbuf[CSR_LOG_BUF_SIZE]; 1233 bufptr = 0; 1234 #endif 1235 1236 cbuf = &acb->cmd; 1237 clen = acb->clen; 1238 buf = acb->data; 1239 len = acb->datalen; 1240 1241 SBIC_TRACE(dev); 1242 regs = &dev->sc_sbicp; 1243 1244 acb->sc_tcnt = 0; 1245 1246 DBG(routine = 3); 1247 DBG(debug_sbic_regs = regs); /* store this to allow debug calls */ 1248 DBGPRINTF(("sbicicmd(%d,%d):%d\n", target, lun, len), 1249 data_pointer_debug > 1); 1250 1251 /* 1252 * set the sbic into non-DMA mode 1253 */ 1254 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1255 1256 dev->sc_stat[0] = 0xff; 1257 dev->sc_msg[0] = 0xff; 1258 i = 1; /* pre-load */ 1259 1260 /* We're stealing the SCSI bus */ 1261 dev->sc_flags |= SBICF_ICMD; 1262 1263 do { 1264 /* 1265 * select the SCSI bus (it's an error if bus isn't free) 1266 */ 1267 if (!(dev->sc_flags & SBICF_SELECTED) 1268 && sbicselectbus(dev, regs, target, lun, 1269 dev->sc_scsiaddr)) { 1270 /*printf("sbicicmd trying to select busy bus!\n");*/ 1271 dev->sc_flags &= ~SBICF_ICMD; 1272 return -1; 1273 } 1274 1275 /* 1276 * Wait for a phase change (or error) then let the 1277 * device sequence us through the various SCSI phases. 1278 */ 1279 1280 wait = sbic_cmd_wait; 1281 1282 asr = GET_SBIC_asr (regs, asr); 1283 GET_SBIC_csr (regs, csr); 1284 CSR_TRACE('I',csr,asr,target); 1285 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1286 1287 #if CSR_LOG_BUF_SIZE 1288 csrbuf[bufptr++] = csr; 1289 #endif 1290 1291 1292 switch (csr) { 1293 case SBIC_CSR_S_XFERRED: 1294 case SBIC_CSR_DISC: 1295 case SBIC_CSR_DISC_1: 1296 dev->sc_flags &= ~SBICF_SELECTED; 1297 GET_SBIC_cmd_phase (regs, phase); 1298 if (phase == 0x60) { 1299 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1300 i = 0; /* done */ 1301 /* break;*/ /* Bypass all the state gobldygook */ 1302 } else { 1303 DBGPRINTF(("sbicicmd: handling disconnect\n"), 1304 reselect_debug > 1); 1305 1306 i = SBIC_STATE_DISCONNECT; 1307 } 1308 break; 1309 1310 case SBIC_CSR_XFERRED | CMD_PHASE: 1311 case SBIC_CSR_MIS | CMD_PHASE: 1312 case SBIC_CSR_MIS_1 | CMD_PHASE: 1313 case SBIC_CSR_MIS_2 | CMD_PHASE: 1314 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1315 if (sbicxfout(regs, clen, 1316 cbuf, CMD_PHASE)) 1317 i = sbicabort(dev, regs, 1318 "icmd sending cmd"); 1319 #if 0 1320 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1321 WAIT_CIP(regs); 1322 GET_SBIC_asr(regs, asr); 1323 CSR_TRACE('I',csr,asr,target); 1324 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI | SBIC_ASR_CIP)) 1325 printf("next: cmd sent asr %02x, csr %02x\n", 1326 asr, csr); 1327 #endif 1328 break; 1329 1330 #if 0 1331 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1332 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1333 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1334 case SBIC_CSR_MIS | DATA_IN_PHASE: 1335 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1336 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1337 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1338 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1339 if (acb->datalen <= 0) 1340 i = sbicabort(dev, regs, "icmd out of data"); 1341 else { 1342 wait = sbic_data_wait; 1343 if (sbicxfstart(regs, acb->datalen, 1344 SBIC_PHASE(csr), wait)) 1345 if (csr & 0x01) 1346 /* data in? */ 1347 i = sbicxfin(regs, acb->datalen, acb->data); 1348 else 1349 i = sbicxfout(regs, acb->datalen, acb->data, 1350 SBIC_PHASE(csr)); 1351 acb->data += acb->datalen - i; 1352 acb->datalen = i; 1353 i = 1; 1354 } 1355 break; 1356 1357 #endif 1358 case SBIC_CSR_XFERRED | STATUS_PHASE: 1359 case SBIC_CSR_MIS | STATUS_PHASE: 1360 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1361 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1362 /* 1363 * the sbic does the status/cmd-complete reading ok, 1364 * so do this with its hi-level commands. 1365 */ 1366 DBGPRINTF(("SBICICMD status phase\n"), sbic_debug); 1367 1368 SBIC_TC_PUT(regs, 0); 1369 SET_SBIC_cmd_phase(regs, 0x46); 1370 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1371 break; 1372 1373 #if THIS_IS_A_RESERVED_STATE 1374 case BUS_FREE_PHASE: /* This is not legal */ 1375 if (dev->sc_stat[0] != 0xff) 1376 goto out; 1377 break; 1378 #endif 1379 1380 default: 1381 i = sbicnextstate(dev, csr, asr); 1382 } 1383 1384 /* 1385 * make sure the last command was taken, 1386 * ie. we're not hunting after an ignored command.. 1387 */ 1388 GET_SBIC_asr(regs, asr); 1389 1390 /* tapes may take a loooong time.. */ 1391 while (asr & SBIC_ASR_BSY){ 1392 if (asr & SBIC_ASR_DBR) { 1393 printf("sbicicmd: Waiting while sbic is " 1394 "jammed, CSR:%02x,ASR:%02x\n", 1395 csr, asr); 1396 #ifdef DDB 1397 Debugger(); 1398 #endif 1399 /* SBIC is jammed */ 1400 /* DUNNO which direction */ 1401 /* Try old direction */ 1402 GET_SBIC_data(regs,i); 1403 GET_SBIC_asr(regs, asr); 1404 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1405 SET_SBIC_data(regs,i); 1406 } 1407 GET_SBIC_asr(regs, asr); 1408 } 1409 1410 /* 1411 * wait for last command to complete 1412 */ 1413 if (asr & SBIC_ASR_LCI) { 1414 printf("sbicicmd: last command ignored\n"); 1415 } 1416 else if (i == 1) /* Bsy */ 1417 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 1418 1419 /* 1420 * do it again 1421 */ 1422 } while (i > 0 && dev->sc_stat[0] == 0xff); 1423 1424 /* Sometimes we need to do an extra read of the CSR */ 1425 GET_SBIC_csr(regs, csr); 1426 CSR_TRACE('I',csr,asr,0xff); 1427 1428 #if CSR_LOG_BUF_SIZE 1429 if (reselect_debug > 1) 1430 for (i = 0; i < bufptr; i++) 1431 printf("CSR:%02x", csrbuf[i]); 1432 #endif 1433 1434 DBGPRINTF(("sbicicmd done(%d,%d):%d =%d=\n", 1435 dev->target, lun, 1436 acb->datalen, 1437 dev->sc_stat[0]), 1438 data_pointer_debug > 1); 1439 1440 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1441 dev->sc_flags &= ~SBICF_ICMD; 1442 1443 SBIC_TRACE(dev); 1444 return dev->sc_stat[0]; 1445 } 1446 1447 /* 1448 * Finish SCSI xfer command: After the completion interrupt from 1449 * a read/write operation, sequence through the final phases in 1450 * programmed i/o. This routine is a lot like sbicicmd except we 1451 * skip (and don't allow) the select, cmd out and data in/out phases. 1452 */ 1453 static void 1454 sbicxfdone(struct sbic_softc *dev, sbic_regmap_p regs, int target) 1455 { 1456 u_char phase, asr, csr; 1457 int s; 1458 1459 SBIC_TRACE(dev); 1460 QPRINTF(("{")); 1461 s = splbio(); 1462 1463 /* 1464 * have the sbic complete on its own 1465 */ 1466 SBIC_TC_PUT(regs, 0); 1467 SET_SBIC_cmd_phase(regs, 0x46); 1468 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1469 1470 do { 1471 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1472 GET_SBIC_csr (regs, csr); 1473 CSR_TRACE('f',csr,asr,target); 1474 QPRINTF(("%02x:", csr)); 1475 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1476 && (csr != SBIC_CSR_S_XFERRED)); 1477 1478 dev->sc_flags &= ~SBICF_SELECTED; 1479 1480 GET_SBIC_cmd_phase (regs, phase); 1481 QPRINTF(("}%02x", phase)); 1482 if (phase == 0x60) 1483 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1484 else 1485 sbicerror(dev, regs, csr); 1486 1487 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1488 splx(s); 1489 SBIC_TRACE(dev); 1490 } 1491 1492 /* 1493 * No DMA chains 1494 */ 1495 1496 static int 1497 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1498 { 1499 int i, usedma; 1500 /* int dmaflags, count; */ 1501 /* int wait;*/ 1502 /* u_char cmd;*/ 1503 u_char asr = 0, csr = 0; 1504 /* u_char *addr; */ 1505 sbic_regmap_p regs; 1506 struct sbic_acb *acb; 1507 1508 SBIC_TRACE(dev); 1509 dev->target = xs->xs_periph->periph_target; 1510 dev->lun = xs->xs_periph->periph_lun; 1511 acb = dev->sc_nexus; 1512 regs = &dev->sc_sbicp; 1513 1514 usedma = acb->flags & ACB_DMA; 1515 1516 DBG(routine = 1); 1517 DBG(debug_sbic_regs = regs); /* store this to allow debug calls */ 1518 DBGPRINTF(("sbicgo(%d,%d)\n", dev->target, dev->lun), 1519 data_pointer_debug > 1); 1520 1521 /* 1522 * set the sbic into DMA mode 1523 */ 1524 if (usedma) 1525 SET_SBIC_control(regs, 1526 SBIC_CTL_EDI | SBIC_CTL_IDI | dev->sc_dmamode); 1527 else 1528 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1529 1530 1531 /* 1532 * select the SCSI bus (it's an error if bus isn't free) 1533 */ 1534 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1535 dev->sc_scsiaddr)) { 1536 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1537 SBIC_TRACE(dev); 1538 /* Not done: may need to be rescheduled */ 1539 return 0; 1540 } 1541 dev->sc_stat[0] = 0xff; 1542 1543 /* 1544 * Allocate the DMA chain 1545 */ 1546 1547 /* Mark end of segment */ 1548 acb->sc_tcnt = 0; 1549 1550 SBIC_TRACE(dev); 1551 /* Enable interrupts */ 1552 dev->sc_enintr(dev); 1553 if (usedma) { 1554 int tcnt; 1555 1556 acb->offset = 0; 1557 acb->sc_tcnt = 0; 1558 /* Note, this does not start DMA */ 1559 tcnt = dev->sc_dmasetup(dev->sc_dmah, dev->sc_dmat, acb, 1560 (acb->flags & ACB_DATAIN) != 0); 1561 1562 DBG(dev->sc_dmatimo = tcnt ? 1 : 0); 1563 DBG(++sbicdma_ops); /* count total DMA operations */ 1564 } 1565 1566 SBIC_TRACE(dev); 1567 1568 /* 1569 * enintr() also enables interrupts for the sbic 1570 */ 1571 DBG(debug_asr = asr); 1572 DBG(debug_csr = csr); 1573 1574 /* 1575 * Lets cycle a while then let the interrupt handler take over 1576 */ 1577 1578 asr = GET_SBIC_asr(regs, asr); 1579 do { 1580 GET_SBIC_csr(regs, csr); 1581 CSR_TRACE('g', csr, asr, dev->target); 1582 1583 DBG(debug_csr = csr); 1584 DBG(routine = 1); 1585 1586 QPRINTF(("go[0x%x]", csr)); 1587 1588 i = sbicnextstate(dev, csr, asr); 1589 1590 WAIT_CIP(regs); 1591 GET_SBIC_asr(regs, asr); 1592 1593 DBG(debug_asr = asr); 1594 1595 if (asr & SBIC_ASR_LCI) 1596 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1597 } while (i == SBIC_STATE_RUNNING && 1598 (asr & (SBIC_ASR_INT | SBIC_ASR_LCI))); 1599 1600 CSR_TRACE('g',csr,asr,i<<4); 1601 SBIC_TRACE(dev); 1602 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) 1603 printf("sbicgo: done & stat = 0xff\n"); 1604 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1605 /* if (i == SBIC_STATE_DONE && dev->sc_stat[0]) { */ 1606 /* Did we really finish that fast? */ 1607 return 1; 1608 } 1609 return 0; 1610 } 1611 1612 1613 int 1614 sbicintr(struct sbic_softc *dev) 1615 { 1616 sbic_regmap_p regs; 1617 u_char asr, csr; 1618 /* u_char *tmpaddr;*/ 1619 /* struct sbic_acb *acb;*/ 1620 int i; 1621 /* int newtarget, newlun;*/ 1622 /* unsigned tcnt;*/ 1623 1624 regs = &dev->sc_sbicp; 1625 1626 /* 1627 * pending interrupt? 1628 */ 1629 GET_SBIC_asr (regs, asr); 1630 if ((asr & SBIC_ASR_INT) == 0) 1631 return 0; 1632 1633 SBIC_TRACE(dev); 1634 do { 1635 GET_SBIC_csr(regs, csr); 1636 CSR_TRACE('i',csr,asr,dev->target); 1637 1638 DBG(debug_csr = csr); 1639 DBG(routine = 2); 1640 1641 QPRINTF(("intr[0x%x]", csr)); 1642 1643 i = sbicnextstate(dev, csr, asr); 1644 1645 WAIT_CIP(regs); 1646 GET_SBIC_asr(regs, asr); 1647 1648 DBG(debug_asr = asr); 1649 1650 #if 0 1651 if (asr & SBIC_ASR_LCI) 1652 printf("sbicintr: LCI asr:%02x csr:%02x\n", asr, csr); 1653 #endif 1654 } while (i == SBIC_STATE_RUNNING && 1655 (asr & (SBIC_ASR_INT | SBIC_ASR_LCI))); 1656 CSR_TRACE('i', csr, asr, i << 4); 1657 SBIC_TRACE(dev); 1658 return 1; 1659 } 1660 1661 /* 1662 * Run commands and wait for disconnect 1663 */ 1664 static int 1665 sbicpoll(struct sbic_softc *dev) 1666 { 1667 sbic_regmap_p regs; 1668 u_char asr, csr; 1669 /* struct sbic_pending* pendp;*/ 1670 int i; 1671 /* unsigned tcnt;*/ 1672 1673 SBIC_TRACE(dev); 1674 regs = &dev->sc_sbicp; 1675 1676 do { 1677 GET_SBIC_asr (regs, asr); 1678 1679 DBG(debug_asr = asr); 1680 1681 GET_SBIC_csr(regs, csr); 1682 CSR_TRACE('p', csr, asr, dev->target); 1683 1684 DBG(debug_csr = csr); 1685 DBG(routine = 2); 1686 1687 QPRINTF(("poll[0x%x]", csr)); 1688 1689 i = sbicnextstate(dev, csr, asr); 1690 1691 WAIT_CIP(regs); 1692 GET_SBIC_asr(regs, asr); 1693 /* tapes may take a loooong time.. */ 1694 while (asr & SBIC_ASR_BSY){ 1695 if (asr & SBIC_ASR_DBR) { 1696 printf("sbipoll: Waiting while sbic is " 1697 "jammed, CSR:%02x,ASR:%02x\n", 1698 csr, asr); 1699 #ifdef DDB 1700 Debugger(); 1701 #endif 1702 /* SBIC is jammed */ 1703 /* DUNNO which direction */ 1704 /* Try old direction */ 1705 GET_SBIC_data(regs,i); 1706 GET_SBIC_asr(regs, asr); 1707 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1708 SET_SBIC_data(regs,i); 1709 } 1710 GET_SBIC_asr(regs, asr); 1711 } 1712 1713 if (asr & SBIC_ASR_LCI) 1714 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr, csr); 1715 else if (i == 1) /* BSY */ 1716 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1717 } while (i == SBIC_STATE_RUNNING); 1718 CSR_TRACE('p', csr, asr, i << 4); 1719 SBIC_TRACE(dev); 1720 return 1; 1721 } 1722 1723 /* 1724 * Handle a single msgin 1725 */ 1726 1727 static int 1728 sbicmsgin(struct sbic_softc *dev) 1729 { 1730 sbic_regmap_p regs; 1731 int recvlen; 1732 u_char asr, csr, *tmpaddr; 1733 1734 regs = &dev->sc_sbicp; 1735 1736 dev->sc_msg[0] = 0xff; 1737 dev->sc_msg[1] = 0xff; 1738 1739 GET_SBIC_asr(regs, asr); 1740 1741 DBGPRINTF(("sbicmsgin asr=%02x\n", asr), reselect_debug > 1); 1742 1743 sbic_save_ptrs(dev, regs); 1744 1745 GET_SBIC_selid (regs, csr); 1746 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1747 1748 SBIC_TC_PUT(regs, 0); 1749 tmpaddr = dev->sc_msg; 1750 recvlen = 1; 1751 do { 1752 while (recvlen--) { 1753 asr = GET_SBIC_asr(regs, asr); 1754 GET_SBIC_csr(regs, csr); 1755 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1756 csr, asr)); 1757 1758 RECV_BYTE(regs, *tmpaddr); 1759 CSR_TRACE('m', csr, asr, *tmpaddr); 1760 #if 1 1761 /* 1762 * get the command completion interrupt, or we 1763 * can't send a new command (LCI) 1764 */ 1765 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1766 GET_SBIC_csr(regs, csr); 1767 CSR_TRACE('X', csr, asr, dev->target); 1768 #else 1769 WAIT_CIP(regs); 1770 do { 1771 GET_SBIC_asr(regs, asr); 1772 csr = 0xff; 1773 GET_SBIC_csr(regs, csr); 1774 CSR_TRACE('X', csr, asr, dev->target); 1775 if (csr == 0xff) 1776 printf("sbicmsgin waiting: csr %02x " 1777 "asr %02x\n", csr, asr); 1778 } while (csr == 0xff); 1779 #endif 1780 1781 DBGPRINTF(("sbicmsgin: got %02x csr %02x asr %02x\n", 1782 *tmpaddr, csr, asr), reselect_debug > 1); 1783 1784 #if do_parity_check 1785 if (asr & SBIC_ASR_PE) { 1786 printf("Parity error"); 1787 /* This code simply does not work. */ 1788 WAIT_CIP(regs); 1789 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1790 WAIT_CIP(regs); 1791 GET_SBIC_asr(regs, asr); 1792 WAIT_CIP(regs); 1793 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1794 WAIT_CIP(regs); 1795 if (!(asr & SBIC_ASR_LCI)) 1796 /* Target wants to send garbled msg*/ 1797 continue; 1798 printf("--fixing\n"); 1799 /* loop until a msgout phase occurs on 1800 target */ 1801 while ((csr & 0x07) != MESG_OUT_PHASE) { 1802 while ((asr & SBIC_ASR_BSY) && 1803 !(asr & 1804 (SBIC_ASR_DBR | SBIC_ASR_INT))) 1805 GET_SBIC_asr(regs, asr); 1806 if (asr & SBIC_ASR_DBR) 1807 panic("msgin: jammed again!\n"); 1808 GET_SBIC_csr(regs, csr); 1809 CSR_TRACE('e', csr, asr, dev->target); 1810 if ((csr & 0x07) != MESG_OUT_PHASE) { 1811 sbicnextstate(dev, csr, asr); 1812 sbic_save_ptrs(dev, regs); 1813 } 1814 } 1815 /* Should be msg out by now */ 1816 SEND_BYTE(regs, MSG_PARITY_ERROR); 1817 } 1818 else 1819 #endif 1820 tmpaddr++; 1821 1822 if (recvlen) { 1823 /* Clear ACK */ 1824 WAIT_CIP(regs); 1825 GET_SBIC_asr(regs, asr); 1826 GET_SBIC_csr(regs, csr); 1827 CSR_TRACE('X',csr,asr,dev->target); 1828 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 1829 csr, asr)); 1830 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1831 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1832 } 1833 1834 }; 1835 1836 if (dev->sc_msg[0] == 0xff) { 1837 printf("sbicmsgin: sbic swallowed our message\n"); 1838 break; 1839 } 1840 1841 DBGPRINTF(("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1842 csr, asr, dev->sc_msg[0]), sync_debug); 1843 1844 /* 1845 * test whether this is a reply to our sync 1846 * request 1847 */ 1848 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 1849 QPRINTF(("IFFY")); 1850 /* Got IFFY msg -- ack it */ 1851 } else if (dev->sc_msg[0] == MSG_REJECT 1852 && dev->sc_sync[dev->target].state == SYNC_SENT) { 1853 QPRINTF(("REJECT of SYN")); 1854 1855 DBGPRINTF(("target %d rejected sync, going async\n", 1856 dev->target), sync_debug); 1857 1858 dev->sc_sync[dev->target].period = sbic_min_period; 1859 dev->sc_sync[dev->target].offset = 0; 1860 dev->sc_sync[dev->target].state = SYNC_DONE; 1861 SET_SBIC_syn(regs, 1862 SBIC_SYN(dev->sc_sync[dev->target].offset, 1863 dev->sc_sync[dev->target].period)); 1864 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 1865 QPRINTF(("REJECT")); 1866 /* 1867 * we'll never REJECt a REJECT message.. 1868 */ 1869 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 1870 QPRINTF(("MSG_SAVE_DATA_PTR")); 1871 /* 1872 * don't reject this either. 1873 */ 1874 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 1875 QPRINTF(("DISCONNECT")); 1876 1877 DBGPRINTF(("sbicmsgin: got disconnect msg %s\n", 1878 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""), 1879 reselect_debug > 1 && 1880 dev->sc_msg[0] == MSG_DISCONNECT); 1881 1882 if (dev->sc_flags & SBICF_ICMD) { 1883 /* We're in immediate mode. Prevent 1884 disconnects. */ 1885 /* prepare to reject the message, NACK */ 1886 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1887 WAIT_CIP(regs); 1888 } 1889 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE) { 1890 QPRINTF(("CMD_COMPLETE")); 1891 /* !! KLUDGE ALERT !! quite a few drives don't seem to 1892 * really like the current way of sending the 1893 * sync-handshake together with the ident-message, and 1894 * they react by sending command-complete and 1895 * disconnecting right after returning the valid sync 1896 * handshake. So, all I can do is reselect the drive, 1897 * and hope it won't disconnect again. I don't think 1898 * this is valid behavior, but I can't help fixing a 1899 * problem that apparently exists. 1900 * 1901 * Note: we should not get here on `normal' command 1902 * completion, as that condition is handled by the 1903 * high-level sel&xfer resume command used to walk 1904 * thru status/cc-phase. 1905 */ 1906 1907 DBGPRINTF(("GOT MSG %d! target %d acting weird.." 1908 " waiting for disconnect...\n", 1909 dev->sc_msg[0], dev->target), sync_debug); 1910 1911 /* Check to see if sbic is handling this */ 1912 GET_SBIC_asr(regs, asr); 1913 if (asr & SBIC_ASR_BSY) 1914 return SBIC_STATE_RUNNING; 1915 1916 /* Let's try this: Assume it works and set 1917 status to 00 */ 1918 dev->sc_stat[0] = 0; 1919 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 1920 && tmpaddr == &dev->sc_msg[1]) { 1921 QPRINTF(("ExtMSG\n")); 1922 /* Read in whole extended message */ 1923 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1924 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1925 GET_SBIC_asr(regs, asr); 1926 GET_SBIC_csr(regs, csr); 1927 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 1928 RECV_BYTE(regs, *tmpaddr); 1929 CSR_TRACE('x',csr,asr,*tmpaddr); 1930 /* Wait for command completion IRQ */ 1931 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1932 recvlen = *tmpaddr++; 1933 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 1934 asr, csr, recvlen)); 1935 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && 1936 dev->sc_msg[1] == 3 && 1937 dev->sc_msg[2] == MSG_SYNC_REQ) { 1938 QPRINTF(("SYN")); 1939 dev->sc_sync[dev->target].period = 1940 sbicfromscsiperiod(dev, 1941 regs, dev->sc_msg[3]); 1942 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 1943 dev->sc_sync[dev->target].state = SYNC_DONE; 1944 SET_SBIC_syn(regs, 1945 SBIC_SYN(dev->sc_sync[dev->target].offset, 1946 dev->sc_sync[dev->target].period)); 1947 printf("%s: target %d now synchronous," 1948 " period=%dns, offset=%d.\n", 1949 dev->sc_dev.dv_xname, dev->target, 1950 dev->sc_msg[3] * 4, dev->sc_msg[4]); 1951 } else { 1952 1953 DBGPRINTF(("sbicmsgin: Rejecting message 0x%02x\n", 1954 dev->sc_msg[0]), sbic_debug || sync_debug); 1955 1956 /* prepare to reject the message, NACK */ 1957 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1958 WAIT_CIP(regs); 1959 } 1960 /* Clear ACK */ 1961 WAIT_CIP(regs); 1962 GET_SBIC_asr(regs, asr); 1963 GET_SBIC_csr(regs, csr); 1964 CSR_TRACE('X',csr,asr,dev->target); 1965 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 1966 csr, asr, recvlen)); 1967 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1968 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1969 } 1970 #if 0 1971 while ((csr == SBIC_CSR_MSGIN_W_ACK) || 1972 (SBIC_PHASE(csr) == MESG_IN_PHASE)); 1973 #else 1974 while (recvlen > 0); 1975 #endif 1976 1977 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 1978 1979 /* Should still have one CSR to read */ 1980 return SBIC_STATE_RUNNING; 1981 } 1982 1983 1984 /* 1985 * sbicnextstate() 1986 * return: 1987 * 0 == done 1988 * 1 == working 1989 * 2 == disconnected 1990 * -1 == error 1991 */ 1992 static int 1993 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 1994 { 1995 sbic_regmap_p regs; 1996 struct sbic_acb *acb; 1997 /* int i;*/ 1998 int newtarget, newlun, wait; 1999 /* unsigned tcnt;*/ 2000 2001 SBIC_TRACE(dev); 2002 regs = &dev->sc_sbicp; 2003 acb = dev->sc_nexus; 2004 2005 QPRINTF(("next[%02x,%02x]",asr,csr)); 2006 2007 switch (csr) { 2008 case SBIC_CSR_XFERRED | CMD_PHASE: 2009 case SBIC_CSR_MIS | CMD_PHASE: 2010 case SBIC_CSR_MIS_1 | CMD_PHASE: 2011 case SBIC_CSR_MIS_2 | CMD_PHASE: 2012 sbic_save_ptrs(dev, regs); 2013 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2014 if (sbicxfout(regs, acb->clen, 2015 &acb->cmd, CMD_PHASE)) 2016 goto abort; 2017 break; 2018 2019 case SBIC_CSR_XFERRED | STATUS_PHASE: 2020 case SBIC_CSR_MIS | STATUS_PHASE: 2021 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2022 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2023 /* 2024 * this should be the normal i/o completion case. 2025 * get the status & cmd complete msg then let the 2026 * device driver look at what happened. 2027 */ 2028 sbicxfdone(dev,regs,dev->target); 2029 2030 if (acb->flags & ACB_DMA) { 2031 DBG(dev->sc_dmatimo = 0); 2032 2033 dev->sc_dmafinish(dev->sc_dmah, dev->sc_dmat, acb); 2034 2035 dev->sc_flags &= ~SBICF_INDMA; 2036 } 2037 sbic_scsidone(acb, dev->sc_stat[0]); 2038 SBIC_TRACE(dev); 2039 return SBIC_STATE_DONE; 2040 2041 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2042 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2043 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2044 case SBIC_CSR_MIS | DATA_IN_PHASE: 2045 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2046 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2047 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2048 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2049 { 2050 int i = 0; 2051 2052 if ((acb->xs->xs_control & XS_CTL_POLL) || 2053 (dev->sc_flags & SBICF_ICMD) || 2054 (acb->flags & ACB_DMA) == 0) { 2055 /* Do PIO */ 2056 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2057 if (acb->datalen <= 0) { 2058 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2059 acb->datalen, asr, csr); 2060 goto abort; 2061 } 2062 wait = sbic_data_wait; 2063 if (sbicxfstart(regs, acb->datalen, 2064 SBIC_PHASE(csr), wait)) { 2065 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 2066 /* data in? */ 2067 i = sbicxfin(regs, acb->datalen, 2068 acb->data); 2069 else 2070 i = sbicxfout(regs, acb->datalen, 2071 acb->data, SBIC_PHASE(csr)); 2072 } 2073 acb->data += acb->datalen - i; 2074 acb->datalen = i; 2075 } else { 2076 /* Transfer = using DMA */ 2077 /* 2078 * do scatter-gather dma 2079 * hacking the controller chip, ouch.. 2080 */ 2081 SET_SBIC_control(regs, 2082 SBIC_CTL_EDI | SBIC_CTL_IDI | dev->sc_dmamode); 2083 /* 2084 * set next dma addr and dec count 2085 */ 2086 sbic_save_ptrs(dev, regs); 2087 2088 if (acb->offset >= acb->datalen) { 2089 printf("sbicnextstate:xfer offset %d asr%x csr%x\n", 2090 acb->offset, asr, csr); 2091 goto abort; 2092 } 2093 DBGPRINTF(("next dmanext: %d(offset %d)\n", 2094 dev->target, acb->offset), 2095 data_pointer_debug > 1); 2096 DBG(dev->sc_dmatimo = 1); 2097 2098 acb->sc_tcnt = 2099 dev->sc_dmanext(dev->sc_dmah, dev->sc_dmat, 2100 acb, acb->offset); 2101 DBGPRINTF(("dmanext transfering %ld bytes\n", 2102 acb->sc_tcnt), data_pointer_debug); 2103 SBIC_TC_PUT(regs, (unsigned)acb->sc_tcnt); 2104 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2105 dev->sc_flags |= SBICF_INDMA; 2106 } 2107 break; 2108 } 2109 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2110 case SBIC_CSR_MIS | MESG_IN_PHASE: 2111 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2112 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2113 SBIC_TRACE(dev); 2114 return sbicmsgin(dev); 2115 2116 case SBIC_CSR_MSGIN_W_ACK: 2117 /* Dunno what I'm ACKing */ 2118 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2119 printf("Acking unknown msgin CSR:%02x",csr); 2120 break; 2121 2122 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2123 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2124 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2125 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2126 2127 DBGPRINTF(("sending REJECT msg to last msg.\n"), sync_debug); 2128 2129 sbic_save_ptrs(dev, regs); 2130 /* 2131 * Should only get here on reject, since it's always 2132 * US that initiate a sync transfer. 2133 */ 2134 SEND_BYTE(regs, MSG_REJECT); 2135 WAIT_CIP(regs); 2136 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI | SBIC_ASR_CIP)) 2137 printf("next: REJECT sent asr %02x\n", asr); 2138 SBIC_TRACE(dev); 2139 return SBIC_STATE_RUNNING; 2140 2141 case SBIC_CSR_DISC: 2142 case SBIC_CSR_DISC_1: 2143 dev->sc_flags &= ~(SBICF_INDMA | SBICF_SELECTED); 2144 2145 /* Try to schedule another target */ 2146 DBGPRINTF(("sbicnext target %d disconnected\n", dev->target), 2147 reselect_debug > 1); 2148 2149 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2150 ++dev->sc_tinfo[dev->target].dconns; 2151 dev->sc_nexus = NULL; 2152 2153 if ((acb->xs->xs_control & XS_CTL_POLL) 2154 || (dev->sc_flags & SBICF_ICMD) 2155 || (!sbic_parallel_operations)) { 2156 SBIC_TRACE(dev); 2157 return SBIC_STATE_DISCONNECT; 2158 } 2159 sbic_sched(dev); 2160 SBIC_TRACE(dev); 2161 return SBIC_STATE_DISCONNECT; 2162 2163 case SBIC_CSR_RSLT_NI: 2164 case SBIC_CSR_RSLT_IFY: 2165 GET_SBIC_rselid(regs, newtarget); 2166 /* check SBIC_RID_SIV? */ 2167 newtarget &= SBIC_RID_MASK; 2168 if (csr == SBIC_CSR_RSLT_IFY) { 2169 /* Read IFY msg to avoid lockup */ 2170 GET_SBIC_data(regs, newlun); 2171 WAIT_CIP(regs); 2172 newlun &= SBIC_TLUN_MASK; 2173 CSR_TRACE('r',csr,asr,newtarget); 2174 } else { 2175 /* Need to get IFY message */ 2176 for (newlun = 256; newlun; --newlun) { 2177 GET_SBIC_asr(regs, asr); 2178 if (asr & SBIC_ASR_INT) 2179 break; 2180 delay(1); 2181 } 2182 newlun = 0; /* XXXX */ 2183 if ((asr & SBIC_ASR_INT) == 0) { 2184 2185 DBGPRINTF(("RSLT_NI - no IFFY message? asr %x\n", 2186 asr), reselect_debug); 2187 2188 } else { 2189 GET_SBIC_csr(regs,csr); 2190 CSR_TRACE('n',csr,asr,newtarget); 2191 if ((csr == (SBIC_CSR_MIS | MESG_IN_PHASE)) || 2192 (csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE)) || 2193 (csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE))) { 2194 sbicmsgin(dev); 2195 newlun = dev->sc_msg[0] & 7; 2196 } else { 2197 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2198 csr); 2199 } 2200 } 2201 } 2202 2203 DBGPRINTF(("sbicnext: reselect %s from targ %d lun %d\n", 2204 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2205 newtarget, newlun), 2206 reselect_debug > 1 || 2207 (reselect_debug && csr == SBIC_CSR_RSLT_NI)); 2208 2209 if (dev->sc_nexus) { 2210 DBGPRINTF(("%s: reselect %s with active command\n", 2211 dev->sc_dev.dv_xname, 2212 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"), 2213 reselect_debug > 1); 2214 #if defined(DDB) && defined (DEBUG) 2215 /* Debugger();*/ 2216 #endif 2217 2218 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, 2219 chain); 2220 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2221 dev->sc_nexus = NULL; 2222 } 2223 /* Reload sync values for this target */ 2224 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2225 SET_SBIC_syn(regs, 2226 SBIC_SYN(dev->sc_sync[newtarget].offset, 2227 dev->sc_sync[newtarget].period)); 2228 else 2229 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2230 for (acb = dev->nexus_list.tqh_first; acb; 2231 acb = acb->chain.tqe_next) { 2232 if (acb->xs->xs_periph->periph_target != newtarget || 2233 acb->xs->xs_periph->periph_lun != newlun) 2234 continue; 2235 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2236 dev->sc_nexus = acb; 2237 dev->sc_flags |= SBICF_SELECTED; 2238 dev->target = newtarget; 2239 dev->lun = newlun; 2240 break; 2241 } 2242 if (acb == NULL) { 2243 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2244 dev->sc_dev.dv_xname, 2245 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2246 &dev->nexus_list.tqh_first); 2247 panic("bad reselect in sbic"); 2248 } 2249 if (csr == SBIC_CSR_RSLT_IFY) 2250 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2251 break; 2252 2253 default: 2254 abort: 2255 /* 2256 * Something unexpected happened -- deal with it. 2257 */ 2258 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, 2259 asr); 2260 #ifdef DDB 2261 Debugger(); 2262 #endif 2263 DBG(dev->sc_dmatimo = 0); 2264 2265 if (dev->sc_flags & SBICF_INDMA) { 2266 dev->sc_dmafinish(dev->sc_dmah, dev->sc_dmat, acb); 2267 dev->sc_flags &= ~SBICF_INDMA; 2268 DBG(dev->sc_dmatimo = 0); 2269 } 2270 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2271 sbicerror(dev, regs, csr); 2272 sbicabort(dev, regs, "next"); 2273 sbic_scsidone(acb, -1); 2274 SBIC_TRACE(dev); 2275 return SBIC_STATE_ERROR; 2276 } 2277 2278 SBIC_TRACE(dev); 2279 return SBIC_STATE_RUNNING; 2280 } 2281 2282 static int 2283 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_p regs, int a) 2284 { 2285 unsigned int fs; 2286 2287 /* 2288 * cycle = DIV / (2*CLK) 2289 * DIV = FS+2 2290 * best we can do is 200ns at 20Mhz, 2 cycles 2291 */ 2292 2293 GET_SBIC_myid(regs,fs); 2294 fs = (fs >> 6) + 2; /* DIV */ 2295 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2296 if (a < 2) 2297 a = 8; /* map to Cycles */ 2298 return (fs * a) >> 2; /* in 4 ns units */ 2299 } 2300 2301 static int 2302 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_p regs, int p) 2303 { 2304 register unsigned int fs, ret; 2305 2306 /* Just the inverse of the above */ 2307 2308 GET_SBIC_myid(regs, fs); 2309 fs = (fs >> 6) + 2; /* DIV */ 2310 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2311 2312 ret = p << 2; /* in ns units */ 2313 ret = ret / fs; /* in Cycles */ 2314 if (ret < sbic_min_period) 2315 return sbic_min_period; 2316 2317 /* verify rounding */ 2318 if (sbictoscsiperiod(dev, regs, ret) < p) 2319 ret++; 2320 return (ret >= 8) ? 0 : ret; 2321 } 2322 2323 #ifdef DEBUG 2324 2325 void 2326 sbicdumpstate() 2327 { 2328 u_char csr, asr; 2329 2330 GET_SBIC_asr(debug_sbic_regs,asr); 2331 GET_SBIC_csr(debug_sbic_regs,csr); 2332 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2333 (routine == 1) ? "sbicgo" : 2334 (routine == 2) ? "sbicintr" : 2335 (routine == 3) ? "sbicicmd" : 2336 (routine == 4) ? "sbicnext" : "unknown", 2337 debug_asr, debug_csr, asr, csr); 2338 2339 } 2340 2341 void 2342 sbictimeout(struct sbic_softc *dev) 2343 { 2344 int s, asr; 2345 2346 s = splbio(); 2347 if (dev->sc_dmatimo) { 2348 if (dev->sc_dmatimo > 1) { 2349 printf("%s: dma timeout #%d\n", 2350 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2351 GET_SBIC_asr(&dev->sc_sbicp, asr); 2352 if (asr & SBIC_ASR_INT) { 2353 /* We need to service a missed IRQ */ 2354 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2355 debug_asr, debug_csr, asr); 2356 sbicintr(dev); 2357 } 2358 sbicdumpstate(); 2359 } 2360 dev->sc_dmatimo++; 2361 } 2362 splx(s); 2363 callout_reset(&dev->sc_timo_ch, 30 * hz, 2364 (void *)sbictimeout, dev); 2365 } 2366 2367 void 2368 sbic_dump_acb(struct sbic_acb *acb) 2369 { 2370 u_char *b = (u_char *) &acb->cmd; 2371 int i; 2372 2373 printf("acb@%p ", acb); 2374 if (acb->xs == NULL) { 2375 printf("<unused>\n"); 2376 return; 2377 } 2378 printf("(%d:%d) flags %2x clen %2d cmd ", 2379 acb->xs->xs_periph->periph_target, 2380 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2381 for (i = acb->clen; i; --i) 2382 printf(" %02x", *b++); 2383 printf("\n"); 2384 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2385 acb->xs->datalen); 2386 printf("tcnt %lx\n", acb->sc_tcnt); 2387 } 2388 2389 void 2390 sbic_dump(struct sbic_softc *dev) 2391 { 2392 sbic_regmap_p regs; 2393 u_char csr, asr; 2394 struct sbic_acb *acb; 2395 int s; 2396 int i; 2397 2398 s = splbio(); 2399 regs = &dev->sc_sbicp; 2400 #if CSR_TRACE_SIZE 2401 printf("csr trace: "); 2402 i = csr_traceptr; 2403 do { 2404 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2405 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2406 switch(csr_trace[i].whr) { 2407 case 'g': 2408 printf("go "); break; 2409 case 's': 2410 printf("select "); break; 2411 case 'y': 2412 printf("select+ "); break; 2413 case 'i': 2414 printf("intr "); break; 2415 case 'f': 2416 printf("finish "); break; 2417 case '>': 2418 printf("out "); break; 2419 case '<': 2420 printf("in "); break; 2421 case 'm': 2422 printf("msgin "); break; 2423 case 'x': 2424 printf("msginx "); break; 2425 case 'X': 2426 printf("msginX "); break; 2427 case 'r': 2428 printf("reselect "); break; 2429 case 'I': 2430 printf("icmd "); break; 2431 case 'a': 2432 printf("abort "); break; 2433 default: 2434 printf("? "); 2435 } 2436 switch(csr_trace[i].csr) { 2437 case 0x11: 2438 printf("INITIATOR"); break; 2439 case 0x16: 2440 printf("S_XFERRED"); break; 2441 case 0x20: 2442 printf("MSGIN_ACK"); break; 2443 case 0x41: 2444 printf("DISC"); break; 2445 case 0x42: 2446 printf("SEL_TIMEO"); break; 2447 case 0x80: 2448 printf("RSLT_NI"); break; 2449 case 0x81: 2450 printf("RSLT_IFY"); break; 2451 case 0x85: 2452 printf("DISC_1"); break; 2453 case 0x18: case 0x19: case 0x1a: 2454 case 0x1b: case 0x1e: case 0x1f: 2455 case 0x28: case 0x29: case 0x2a: 2456 case 0x2b: case 0x2e: case 0x2f: 2457 case 0x48: case 0x49: case 0x4a: 2458 case 0x4b: case 0x4e: case 0x4f: 2459 case 0x88: case 0x89: case 0x8a: 2460 case 0x8b: case 0x8e: case 0x8f: 2461 switch(csr_trace[i].csr & 0xf0) { 2462 case 0x10: 2463 printf("DONE_"); break; 2464 case 0x20: 2465 printf("STOP_"); break; 2466 case 0x40: 2467 printf("ERR_"); break; 2468 case 0x80: 2469 printf("REQ_"); break; 2470 } 2471 switch(csr_trace[i].csr & 7) { 2472 case 0: 2473 printf("DATA_OUT"); break; 2474 case 1: 2475 printf("DATA_IN"); break; 2476 case 2: 2477 printf("CMD"); break; 2478 case 3: 2479 printf("STATUS"); break; 2480 case 6: 2481 printf("MSG_OUT"); break; 2482 case 7: 2483 printf("MSG_IN"); break; 2484 default: 2485 printf("invld phs"); 2486 } 2487 break; 2488 default: printf("****"); break; 2489 } 2490 if (csr_trace[i].asr & SBIC_ASR_INT) 2491 printf(" ASR_INT"); 2492 if (csr_trace[i].asr & SBIC_ASR_LCI) 2493 printf(" ASR_LCI"); 2494 if (csr_trace[i].asr & SBIC_ASR_BSY) 2495 printf(" ASR_BSY"); 2496 if (csr_trace[i].asr & SBIC_ASR_CIP) 2497 printf(" ASR_CIP"); 2498 printf("\n"); 2499 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2500 } while (i != csr_traceptr); 2501 #endif 2502 GET_SBIC_asr(regs, asr); 2503 if ((asr & SBIC_ASR_INT) == 0) 2504 GET_SBIC_csr(regs, csr); 2505 else 2506 csr = 0; 2507 printf("%s@%p regs %p asr %x csr %x\n", dev->sc_dev.dv_xname, 2508 dev, regs, asr, csr); 2509 if ((acb = dev->free_list.tqh_first)) { 2510 printf("Free list:\n"); 2511 while (acb) { 2512 sbic_dump_acb(acb); 2513 acb = acb->chain.tqe_next; 2514 } 2515 } 2516 if ((acb = dev->ready_list.tqh_first)) { 2517 printf("Ready list:\n"); 2518 while (acb) { 2519 sbic_dump_acb(acb); 2520 acb = acb->chain.tqe_next; 2521 } 2522 } 2523 if ((acb = dev->nexus_list.tqh_first)) { 2524 printf("Nexus list:\n"); 2525 while (acb) { 2526 sbic_dump_acb(acb); 2527 acb = acb->chain.tqe_next; 2528 } 2529 } 2530 if (dev->sc_nexus) { 2531 printf("nexus:\n"); 2532 sbic_dump_acb(dev->sc_nexus); 2533 } 2534 printf("targ %d lun %d flags %x\n", 2535 dev->target, dev->lun, dev->sc_flags); 2536 for (i = 0; i < 8; ++i) { 2537 if (dev->sc_tinfo[i].cmds > 2) { 2538 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2539 i, dev->sc_tinfo[i].cmds, 2540 dev->sc_tinfo[i].dconns, 2541 dev->sc_tinfo[i].lubusy); 2542 } 2543 } 2544 splx(s); 2545 } 2546 2547 #endif 2548
Indexes created Tue Sep 30 11:09:46 GMT 2025