sbic.c revision 1.4
1 /* $NetBSD: sbic.c,v 1.4 2002/09/27 15:35:31 provos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Richard Earnshaw 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * 29 * Copyright (c) 1994 Christian E. Hopps 30 * Copyright (c) 1990 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to Berkeley by 34 * Van Jacobson of Lawrence Berkeley Laboratory. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the University of 47 * California, Berkeley and its contributors. 48 * 4. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * from: sbic.c,v 1.21 1996/01/07 22:01:54 65 */ 66 67 /* 68 * WD 33C93 scsi adaptor driver 69 */ 70 71 #if 0 72 /* 73 * The UPROTECTED_CSR code is bogus. It can read the csr (SCSI Status 74 * register) at times when an interrupt may be pending. Doing this will 75 * clear the interrupt, so we won't see it at times when we really need 76 * to. 77 */ 78 #define UNPROTECTED_CSR 79 #endif 80 81 #define DEBUG 82 /* #define SBIC_DEBUG(a) a */ 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 88 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.4 2002/09/27 15:35:31 provos Exp $"); 89 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/kernel.h> /* For hz */ 93 #include <sys/device.h> 94 #include <sys/buf.h> 95 96 #include <uvm/uvm_extern.h> 97 98 #include <machine/bus.h> 99 #include <machine/intr.h> 100 101 #include <dev/scsipi/scsi_all.h> 102 #include <dev/scsipi/scsipi_all.h> 103 #include <dev/scsipi/scsiconf.h> 104 105 #include <acorn32/podulebus/sbicreg.h> 106 #include <acorn32/podulebus/sbicvar.h> 107 108 /* 109 * SCSI delays 110 * In u-seconds, primarily for state changes on the SPC. 111 */ 112 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 113 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 114 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 115 116 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 117 118 static int sbicicmd (struct sbic_softc *, int, int, 119 struct sbic_acb *); 120 static int sbicgo (struct sbic_softc *, struct scsipi_xfer *); 121 static int sbicwait (sbic_regmap_p, char, int , int); 122 static int sbicselectbus (struct sbic_softc *, sbic_regmap_p, u_char, 123 u_char, u_char); 124 static int sbicxfstart (sbic_regmap_p, int, u_char, int); 125 static int sbicxfout (sbic_regmap_p regs, int, void *, int); 126 static int sbicfromscsiperiod (struct sbic_softc *, sbic_regmap_p, int); 127 static int sbictoscsiperiod (struct sbic_softc *, sbic_regmap_p, int); 128 static int sbicpoll (struct sbic_softc *); 129 static int sbicnextstate (struct sbic_softc *, u_char, u_char); 130 static int sbicmsgin (struct sbic_softc *); 131 static int sbicxfin (sbic_regmap_p regs, int, void *); 132 static int sbicabort (struct sbic_softc *, sbic_regmap_p, char *); 133 static void sbicxfdone (struct sbic_softc *, sbic_regmap_p, int); 134 static void sbicerror (struct sbic_softc *, sbic_regmap_p, u_char); 135 static void sbicreset (struct sbic_softc *); 136 static void sbic_scsidone (struct sbic_acb *, int); 137 static void sbic_sched (struct sbic_softc *); 138 static void sbic_save_ptrs (struct sbic_softc *, sbic_regmap_p); 139 140 /* 141 * Synch xfer parameters, and timing conversions 142 */ 143 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 144 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 145 146 int sbic_cmd_wait = SBIC_CMD_WAIT; 147 int sbic_data_wait = SBIC_DATA_WAIT; 148 int sbic_init_wait = SBIC_INIT_WAIT; 149 150 /* 151 * was broken before.. now if you want this you get it for all drives 152 * on sbic controllers. 153 */ 154 u_char sbic_inhibit_sync[8]; 155 int sbic_enable_reselect = 1; 156 int sbic_clock_override = 0; 157 int sbic_no_dma = 1; /* was 0 */ 158 int sbic_parallel_operations = 1; 159 160 #ifdef DEBUG 161 sbic_regmap_p debug_sbic_regs; 162 int sbicdma_ops = 0; /* total DMA operations */ 163 int sbicdma_saves = 0; 164 #define QPRINTF(a) if (sbic_debug > 1) printf a 165 #define DBGPRINTF(x,p) if (p) printf x 166 #define DBG(x) x 167 int sbic_debug = 0; 168 int sync_debug = 0; 169 int sbic_dma_debug = 0; 170 int reselect_debug = 0; 171 int data_pointer_debug = 0; 172 u_char debug_asr, debug_csr, routine; 173 174 void sbicdumpstate (void); 175 void sbictimeout (struct sbic_softc *); 176 void sbic_dump (struct sbic_softc *); 177 void sbic_dump_acb (struct sbic_acb *); 178 179 #define CSR_TRACE_SIZE 32 180 #if CSR_TRACE_SIZE 181 #define CSR_TRACE(w,c,a,x) do { \ 182 int s = splbio(); \ 183 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 184 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 185 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 186 splx(s); \ 187 } while (0) 188 int csr_traceptr; 189 int csr_tracesize = CSR_TRACE_SIZE; 190 struct { 191 u_char whr; 192 u_char csr; 193 u_char asr; 194 u_char xtn; 195 } csr_trace[CSR_TRACE_SIZE]; 196 #else 197 #define CSR_TRACE 198 #endif 199 200 #define SBIC_TRACE_SIZE 0 201 #if SBIC_TRACE_SIZE 202 #define SBIC_TRACE(dev) do { \ 203 int s = splbio(); \ 204 sbic_trace[sbic_traceptr].sp = &s; \ 205 sbic_trace[sbic_traceptr].line = __LINE__; \ 206 sbic_trace[sbic_traceptr].sr = s; \ 207 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 208 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 209 splx(s); \ 210 } while (0) 211 int sbic_traceptr; 212 int sbic_tracesize = SBIC_TRACE_SIZE; 213 struct { 214 void *sp; 215 u_short line; 216 u_short sr; 217 int csr; 218 } sbic_trace[SBIC_TRACE_SIZE]; 219 #else 220 #define SBIC_TRACE(dev) 221 #endif 222 223 #else 224 #define QPRINTF(a) 225 #define DBGPRINTF(x,p) 226 #define DBG(x) 227 #define CSR_TRACE 228 #define SBIC_TRACE 229 #endif 230 231 #ifndef SBIC_DEBUG 232 #define SBIC_DEBUG(x) 233 #endif 234 235 /* 236 * default minphys routine for sbic based controllers 237 */ 238 void 239 sbic_minphys(struct buf *bp) 240 { 241 /* 242 * No max transfer at this level. 243 */ 244 minphys(bp); 245 } 246 247 /* 248 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 249 */ 250 static void 251 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_p regs) 252 { 253 int count, asr, s; 254 struct sbic_acb* acb; 255 256 SBIC_TRACE(dev); 257 if (!(dev->sc_flags & SBICF_INDMA)) 258 return; /* DMA not active */ 259 260 s = splbio(); 261 262 acb = dev->sc_nexus; 263 if (acb == NULL) { 264 splx(s); 265 return; 266 } 267 count = -1; 268 do { 269 GET_SBIC_asr(regs, asr); 270 if (asr & SBIC_ASR_DBR) { 271 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 272 splx(s); 273 SBIC_TRACE(dev); 274 return; 275 } 276 } while (asr & (SBIC_ASR_BSY | SBIC_ASR_CIP)); 277 278 /* Save important state */ 279 /* must be done before dmastop */ 280 SBIC_TC_GET(regs, count); 281 282 /* Shut down DMA ====CAREFUL==== */ 283 dev->sc_dmastop(dev->sc_dmah, dev->sc_dmat, acb); 284 dev->sc_flags &= ~SBICF_INDMA; 285 #ifdef DIAGNOSTIC 286 { 287 int count2; 288 289 SBIC_TC_GET(regs, count2); 290 if (count2 != count) 291 panic("sbic_save_ptrs: DMA was still active(%d,%d)", 292 count, count2); 293 } 294 #endif 295 /* Note where we got to before stopping. We need this to resume 296 later. */ 297 acb->offset += acb->sc_tcnt - count; 298 SBIC_TC_PUT(regs, 0); 299 300 DBGPRINTF(("SBIC saving tgt %d data pointers: Offset now %d ASR:%02x", 301 dev->target, acb->offset, asr), data_pointer_debug >= 1); 302 303 acb->sc_tcnt = 0; 304 305 DBG(sbicdma_saves++); 306 splx(s); 307 SBIC_TRACE(dev); 308 } 309 310 /* 311 * used by specific sbic controller 312 * 313 * it appears that the higher level code does nothing with LUN's 314 * so I will too. I could plug it in, however so could they 315 * in scsi_scsi_cmd(). 316 */ 317 void 318 sbic_scsi_request(struct scsipi_channel *chan, 319 scsipi_adapter_req_t req, void *arg) 320 { 321 struct scsipi_xfer *xs; 322 struct sbic_acb *acb; 323 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 324 struct scsipi_periph *periph; 325 int flags, s, stat; 326 327 switch (req) { 328 case ADAPTER_REQ_RUN_XFER: 329 xs = arg; 330 periph = xs->xs_periph; 331 SBIC_TRACE(dev); 332 flags = xs->xs_control; 333 334 if (flags & XS_CTL_DATA_UIO) 335 panic("sbic: scsi data uio requested"); 336 337 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 338 panic("sbic_scsicmd: busy"); 339 340 s = splbio(); 341 acb = dev->free_list.tqh_first; 342 if (acb) 343 TAILQ_REMOVE(&dev->free_list, acb, chain); 344 splx(s); 345 346 if (acb == NULL) { 347 DBG(printf("sbic_scsicmd: unable to queue request for " 348 "target %d\n", periph->periph_target)); 349 #if defined(DDB) && defined(DEBUG) 350 Debugger(); 351 #endif 352 xs->error = XS_RESOURCE_SHORTAGE; 353 SBIC_TRACE(dev); 354 scsipi_done(xs); 355 return; 356 } 357 358 acb->flags = ACB_ACTIVE; 359 if (flags & XS_CTL_DATA_IN) 360 acb->flags |= ACB_DATAIN; 361 acb->xs = xs; 362 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 363 acb->clen = xs->cmdlen; 364 acb->data = xs->data; 365 acb->datalen = xs->datalen; 366 367 QPRINTF(("sbic_scsi_request: Cmd %02x (len %d), Data %p(%d)\n", 368 (unsigned) acb->cmd.opcode, acb->clen, xs->data, 369 xs->datalen)); 370 if (flags & XS_CTL_POLL) { 371 s = splbio(); 372 /* 373 * This has major side effects -- it locks up the 374 * machine. 375 */ 376 377 dev->sc_flags |= SBICF_ICMD; 378 do { 379 while (dev->sc_nexus) 380 sbicpoll(dev); 381 dev->sc_nexus = acb; 382 dev->sc_stat[0] = -1; 383 dev->target = periph->periph_target; 384 dev->lun = periph->periph_lun; 385 stat = sbicicmd(dev, periph->periph_target, 386 periph->periph_lun, acb); 387 } while (dev->sc_nexus != acb); 388 389 sbic_scsidone(acb, stat); 390 splx(s); 391 SBIC_TRACE(dev); 392 return; 393 } 394 395 s = splbio(); 396 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 397 398 if (dev->sc_nexus) { 399 splx(s); 400 SBIC_TRACE(dev); 401 return; 402 } 403 404 /* 405 * Nothing is active, try to start it now. 406 */ 407 sbic_sched(dev); 408 splx(s); 409 410 SBIC_TRACE(dev); 411 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 412 return; 413 414 case ADAPTER_REQ_GROW_RESOURCES: 415 case ADAPTER_REQ_SET_XFER_MODE: 416 /* XXX Not supported. */ 417 return; 418 } 419 } 420 421 /* 422 * attempt to start the next available command 423 */ 424 static void 425 sbic_sched(struct sbic_softc *dev) 426 { 427 struct scsipi_xfer *xs; 428 struct scsipi_periph *periph; 429 struct sbic_acb *acb; 430 int flags, /*phase,*/ stat, i; 431 432 SBIC_TRACE(dev); 433 if (dev->sc_nexus) 434 return; /* a command is current active */ 435 436 SBIC_TRACE(dev); 437 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 438 periph = acb->xs->xs_periph; 439 i = periph->periph_target; 440 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 441 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 442 443 TAILQ_REMOVE(&dev->ready_list, acb, chain); 444 dev->sc_nexus = acb; 445 periph = acb->xs->xs_periph; 446 ti = &dev->sc_tinfo[periph->periph_target]; 447 ti->lubusy |= (1 << periph->periph_lun); 448 break; 449 } 450 } 451 452 SBIC_TRACE(dev); 453 if (acb == NULL) 454 return; /* did not find an available command */ 455 456 xs = acb->xs; 457 periph = xs->xs_periph; 458 flags = xs->xs_control; 459 460 if (flags & XS_CTL_RESET) 461 sbicreset(dev); 462 463 DBGPRINTF(("sbic_sched(%d,%d)\n", periph->periph_target, 464 periph->periph_lun), data_pointer_debug > 1); 465 DBG(if (data_pointer_debug > 1) sbic_dump_acb(acb)); 466 dev->sc_stat[0] = -1; 467 dev->target = periph->periph_target; 468 dev->lun = periph->periph_lun; 469 470 /* Decide if we can use DMA for this transfer. */ 471 if ((flags & XS_CTL_POLL) == 0 472 && !sbic_no_dma 473 && dev->sc_dmaok(dev->sc_dmah, dev->sc_dmat, acb)) 474 acb->flags |= ACB_DMA; 475 476 if ((flags & XS_CTL_POLL) || 477 (!sbic_parallel_operations && (acb->flags & ACB_DMA) == 0)) 478 stat = sbicicmd(dev, periph->periph_target, 479 periph->periph_lun, acb); 480 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 481 SBIC_TRACE(dev); 482 return; 483 } else 484 stat = dev->sc_stat[0]; 485 486 sbic_scsidone(acb, stat); 487 SBIC_TRACE(dev); 488 } 489 490 static void 491 sbic_scsidone(struct sbic_acb *acb, int stat) 492 { 493 struct scsipi_xfer *xs; 494 struct scsipi_periph *periph; 495 struct sbic_softc *dev; 496 /* int s;*/ 497 int dosched = 0; 498 499 xs = acb->xs; 500 periph = xs->xs_periph; 501 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 502 SBIC_TRACE(dev); 503 #ifdef DIAGNOSTIC 504 if (acb == NULL || xs == NULL) { 505 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", 506 dev->target, dev->lun); 507 #ifdef DDB 508 Debugger(); 509 #endif 510 return; 511 } 512 #endif 513 514 DBGPRINTF(("scsidone: (%d,%d)->(%d,%d)%02x acbfl=%x\n", 515 periph->periph_target, periph->periph_lun, 516 dev->target, dev->lun, stat, acb->flags), 517 data_pointer_debug > 1); 518 DBG(if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) 519 panic("target == hostid")); 520 521 xs->status = stat; 522 xs->resid = 0; 523 if (xs->error == XS_NOERROR) { 524 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 525 xs->error = XS_BUSY; 526 } 527 528 /* 529 * Remove the ACB from whatever queue it's on. We have to do a bit of 530 * a hack to figure out which queue it's on. Note that it is *not* 531 * necessary to cdr down the ready queue, but we must cdr down the 532 * nexus queue and see if it's there, so we can mark the unit as no 533 * longer busy. This code is sickening, but it works. 534 */ 535 if (acb == dev->sc_nexus) { 536 dev->sc_nexus = NULL; 537 dev->sc_tinfo[periph->periph_target].lubusy &= 538 ~(1 << periph->periph_lun); 539 if (dev->ready_list.tqh_first) 540 dosched = 1; /* start next command */ 541 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 542 TAILQ_REMOVE(&dev->ready_list, acb, chain); 543 } else { 544 register struct sbic_acb *acb2; 545 for (acb2 = dev->nexus_list.tqh_first; acb2; 546 acb2 = acb2->chain.tqe_next) { 547 if (acb2 == acb) { 548 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 549 dev->sc_tinfo[periph->periph_target].lubusy 550 &= ~(1 << periph->periph_lun); 551 break; 552 } 553 } 554 if (acb2) 555 ; 556 else if (acb->chain.tqe_next) { 557 TAILQ_REMOVE(&dev->ready_list, acb, chain); 558 } else { 559 printf("%s: can't find matching acb\n", 560 dev->sc_dev.dv_xname); 561 #ifdef DDB 562 Debugger(); 563 #endif 564 } 565 } 566 /* Put it on the free list. */ 567 acb->flags = ACB_FREE; 568 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 569 570 dev->sc_tinfo[periph->periph_target].cmds++; 571 572 scsipi_done(xs); 573 574 if (dosched) 575 sbic_sched(dev); 576 SBIC_TRACE(dev); 577 } 578 579 static int 580 sbicwait(sbic_regmap_p regs, char until, int timeo, int line) 581 { 582 u_char val; 583 int csr; 584 585 SBIC_TRACE((struct sbic_softc *)0); 586 if (timeo == 0) 587 timeo = 1000000; /* some large value.. */ 588 589 GET_SBIC_asr(regs,val); 590 while ((val & until) == 0) { 591 if (timeo-- == 0) { 592 GET_SBIC_csr(regs, csr); 593 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 594 line, val, csr); 595 #if defined(DDB) && defined(DEBUG) 596 Debugger(); 597 #endif 598 return val; /* Maybe I should abort */ 599 break; 600 } 601 DELAY(1); 602 GET_SBIC_asr(regs,val); 603 } 604 SBIC_TRACE((struct sbic_softc *)0); 605 return val; 606 } 607 608 static int 609 sbicabort(struct sbic_softc *dev, sbic_regmap_p regs, char *where) 610 { 611 u_char csr, asr; 612 613 GET_SBIC_asr(regs, asr); 614 GET_SBIC_csr(regs, csr); 615 616 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 617 dev->sc_dev.dv_xname, where, csr, asr); 618 619 620 #if 0 621 /* Clean up running command */ 622 if (dev->sc_nexus != NULL) { 623 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 624 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 625 } 626 while (acb = dev->nexus_list.tqh_first) { 627 acb->xs->error = XS_DRIVER_STUFFUP; 628 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 629 } 630 #endif 631 632 /* Clean up chip itself */ 633 if (dev->sc_flags & SBICF_SELECTED) { 634 while (asr & SBIC_ASR_DBR) { 635 /* sbic is jammed w/data. need to clear it */ 636 /* But we don't know what direction it needs to go */ 637 GET_SBIC_data(regs, asr); 638 printf("%s: abort %s: clearing data buffer 0x%02x\n", 639 dev->sc_dev.dv_xname, where, asr); 640 GET_SBIC_asr(regs, asr); 641 /* Not the read direction, then */ 642 if (asr & SBIC_ASR_DBR) 643 SET_SBIC_data(regs, asr); 644 GET_SBIC_asr(regs, asr); 645 } 646 WAIT_CIP(regs); 647 printf("%s: sbicabort - sending ABORT command\n", 648 dev->sc_dev.dv_xname); 649 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 650 WAIT_CIP(regs); 651 652 GET_SBIC_asr(regs, asr); 653 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI)) { 654 /* ok, get more drastic.. */ 655 656 printf("%s: sbicabort - asr %x, trying to reset\n", 657 dev->sc_dev.dv_xname, asr); 658 sbicreset(dev); 659 dev->sc_flags &= ~SBICF_SELECTED; 660 return -1; 661 } 662 printf("%s: sbicabort - sending DISC command\n", 663 dev->sc_dev.dv_xname); 664 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 665 666 do { 667 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 668 GET_SBIC_csr (regs, csr); 669 CSR_TRACE('a',csr,asr,0); 670 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 671 && (csr != SBIC_CSR_CMD_INVALID)); 672 673 /* lets just hope it worked.. */ 674 dev->sc_flags &= ~SBICF_SELECTED; 675 } 676 return -1; 677 } 678 679 680 /* 681 * Initialize driver-private structures 682 */ 683 684 int 685 sbicinit(struct sbic_softc *dev) 686 { 687 sbic_regmap_p regs; 688 u_int i; 689 /* u_int my_id, s;*/ 690 /* u_char csr;*/ 691 struct sbic_acb *acb; 692 u_int inhibit_sync; 693 694 extern u_long scsi_nosync; 695 extern int shift_nosync; 696 697 SBIC_DEBUG(printf("sbicinit:\n")); 698 699 regs = &dev->sc_sbicp; 700 701 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 702 TAILQ_INIT(&dev->ready_list); 703 TAILQ_INIT(&dev->nexus_list); 704 TAILQ_INIT(&dev->free_list); 705 callout_init(&dev->sc_timo_ch); 706 dev->sc_nexus = NULL; 707 acb = dev->sc_acb; 708 memset(acb, 0, sizeof(dev->sc_acb)); 709 710 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 711 712 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 713 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 714 acb++; 715 } 716 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 717 /* make sure timeout is really not needed */ 718 DBG(callout_reset(&dev->sc_timo_ch, 30 * hz, 719 (void *)sbictimeout, dev)); 720 } else 721 panic("sbic: reinitializing driver!"); 722 723 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 724 725 dev->sc_flags |= SBICF_ALIVE; 726 dev->sc_flags &= ~SBICF_SELECTED; 727 728 /* initialize inhibit array */ 729 if (scsi_nosync) { 730 731 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 732 733 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 734 shift_nosync += 8; 735 736 DBGPRINTF(("%s: Inhibiting synchronous transfer %02x\n", 737 dev->sc_dev.dv_xname, inhibit_sync), inhibit_sync); 738 739 for (i = 0; i < 8; ++i) 740 if (inhibit_sync & (1 << i)) 741 sbic_inhibit_sync[i] = 1; 742 } 743 744 SBIC_DEBUG(printf("sbicinit: %d\n", __LINE__)); 745 746 sbicreset(dev); 747 return 0; 748 } 749 750 static void 751 sbicreset(struct sbic_softc *dev) 752 { 753 sbic_regmap_p regs; 754 u_int my_id, s; 755 /* u_int i;*/ 756 u_char csr; 757 /* struct sbic_acb *acb;*/ 758 759 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 760 761 regs = &dev->sc_sbicp; 762 763 SBIC_DEBUG(printf("sbicreset: regs = %08x\n", regs)); 764 765 #if 0 766 if (dev->sc_flags & SBICF_ALIVE) { 767 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 768 WAIT_CIP(regs); 769 } 770 #else 771 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 772 773 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 774 775 WAIT_CIP(regs); 776 777 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 778 #endif 779 s = splbio(); 780 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 781 782 /* Enable advanced mode */ 783 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 784 SET_SBIC_myid(regs, my_id); 785 786 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 787 788 /* 789 * Disable interrupts (in dmainit) then reset the chip 790 */ 791 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 792 DELAY(25); 793 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 794 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 795 796 if (dev->sc_clkfreq < 110) 797 my_id |= SBIC_ID_FS_8_10; 798 else if (dev->sc_clkfreq < 160) 799 my_id |= SBIC_ID_FS_12_15; 800 else if (dev->sc_clkfreq < 210) 801 my_id |= SBIC_ID_FS_16_20; 802 803 SET_SBIC_myid(regs, my_id); 804 805 SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__)); 806 807 /* 808 * Set up various chip parameters 809 */ 810 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 811 | dev->sc_dmamode); 812 /* 813 * don't allow (re)selection (SBIC_RID_ES) 814 * until we can handle target mode!! 815 */ 816 SET_SBIC_rselid(regs, SBIC_RID_ER); 817 SET_SBIC_syn(regs, 0); /* asynch for now */ 818 819 /* 820 * anything else was zeroed by reset 821 */ 822 splx(s); 823 824 #if 0 825 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 826 TAILQ_INIT(&dev->ready_list); 827 TAILQ_INIT(&dev->nexus_list); 828 TAILQ_INIT(&dev->free_list); 829 dev->sc_nexus = NULL; 830 acb = dev->sc_acb; 831 memset(acb, 0, sizeof(dev->sc_acb)); 832 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 833 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 834 acb++; 835 } 836 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 837 } else { 838 if (dev->sc_nexus != NULL) { 839 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 840 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 841 } 842 while (acb = dev->nexus_list.tqh_first) { 843 acb->xs->error = XS_DRIVER_STUFFUP; 844 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 845 } 846 } 847 848 dev->sc_flags |= SBICF_ALIVE; 849 #endif 850 dev->sc_flags &= ~SBICF_SELECTED; 851 } 852 853 static void 854 sbicerror(struct sbic_softc *dev, sbic_regmap_p regs, u_char csr) 855 { 856 #ifdef DIAGNOSTIC 857 if (dev->sc_nexus == NULL) 858 panic("sbicerror"); 859 #endif 860 if (dev->sc_nexus->xs->xs_control & XS_CTL_SILENT) 861 return; 862 863 printf("%s: ", dev->sc_dev.dv_xname); 864 printf("csr == 0x%02x\n", csr); /* XXX */ 865 } 866 867 /* 868 * select the bus, return when selected or error. 869 */ 870 static int 871 sbicselectbus(struct sbic_softc *dev, sbic_regmap_p regs, u_char target, 872 u_char lun, u_char our_addr) 873 { 874 u_char asr, csr, id; 875 876 SBIC_TRACE(dev); 877 QPRINTF(("sbicselectbus %d\n", target)); 878 879 /* 880 * if we're already selected, return (XXXX panic maybe?) 881 */ 882 if (dev->sc_flags & SBICF_SELECTED) { 883 SBIC_TRACE(dev); 884 return 1; 885 } 886 887 /* 888 * issue select 889 */ 890 SBIC_TC_PUT(regs, 0); 891 SET_SBIC_selid(regs, target); 892 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 893 894 /* 895 * set sync or async 896 */ 897 if (dev->sc_sync[target].state == SYNC_DONE) 898 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 899 dev->sc_sync[target].period)); 900 else 901 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 902 903 GET_SBIC_asr(regs, asr); 904 if (asr & (SBIC_ASR_INT | SBIC_ASR_BSY)) { 905 /* This means we got ourselves reselected upon */ 906 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 907 #ifdef DDB 908 /* Debugger();*/ 909 #endif 910 SBIC_TRACE(dev); 911 return 1; 912 } 913 914 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 915 916 /* 917 * wait for select (merged from separate function may need 918 * cleanup) 919 */ 920 WAIT_CIP(regs); 921 do { 922 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 923 if (asr & SBIC_ASR_LCI) { 924 925 DBGPRINTF(("sbicselectbus: late LCI asr %02x\n", asr), 926 reselect_debug); 927 928 SBIC_TRACE(dev); 929 return 1; 930 } 931 GET_SBIC_csr (regs, csr); 932 CSR_TRACE('s',csr,asr,target); 933 QPRINTF(("%02x ", csr)); 934 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 935 936 DBGPRINTF(("sbicselectbus: reselected asr %02x\n", 937 asr), reselect_debug); 938 939 /* We need to handle this now so we don't lock 940 up later */ 941 sbicnextstate(dev, csr, asr); 942 SBIC_TRACE(dev); 943 return 1; 944 } 945 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 946 panic("sbicselectbus: target issued select!"); 947 return 1; 948 } 949 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 950 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 951 csr != SBIC_CSR_SEL_TIMEO); 952 953 /* Enable (or not) reselection */ 954 if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 955 SET_SBIC_rselid (regs, 0); 956 else 957 SET_SBIC_rselid (regs, SBIC_RID_ER); 958 959 if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) { 960 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 961 GET_SBIC_selid(regs, id); 962 dev->target = id; 963 GET_SBIC_tlun(regs,dev->lun); 964 if (dev->lun & SBIC_TLUN_VALID) 965 dev->lun &= SBIC_TLUN_MASK; 966 else 967 dev->lun = lun; 968 } else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 969 /* 970 * Send identify message 971 * (SCSI-2 requires an identify msg (?)) 972 */ 973 GET_SBIC_selid(regs, id); 974 dev->target = id; 975 GET_SBIC_tlun(regs,dev->lun); 976 if (dev->lun & SBIC_TLUN_VALID) 977 dev->lun &= SBIC_TLUN_MASK; 978 else 979 dev->lun = lun; 980 /* 981 * handle drives that don't want to be asked 982 * whether to go sync at all. 983 */ 984 if (sbic_inhibit_sync[id] 985 && dev->sc_sync[id].state == SYNC_START) { 986 DBGPRINTF(("Forcing target %d asynchronous.\n", id), 987 sync_debug); 988 989 dev->sc_sync[id].offset = 0; 990 dev->sc_sync[id].period = sbic_min_period; 991 dev->sc_sync[id].state = SYNC_DONE; 992 } 993 994 995 if (dev->sc_sync[id].state != SYNC_START){ 996 if ((dev->sc_nexus->xs->xs_control & XS_CTL_POLL) 997 || (dev->sc_flags & SBICF_ICMD) 998 || !sbic_enable_reselect) 999 SEND_BYTE(regs, MSG_IDENTIFY | lun); 1000 else 1001 SEND_BYTE(regs, MSG_IDENTIFY_DR | lun); 1002 } else { 1003 /* 1004 * try to initiate a sync transfer. 1005 * So compose the sync message we're going 1006 * to send to the target 1007 */ 1008 1009 DBGPRINTF(("Sending sync request to target %d ... ", 1010 id), sync_debug); 1011 1012 /* 1013 * setup scsi message sync message request 1014 */ 1015 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1016 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1017 dev->sc_msg[2] = 3; 1018 dev->sc_msg[3] = MSG_SYNC_REQ; 1019 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1020 sbic_min_period); 1021 dev->sc_msg[5] = sbic_max_offset; 1022 1023 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, 1024 sbic_cmd_wait)) 1025 sbicxfout(regs, 6, dev->sc_msg, 1026 MESG_OUT_PHASE); 1027 1028 dev->sc_sync[id].state = SYNC_SENT; 1029 1030 DBGPRINTF(("sent\n"), sync_debug); 1031 } 1032 1033 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1034 GET_SBIC_csr (regs, csr); 1035 CSR_TRACE('y',csr,asr,target); 1036 QPRINTF(("[%02x]", csr)); 1037 1038 DBGPRINTF(("csr-result of last msgout: 0x%x\n", csr), 1039 sync_debug && dev->sc_sync[id].state == SYNC_SENT); 1040 1041 if (csr != SBIC_CSR_SEL_TIMEO) 1042 dev->sc_flags |= SBICF_SELECTED; 1043 } 1044 if (csr == SBIC_CSR_SEL_TIMEO) 1045 dev->sc_nexus->xs->error = XS_SELTIMEOUT; 1046 1047 QPRINTF(("\n")); 1048 1049 SBIC_TRACE(dev); 1050 return csr == SBIC_CSR_SEL_TIMEO; 1051 } 1052 1053 static int 1054 sbicxfstart(sbic_regmap_p regs, int len, u_char phase, int wait) 1055 { 1056 u_char id; 1057 1058 switch (phase) { 1059 case DATA_IN_PHASE: 1060 case MESG_IN_PHASE: 1061 GET_SBIC_selid (regs, id); 1062 id |= SBIC_SID_FROM_SCSI; 1063 SET_SBIC_selid (regs, id); 1064 SBIC_TC_PUT (regs, (unsigned)len); 1065 break; 1066 case DATA_OUT_PHASE: 1067 case MESG_OUT_PHASE: 1068 case CMD_PHASE: 1069 GET_SBIC_selid (regs, id); 1070 id &= ~SBIC_SID_FROM_SCSI; 1071 SET_SBIC_selid (regs, id); 1072 SBIC_TC_PUT (regs, (unsigned)len); 1073 break; 1074 default: 1075 SBIC_TC_PUT (regs, 0); 1076 } 1077 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1078 1079 return 1; 1080 } 1081 1082 static int 1083 sbicxfout(sbic_regmap_p regs, int len, void *bp, int phase) 1084 { 1085 #ifdef UNPROTECTED_CSR 1086 u_char orig_csr 1087 #endif 1088 u_char asr, *buf; 1089 /* u_char csr;*/ 1090 int wait; 1091 1092 buf = bp; 1093 wait = sbic_data_wait; 1094 1095 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1096 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1097 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1098 1099 #ifdef UNPROTECTED_CSR 1100 GET_SBIC_csr (regs, orig_csr); 1101 CSR_TRACE('>',orig_csr,0,0); 1102 #endif 1103 1104 /* 1105 * sigh.. WD-PROTO strikes again.. sending the command in one go 1106 * causes the chip to lock up if talking to certain (misbehaving?) 1107 * targets. Anyway, this procedure should work for all targets, but 1108 * it's slightly slower due to the overhead 1109 */ 1110 WAIT_CIP (regs); 1111 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1112 for (;len > 0; len--) { 1113 GET_SBIC_asr (regs, asr); 1114 while ((asr & SBIC_ASR_DBR) == 0) { 1115 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1116 1117 DBGPRINTF(("sbicxfout fail: l%d i%x w%d\n", 1118 len, asr, wait), sbic_debug); 1119 1120 return len; 1121 } 1122 /* DELAY(1);*/ 1123 GET_SBIC_asr (regs, asr); 1124 } 1125 1126 SET_SBIC_data (regs, *buf); 1127 buf++; 1128 } 1129 SBIC_TC_GET(regs, len); 1130 QPRINTF(("sbicxfout done %d bytes\n", len)); 1131 /* 1132 * this leaves with one csr to be read 1133 */ 1134 return 0; 1135 } 1136 1137 /* returns # bytes left to read */ 1138 static int 1139 sbicxfin(sbic_regmap_p regs, int len, void *bp) 1140 { 1141 int wait; 1142 /* int read;*/ 1143 u_char *obp, *buf; 1144 #ifdef UNPROTECTED_CSR 1145 u_char orig_csr, csr; 1146 #endif 1147 u_char asr; 1148 1149 wait = sbic_data_wait; 1150 obp = bp; 1151 buf = bp; 1152 1153 #ifdef UNPROTECTED_CSR 1154 GET_SBIC_csr (regs, orig_csr); 1155 CSR_TRACE('<',orig_csr,0,0); 1156 1157 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1158 #endif 1159 1160 WAIT_CIP (regs); 1161 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1162 for (;len > 0; len--) { 1163 GET_SBIC_asr (regs, asr); 1164 if ((asr & SBIC_ASR_PE)) { 1165 DBG(printf("sbicxfin parity error: l%d i%x w%d\n", 1166 len, asr, wait)); 1167 #if defined(DDB) && defined(DEBUG) 1168 Debugger(); 1169 #endif 1170 DBG(return ((unsigned long)buf - (unsigned long)bp)); 1171 } 1172 while ((asr & SBIC_ASR_DBR) == 0) { 1173 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1174 1175 DBG(if (sbic_debug) { 1176 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1177 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1178 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1179 printf("sbicxfin fail: l%d i%x w%d\n", len, asr, wait); }); 1180 1181 return len; 1182 } 1183 1184 #ifdef UNPROTECTED_CSR 1185 if (!(asr & SBIC_ASR_BSY)) { 1186 GET_SBIC_csr(regs, csr); 1187 CSR_TRACE('<',csr,asr,len); 1188 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1189 } 1190 #endif 1191 1192 /* DELAY(1);*/ 1193 GET_SBIC_asr (regs, asr); 1194 } 1195 1196 GET_SBIC_data (regs, *buf); 1197 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1198 buf++; 1199 } 1200 1201 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1202 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1203 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1204 1205 /* this leaves with one csr to be read */ 1206 return len; 1207 } 1208 1209 /* 1210 * SCSI 'immediate' command: issue a command to some SCSI device 1211 * and get back an 'immediate' response (i.e., do programmed xfer 1212 * to get the response data). 'cbuf' is a buffer containing a scsi 1213 * command of length clen bytes. 'buf' is a buffer of length 'len' 1214 * bytes for data. The transfer direction is determined by the device 1215 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1216 * command must supply no data. 1217 */ 1218 static int 1219 sbicicmd(struct sbic_softc *dev, int target, int lun, struct sbic_acb *acb) 1220 { 1221 sbic_regmap_p regs; 1222 u_char phase, csr, asr; 1223 int wait; 1224 /* int newtarget, cmd_sent, parity_err;*/ 1225 1226 /* int discon;*/ 1227 int i; 1228 1229 void *cbuf, *buf; 1230 int clen, len; 1231 1232 #define CSR_LOG_BUF_SIZE 0 1233 #if CSR_LOG_BUF_SIZE 1234 int bufptr; 1235 int csrbuf[CSR_LOG_BUF_SIZE]; 1236 bufptr = 0; 1237 #endif 1238 1239 cbuf = &acb->cmd; 1240 clen = acb->clen; 1241 buf = acb->data; 1242 len = acb->datalen; 1243 1244 SBIC_TRACE(dev); 1245 regs = &dev->sc_sbicp; 1246 1247 acb->sc_tcnt = 0; 1248 1249 DBG(routine = 3); 1250 DBG(debug_sbic_regs = regs); /* store this to allow debug calls */ 1251 DBGPRINTF(("sbicicmd(%d,%d):%d\n", target, lun, len), 1252 data_pointer_debug > 1); 1253 1254 /* 1255 * set the sbic into non-DMA mode 1256 */ 1257 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1258 1259 dev->sc_stat[0] = 0xff; 1260 dev->sc_msg[0] = 0xff; 1261 i = 1; /* pre-load */ 1262 1263 /* We're stealing the SCSI bus */ 1264 dev->sc_flags |= SBICF_ICMD; 1265 1266 do { 1267 /* 1268 * select the SCSI bus (it's an error if bus isn't free) 1269 */ 1270 if (!(dev->sc_flags & SBICF_SELECTED) 1271 && sbicselectbus(dev, regs, target, lun, 1272 dev->sc_scsiaddr)) { 1273 /*printf("sbicicmd trying to select busy bus!\n");*/ 1274 dev->sc_flags &= ~SBICF_ICMD; 1275 return -1; 1276 } 1277 1278 /* 1279 * Wait for a phase change (or error) then let the 1280 * device sequence us through the various SCSI phases. 1281 */ 1282 1283 wait = sbic_cmd_wait; 1284 1285 asr = GET_SBIC_asr (regs, asr); 1286 GET_SBIC_csr (regs, csr); 1287 CSR_TRACE('I',csr,asr,target); 1288 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1289 1290 #if CSR_LOG_BUF_SIZE 1291 csrbuf[bufptr++] = csr; 1292 #endif 1293 1294 1295 switch (csr) { 1296 case SBIC_CSR_S_XFERRED: 1297 case SBIC_CSR_DISC: 1298 case SBIC_CSR_DISC_1: 1299 dev->sc_flags &= ~SBICF_SELECTED; 1300 GET_SBIC_cmd_phase (regs, phase); 1301 if (phase == 0x60) { 1302 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1303 i = 0; /* done */ 1304 /* break;*/ /* Bypass all the state gobldygook */ 1305 } else { 1306 DBGPRINTF(("sbicicmd: handling disconnect\n"), 1307 reselect_debug > 1); 1308 1309 i = SBIC_STATE_DISCONNECT; 1310 } 1311 break; 1312 1313 case SBIC_CSR_XFERRED | CMD_PHASE: 1314 case SBIC_CSR_MIS | CMD_PHASE: 1315 case SBIC_CSR_MIS_1 | CMD_PHASE: 1316 case SBIC_CSR_MIS_2 | CMD_PHASE: 1317 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1318 if (sbicxfout(regs, clen, 1319 cbuf, CMD_PHASE)) 1320 i = sbicabort(dev, regs, 1321 "icmd sending cmd"); 1322 #if 0 1323 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1324 WAIT_CIP(regs); 1325 GET_SBIC_asr(regs, asr); 1326 CSR_TRACE('I',csr,asr,target); 1327 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI | SBIC_ASR_CIP)) 1328 printf("next: cmd sent asr %02x, csr %02x\n", 1329 asr, csr); 1330 #endif 1331 break; 1332 1333 #if 0 1334 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1335 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1336 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1337 case SBIC_CSR_MIS | DATA_IN_PHASE: 1338 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1339 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1340 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1341 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1342 if (acb->datalen <= 0) 1343 i = sbicabort(dev, regs, "icmd out of data"); 1344 else { 1345 wait = sbic_data_wait; 1346 if (sbicxfstart(regs, acb->datalen, 1347 SBIC_PHASE(csr), wait)) 1348 if (csr & 0x01) 1349 /* data in? */ 1350 i = sbicxfin(regs, acb->datalen, acb->data); 1351 else 1352 i = sbicxfout(regs, acb->datalen, acb->data, 1353 SBIC_PHASE(csr)); 1354 acb->data += acb->datalen - i; 1355 acb->datalen = i; 1356 i = 1; 1357 } 1358 break; 1359 1360 #endif 1361 case SBIC_CSR_XFERRED | STATUS_PHASE: 1362 case SBIC_CSR_MIS | STATUS_PHASE: 1363 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1364 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1365 /* 1366 * the sbic does the status/cmd-complete reading ok, 1367 * so do this with its hi-level commands. 1368 */ 1369 DBGPRINTF(("SBICICMD status phase\n"), sbic_debug); 1370 1371 SBIC_TC_PUT(regs, 0); 1372 SET_SBIC_cmd_phase(regs, 0x46); 1373 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1374 break; 1375 1376 #if THIS_IS_A_RESERVED_STATE 1377 case BUS_FREE_PHASE: /* This is not legal */ 1378 if (dev->sc_stat[0] != 0xff) 1379 goto out; 1380 break; 1381 #endif 1382 1383 default: 1384 i = sbicnextstate(dev, csr, asr); 1385 } 1386 1387 /* 1388 * make sure the last command was taken, 1389 * ie. we're not hunting after an ignored command.. 1390 */ 1391 GET_SBIC_asr(regs, asr); 1392 1393 /* tapes may take a loooong time.. */ 1394 while (asr & SBIC_ASR_BSY){ 1395 if (asr & SBIC_ASR_DBR) { 1396 printf("sbicicmd: Waiting while sbic is " 1397 "jammed, CSR:%02x,ASR:%02x\n", 1398 csr, asr); 1399 #ifdef DDB 1400 Debugger(); 1401 #endif 1402 /* SBIC is jammed */ 1403 /* DUNNO which direction */ 1404 /* Try old direction */ 1405 GET_SBIC_data(regs,i); 1406 GET_SBIC_asr(regs, asr); 1407 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1408 SET_SBIC_data(regs,i); 1409 } 1410 GET_SBIC_asr(regs, asr); 1411 } 1412 1413 /* 1414 * wait for last command to complete 1415 */ 1416 if (asr & SBIC_ASR_LCI) { 1417 printf("sbicicmd: last command ignored\n"); 1418 } 1419 else if (i == 1) /* Bsy */ 1420 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 1421 1422 /* 1423 * do it again 1424 */ 1425 } while (i > 0 && dev->sc_stat[0] == 0xff); 1426 1427 /* Sometimes we need to do an extra read of the CSR */ 1428 GET_SBIC_csr(regs, csr); 1429 CSR_TRACE('I',csr,asr,0xff); 1430 1431 #if CSR_LOG_BUF_SIZE 1432 if (reselect_debug > 1) 1433 for (i = 0; i < bufptr; i++) 1434 printf("CSR:%02x", csrbuf[i]); 1435 #endif 1436 1437 DBGPRINTF(("sbicicmd done(%d,%d):%d =%d=\n", 1438 dev->target, lun, 1439 acb->datalen, 1440 dev->sc_stat[0]), 1441 data_pointer_debug > 1); 1442 1443 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1444 dev->sc_flags &= ~SBICF_ICMD; 1445 1446 SBIC_TRACE(dev); 1447 return dev->sc_stat[0]; 1448 } 1449 1450 /* 1451 * Finish SCSI xfer command: After the completion interrupt from 1452 * a read/write operation, sequence through the final phases in 1453 * programmed i/o. This routine is a lot like sbicicmd except we 1454 * skip (and don't allow) the select, cmd out and data in/out phases. 1455 */ 1456 static void 1457 sbicxfdone(struct sbic_softc *dev, sbic_regmap_p regs, int target) 1458 { 1459 u_char phase, asr, csr; 1460 int s; 1461 1462 SBIC_TRACE(dev); 1463 QPRINTF(("{")); 1464 s = splbio(); 1465 1466 /* 1467 * have the sbic complete on its own 1468 */ 1469 SBIC_TC_PUT(regs, 0); 1470 SET_SBIC_cmd_phase(regs, 0x46); 1471 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1472 1473 do { 1474 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1475 GET_SBIC_csr (regs, csr); 1476 CSR_TRACE('f',csr,asr,target); 1477 QPRINTF(("%02x:", csr)); 1478 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1479 && (csr != SBIC_CSR_S_XFERRED)); 1480 1481 dev->sc_flags &= ~SBICF_SELECTED; 1482 1483 GET_SBIC_cmd_phase (regs, phase); 1484 QPRINTF(("}%02x", phase)); 1485 if (phase == 0x60) 1486 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1487 else 1488 sbicerror(dev, regs, csr); 1489 1490 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1491 splx(s); 1492 SBIC_TRACE(dev); 1493 } 1494 1495 /* 1496 * No DMA chains 1497 */ 1498 1499 static int 1500 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1501 { 1502 int i, usedma; 1503 /* int dmaflags, count; */ 1504 /* int wait;*/ 1505 /* u_char cmd;*/ 1506 u_char asr = 0, csr = 0; 1507 /* u_char *addr; */ 1508 sbic_regmap_p regs; 1509 struct sbic_acb *acb; 1510 1511 SBIC_TRACE(dev); 1512 dev->target = xs->xs_periph->periph_target; 1513 dev->lun = xs->xs_periph->periph_lun; 1514 acb = dev->sc_nexus; 1515 regs = &dev->sc_sbicp; 1516 1517 usedma = acb->flags & ACB_DMA; 1518 1519 DBG(routine = 1); 1520 DBG(debug_sbic_regs = regs); /* store this to allow debug calls */ 1521 DBGPRINTF(("sbicgo(%d,%d)\n", dev->target, dev->lun), 1522 data_pointer_debug > 1); 1523 1524 /* 1525 * set the sbic into DMA mode 1526 */ 1527 if (usedma) 1528 SET_SBIC_control(regs, 1529 SBIC_CTL_EDI | SBIC_CTL_IDI | dev->sc_dmamode); 1530 else 1531 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1532 1533 1534 /* 1535 * select the SCSI bus (it's an error if bus isn't free) 1536 */ 1537 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1538 dev->sc_scsiaddr)) { 1539 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1540 SBIC_TRACE(dev); 1541 /* Not done: may need to be rescheduled */ 1542 return 0; 1543 } 1544 dev->sc_stat[0] = 0xff; 1545 1546 /* 1547 * Allocate the DMA chain 1548 */ 1549 1550 /* Mark end of segment */ 1551 acb->sc_tcnt = 0; 1552 1553 SBIC_TRACE(dev); 1554 /* Enable interrupts */ 1555 dev->sc_enintr(dev); 1556 if (usedma) { 1557 int tcnt; 1558 1559 acb->offset = 0; 1560 acb->sc_tcnt = 0; 1561 /* Note, this does not start DMA */ 1562 tcnt = dev->sc_dmasetup(dev->sc_dmah, dev->sc_dmat, acb, 1563 (acb->flags & ACB_DATAIN) != 0); 1564 1565 DBG(dev->sc_dmatimo = tcnt ? 1 : 0); 1566 DBG(++sbicdma_ops); /* count total DMA operations */ 1567 } 1568 1569 SBIC_TRACE(dev); 1570 1571 /* 1572 * enintr() also enables interrupts for the sbic 1573 */ 1574 DBG(debug_asr = asr); 1575 DBG(debug_csr = csr); 1576 1577 /* 1578 * Lets cycle a while then let the interrupt handler take over 1579 */ 1580 1581 asr = GET_SBIC_asr(regs, asr); 1582 do { 1583 GET_SBIC_csr(regs, csr); 1584 CSR_TRACE('g', csr, asr, dev->target); 1585 1586 DBG(debug_csr = csr); 1587 DBG(routine = 1); 1588 1589 QPRINTF(("go[0x%x]", csr)); 1590 1591 i = sbicnextstate(dev, csr, asr); 1592 1593 WAIT_CIP(regs); 1594 GET_SBIC_asr(regs, asr); 1595 1596 DBG(debug_asr = asr); 1597 1598 if (asr & SBIC_ASR_LCI) 1599 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1600 } while (i == SBIC_STATE_RUNNING && 1601 (asr & (SBIC_ASR_INT | SBIC_ASR_LCI))); 1602 1603 CSR_TRACE('g',csr,asr,i<<4); 1604 SBIC_TRACE(dev); 1605 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) 1606 printf("sbicgo: done & stat = 0xff\n"); 1607 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1608 /* if (i == SBIC_STATE_DONE && dev->sc_stat[0]) { */ 1609 /* Did we really finish that fast? */ 1610 return 1; 1611 } 1612 return 0; 1613 } 1614 1615 1616 int 1617 sbicintr(struct sbic_softc *dev) 1618 { 1619 sbic_regmap_p regs; 1620 u_char asr, csr; 1621 /* u_char *tmpaddr;*/ 1622 /* struct sbic_acb *acb;*/ 1623 int i; 1624 /* int newtarget, newlun;*/ 1625 /* unsigned tcnt;*/ 1626 1627 regs = &dev->sc_sbicp; 1628 1629 /* 1630 * pending interrupt? 1631 */ 1632 GET_SBIC_asr (regs, asr); 1633 if ((asr & SBIC_ASR_INT) == 0) 1634 return 0; 1635 1636 SBIC_TRACE(dev); 1637 do { 1638 GET_SBIC_csr(regs, csr); 1639 CSR_TRACE('i',csr,asr,dev->target); 1640 1641 DBG(debug_csr = csr); 1642 DBG(routine = 2); 1643 1644 QPRINTF(("intr[0x%x]", csr)); 1645 1646 i = sbicnextstate(dev, csr, asr); 1647 1648 WAIT_CIP(regs); 1649 GET_SBIC_asr(regs, asr); 1650 1651 DBG(debug_asr = asr); 1652 1653 #if 0 1654 if (asr & SBIC_ASR_LCI) 1655 printf("sbicintr: LCI asr:%02x csr:%02x\n", asr, csr); 1656 #endif 1657 } while (i == SBIC_STATE_RUNNING && 1658 (asr & (SBIC_ASR_INT | SBIC_ASR_LCI))); 1659 CSR_TRACE('i', csr, asr, i << 4); 1660 SBIC_TRACE(dev); 1661 return 1; 1662 } 1663 1664 /* 1665 * Run commands and wait for disconnect 1666 */ 1667 static int 1668 sbicpoll(struct sbic_softc *dev) 1669 { 1670 sbic_regmap_p regs; 1671 u_char asr, csr; 1672 /* struct sbic_pending* pendp;*/ 1673 int i; 1674 /* unsigned tcnt;*/ 1675 1676 SBIC_TRACE(dev); 1677 regs = &dev->sc_sbicp; 1678 1679 do { 1680 GET_SBIC_asr (regs, asr); 1681 1682 DBG(debug_asr = asr); 1683 1684 GET_SBIC_csr(regs, csr); 1685 CSR_TRACE('p', csr, asr, dev->target); 1686 1687 DBG(debug_csr = csr); 1688 DBG(routine = 2); 1689 1690 QPRINTF(("poll[0x%x]", csr)); 1691 1692 i = sbicnextstate(dev, csr, asr); 1693 1694 WAIT_CIP(regs); 1695 GET_SBIC_asr(regs, asr); 1696 /* tapes may take a loooong time.. */ 1697 while (asr & SBIC_ASR_BSY){ 1698 if (asr & SBIC_ASR_DBR) { 1699 printf("sbipoll: Waiting while sbic is " 1700 "jammed, CSR:%02x,ASR:%02x\n", 1701 csr, asr); 1702 #ifdef DDB 1703 Debugger(); 1704 #endif 1705 /* SBIC is jammed */ 1706 /* DUNNO which direction */ 1707 /* Try old direction */ 1708 GET_SBIC_data(regs,i); 1709 GET_SBIC_asr(regs, asr); 1710 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1711 SET_SBIC_data(regs,i); 1712 } 1713 GET_SBIC_asr(regs, asr); 1714 } 1715 1716 if (asr & SBIC_ASR_LCI) 1717 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr, csr); 1718 else if (i == 1) /* BSY */ 1719 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1720 } while (i == SBIC_STATE_RUNNING); 1721 CSR_TRACE('p', csr, asr, i << 4); 1722 SBIC_TRACE(dev); 1723 return 1; 1724 } 1725 1726 /* 1727 * Handle a single msgin 1728 */ 1729 1730 static int 1731 sbicmsgin(struct sbic_softc *dev) 1732 { 1733 sbic_regmap_p regs; 1734 int recvlen; 1735 u_char asr, csr, *tmpaddr; 1736 1737 regs = &dev->sc_sbicp; 1738 1739 dev->sc_msg[0] = 0xff; 1740 dev->sc_msg[1] = 0xff; 1741 1742 GET_SBIC_asr(regs, asr); 1743 1744 DBGPRINTF(("sbicmsgin asr=%02x\n", asr), reselect_debug > 1); 1745 1746 sbic_save_ptrs(dev, regs); 1747 1748 GET_SBIC_selid (regs, csr); 1749 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1750 1751 SBIC_TC_PUT(regs, 0); 1752 tmpaddr = dev->sc_msg; 1753 recvlen = 1; 1754 do { 1755 while (recvlen--) { 1756 asr = GET_SBIC_asr(regs, asr); 1757 GET_SBIC_csr(regs, csr); 1758 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1759 csr, asr)); 1760 1761 RECV_BYTE(regs, *tmpaddr); 1762 CSR_TRACE('m', csr, asr, *tmpaddr); 1763 #if 1 1764 /* 1765 * get the command completion interrupt, or we 1766 * can't send a new command (LCI) 1767 */ 1768 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1769 GET_SBIC_csr(regs, csr); 1770 CSR_TRACE('X', csr, asr, dev->target); 1771 #else 1772 WAIT_CIP(regs); 1773 do { 1774 GET_SBIC_asr(regs, asr); 1775 csr = 0xff; 1776 GET_SBIC_csr(regs, csr); 1777 CSR_TRACE('X', csr, asr, dev->target); 1778 if (csr == 0xff) 1779 printf("sbicmsgin waiting: csr %02x " 1780 "asr %02x\n", csr, asr); 1781 } while (csr == 0xff); 1782 #endif 1783 1784 DBGPRINTF(("sbicmsgin: got %02x csr %02x asr %02x\n", 1785 *tmpaddr, csr, asr), reselect_debug > 1); 1786 1787 #if do_parity_check 1788 if (asr & SBIC_ASR_PE) { 1789 printf("Parity error"); 1790 /* This code simply does not work. */ 1791 WAIT_CIP(regs); 1792 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1793 WAIT_CIP(regs); 1794 GET_SBIC_asr(regs, asr); 1795 WAIT_CIP(regs); 1796 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1797 WAIT_CIP(regs); 1798 if (!(asr & SBIC_ASR_LCI)) 1799 /* Target wants to send garbled msg*/ 1800 continue; 1801 printf("--fixing\n"); 1802 /* loop until a msgout phase occurs on 1803 target */ 1804 while ((csr & 0x07) != MESG_OUT_PHASE) { 1805 while ((asr & SBIC_ASR_BSY) && 1806 !(asr & 1807 (SBIC_ASR_DBR | SBIC_ASR_INT))) 1808 GET_SBIC_asr(regs, asr); 1809 if (asr & SBIC_ASR_DBR) 1810 panic("msgin: jammed again!"); 1811 GET_SBIC_csr(regs, csr); 1812 CSR_TRACE('e', csr, asr, dev->target); 1813 if ((csr & 0x07) != MESG_OUT_PHASE) { 1814 sbicnextstate(dev, csr, asr); 1815 sbic_save_ptrs(dev, regs); 1816 } 1817 } 1818 /* Should be msg out by now */ 1819 SEND_BYTE(regs, MSG_PARITY_ERROR); 1820 } 1821 else 1822 #endif 1823 tmpaddr++; 1824 1825 if (recvlen) { 1826 /* Clear ACK */ 1827 WAIT_CIP(regs); 1828 GET_SBIC_asr(regs, asr); 1829 GET_SBIC_csr(regs, csr); 1830 CSR_TRACE('X',csr,asr,dev->target); 1831 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 1832 csr, asr)); 1833 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1834 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1835 } 1836 1837 }; 1838 1839 if (dev->sc_msg[0] == 0xff) { 1840 printf("sbicmsgin: sbic swallowed our message\n"); 1841 break; 1842 } 1843 1844 DBGPRINTF(("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1845 csr, asr, dev->sc_msg[0]), sync_debug); 1846 1847 /* 1848 * test whether this is a reply to our sync 1849 * request 1850 */ 1851 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 1852 QPRINTF(("IFFY")); 1853 /* Got IFFY msg -- ack it */ 1854 } else if (dev->sc_msg[0] == MSG_REJECT 1855 && dev->sc_sync[dev->target].state == SYNC_SENT) { 1856 QPRINTF(("REJECT of SYN")); 1857 1858 DBGPRINTF(("target %d rejected sync, going async\n", 1859 dev->target), sync_debug); 1860 1861 dev->sc_sync[dev->target].period = sbic_min_period; 1862 dev->sc_sync[dev->target].offset = 0; 1863 dev->sc_sync[dev->target].state = SYNC_DONE; 1864 SET_SBIC_syn(regs, 1865 SBIC_SYN(dev->sc_sync[dev->target].offset, 1866 dev->sc_sync[dev->target].period)); 1867 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 1868 QPRINTF(("REJECT")); 1869 /* 1870 * we'll never REJECt a REJECT message.. 1871 */ 1872 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 1873 QPRINTF(("MSG_SAVE_DATA_PTR")); 1874 /* 1875 * don't reject this either. 1876 */ 1877 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 1878 QPRINTF(("DISCONNECT")); 1879 1880 DBGPRINTF(("sbicmsgin: got disconnect msg %s\n", 1881 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""), 1882 reselect_debug > 1 && 1883 dev->sc_msg[0] == MSG_DISCONNECT); 1884 1885 if (dev->sc_flags & SBICF_ICMD) { 1886 /* We're in immediate mode. Prevent 1887 disconnects. */ 1888 /* prepare to reject the message, NACK */ 1889 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1890 WAIT_CIP(regs); 1891 } 1892 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE) { 1893 QPRINTF(("CMD_COMPLETE")); 1894 /* !! KLUDGE ALERT !! quite a few drives don't seem to 1895 * really like the current way of sending the 1896 * sync-handshake together with the ident-message, and 1897 * they react by sending command-complete and 1898 * disconnecting right after returning the valid sync 1899 * handshake. So, all I can do is reselect the drive, 1900 * and hope it won't disconnect again. I don't think 1901 * this is valid behavior, but I can't help fixing a 1902 * problem that apparently exists. 1903 * 1904 * Note: we should not get here on `normal' command 1905 * completion, as that condition is handled by the 1906 * high-level sel&xfer resume command used to walk 1907 * thru status/cc-phase. 1908 */ 1909 1910 DBGPRINTF(("GOT MSG %d! target %d acting weird.." 1911 " waiting for disconnect...\n", 1912 dev->sc_msg[0], dev->target), sync_debug); 1913 1914 /* Check to see if sbic is handling this */ 1915 GET_SBIC_asr(regs, asr); 1916 if (asr & SBIC_ASR_BSY) 1917 return SBIC_STATE_RUNNING; 1918 1919 /* Let's try this: Assume it works and set 1920 status to 00 */ 1921 dev->sc_stat[0] = 0; 1922 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 1923 && tmpaddr == &dev->sc_msg[1]) { 1924 QPRINTF(("ExtMSG\n")); 1925 /* Read in whole extended message */ 1926 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1927 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1928 GET_SBIC_asr(regs, asr); 1929 GET_SBIC_csr(regs, csr); 1930 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 1931 RECV_BYTE(regs, *tmpaddr); 1932 CSR_TRACE('x',csr,asr,*tmpaddr); 1933 /* Wait for command completion IRQ */ 1934 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1935 recvlen = *tmpaddr++; 1936 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 1937 asr, csr, recvlen)); 1938 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && 1939 dev->sc_msg[1] == 3 && 1940 dev->sc_msg[2] == MSG_SYNC_REQ) { 1941 QPRINTF(("SYN")); 1942 dev->sc_sync[dev->target].period = 1943 sbicfromscsiperiod(dev, 1944 regs, dev->sc_msg[3]); 1945 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 1946 dev->sc_sync[dev->target].state = SYNC_DONE; 1947 SET_SBIC_syn(regs, 1948 SBIC_SYN(dev->sc_sync[dev->target].offset, 1949 dev->sc_sync[dev->target].period)); 1950 printf("%s: target %d now synchronous," 1951 " period=%dns, offset=%d.\n", 1952 dev->sc_dev.dv_xname, dev->target, 1953 dev->sc_msg[3] * 4, dev->sc_msg[4]); 1954 } else { 1955 1956 DBGPRINTF(("sbicmsgin: Rejecting message 0x%02x\n", 1957 dev->sc_msg[0]), sbic_debug || sync_debug); 1958 1959 /* prepare to reject the message, NACK */ 1960 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1961 WAIT_CIP(regs); 1962 } 1963 /* Clear ACK */ 1964 WAIT_CIP(regs); 1965 GET_SBIC_asr(regs, asr); 1966 GET_SBIC_csr(regs, csr); 1967 CSR_TRACE('X',csr,asr,dev->target); 1968 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 1969 csr, asr, recvlen)); 1970 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1971 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1972 } 1973 #if 0 1974 while ((csr == SBIC_CSR_MSGIN_W_ACK) || 1975 (SBIC_PHASE(csr) == MESG_IN_PHASE)); 1976 #else 1977 while (recvlen > 0); 1978 #endif 1979 1980 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 1981 1982 /* Should still have one CSR to read */ 1983 return SBIC_STATE_RUNNING; 1984 } 1985 1986 1987 /* 1988 * sbicnextstate() 1989 * return: 1990 * 0 == done 1991 * 1 == working 1992 * 2 == disconnected 1993 * -1 == error 1994 */ 1995 static int 1996 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 1997 { 1998 sbic_regmap_p regs; 1999 struct sbic_acb *acb; 2000 /* int i;*/ 2001 int newtarget, newlun, wait; 2002 /* unsigned tcnt;*/ 2003 2004 SBIC_TRACE(dev); 2005 regs = &dev->sc_sbicp; 2006 acb = dev->sc_nexus; 2007 2008 QPRINTF(("next[%02x,%02x]",asr,csr)); 2009 2010 switch (csr) { 2011 case SBIC_CSR_XFERRED | CMD_PHASE: 2012 case SBIC_CSR_MIS | CMD_PHASE: 2013 case SBIC_CSR_MIS_1 | CMD_PHASE: 2014 case SBIC_CSR_MIS_2 | CMD_PHASE: 2015 sbic_save_ptrs(dev, regs); 2016 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2017 if (sbicxfout(regs, acb->clen, 2018 &acb->cmd, CMD_PHASE)) 2019 goto abort; 2020 break; 2021 2022 case SBIC_CSR_XFERRED | STATUS_PHASE: 2023 case SBIC_CSR_MIS | STATUS_PHASE: 2024 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2025 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2026 /* 2027 * this should be the normal i/o completion case. 2028 * get the status & cmd complete msg then let the 2029 * device driver look at what happened. 2030 */ 2031 sbicxfdone(dev,regs,dev->target); 2032 2033 if (acb->flags & ACB_DMA) { 2034 DBG(dev->sc_dmatimo = 0); 2035 2036 dev->sc_dmafinish(dev->sc_dmah, dev->sc_dmat, acb); 2037 2038 dev->sc_flags &= ~SBICF_INDMA; 2039 } 2040 sbic_scsidone(acb, dev->sc_stat[0]); 2041 SBIC_TRACE(dev); 2042 return SBIC_STATE_DONE; 2043 2044 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2045 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2046 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2047 case SBIC_CSR_MIS | DATA_IN_PHASE: 2048 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2049 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2050 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2051 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2052 { 2053 int i = 0; 2054 2055 if ((acb->xs->xs_control & XS_CTL_POLL) || 2056 (dev->sc_flags & SBICF_ICMD) || 2057 (acb->flags & ACB_DMA) == 0) { 2058 /* Do PIO */ 2059 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2060 if (acb->datalen <= 0) { 2061 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2062 acb->datalen, asr, csr); 2063 goto abort; 2064 } 2065 wait = sbic_data_wait; 2066 if (sbicxfstart(regs, acb->datalen, 2067 SBIC_PHASE(csr), wait)) { 2068 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 2069 /* data in? */ 2070 i = sbicxfin(regs, acb->datalen, 2071 acb->data); 2072 else 2073 i = sbicxfout(regs, acb->datalen, 2074 acb->data, SBIC_PHASE(csr)); 2075 } 2076 acb->data += acb->datalen - i; 2077 acb->datalen = i; 2078 } else { 2079 /* Transfer = using DMA */ 2080 /* 2081 * do scatter-gather dma 2082 * hacking the controller chip, ouch.. 2083 */ 2084 SET_SBIC_control(regs, 2085 SBIC_CTL_EDI | SBIC_CTL_IDI | dev->sc_dmamode); 2086 /* 2087 * set next dma addr and dec count 2088 */ 2089 sbic_save_ptrs(dev, regs); 2090 2091 if (acb->offset >= acb->datalen) { 2092 printf("sbicnextstate:xfer offset %d asr%x csr%x\n", 2093 acb->offset, asr, csr); 2094 goto abort; 2095 } 2096 DBGPRINTF(("next dmanext: %d(offset %d)\n", 2097 dev->target, acb->offset), 2098 data_pointer_debug > 1); 2099 DBG(dev->sc_dmatimo = 1); 2100 2101 acb->sc_tcnt = 2102 dev->sc_dmanext(dev->sc_dmah, dev->sc_dmat, 2103 acb, acb->offset); 2104 DBGPRINTF(("dmanext transfering %ld bytes\n", 2105 acb->sc_tcnt), data_pointer_debug); 2106 SBIC_TC_PUT(regs, (unsigned)acb->sc_tcnt); 2107 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2108 dev->sc_flags |= SBICF_INDMA; 2109 } 2110 break; 2111 } 2112 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2113 case SBIC_CSR_MIS | MESG_IN_PHASE: 2114 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2115 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2116 SBIC_TRACE(dev); 2117 return sbicmsgin(dev); 2118 2119 case SBIC_CSR_MSGIN_W_ACK: 2120 /* Dunno what I'm ACKing */ 2121 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2122 printf("Acking unknown msgin CSR:%02x",csr); 2123 break; 2124 2125 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2126 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2127 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2128 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2129 2130 DBGPRINTF(("sending REJECT msg to last msg.\n"), sync_debug); 2131 2132 sbic_save_ptrs(dev, regs); 2133 /* 2134 * Should only get here on reject, since it's always 2135 * US that initiate a sync transfer. 2136 */ 2137 SEND_BYTE(regs, MSG_REJECT); 2138 WAIT_CIP(regs); 2139 if (asr & (SBIC_ASR_BSY | SBIC_ASR_LCI | SBIC_ASR_CIP)) 2140 printf("next: REJECT sent asr %02x\n", asr); 2141 SBIC_TRACE(dev); 2142 return SBIC_STATE_RUNNING; 2143 2144 case SBIC_CSR_DISC: 2145 case SBIC_CSR_DISC_1: 2146 dev->sc_flags &= ~(SBICF_INDMA | SBICF_SELECTED); 2147 2148 /* Try to schedule another target */ 2149 DBGPRINTF(("sbicnext target %d disconnected\n", dev->target), 2150 reselect_debug > 1); 2151 2152 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2153 ++dev->sc_tinfo[dev->target].dconns; 2154 dev->sc_nexus = NULL; 2155 2156 if ((acb->xs->xs_control & XS_CTL_POLL) 2157 || (dev->sc_flags & SBICF_ICMD) 2158 || (!sbic_parallel_operations)) { 2159 SBIC_TRACE(dev); 2160 return SBIC_STATE_DISCONNECT; 2161 } 2162 sbic_sched(dev); 2163 SBIC_TRACE(dev); 2164 return SBIC_STATE_DISCONNECT; 2165 2166 case SBIC_CSR_RSLT_NI: 2167 case SBIC_CSR_RSLT_IFY: 2168 GET_SBIC_rselid(regs, newtarget); 2169 /* check SBIC_RID_SIV? */ 2170 newtarget &= SBIC_RID_MASK; 2171 if (csr == SBIC_CSR_RSLT_IFY) { 2172 /* Read IFY msg to avoid lockup */ 2173 GET_SBIC_data(regs, newlun); 2174 WAIT_CIP(regs); 2175 newlun &= SBIC_TLUN_MASK; 2176 CSR_TRACE('r',csr,asr,newtarget); 2177 } else { 2178 /* Need to get IFY message */ 2179 for (newlun = 256; newlun; --newlun) { 2180 GET_SBIC_asr(regs, asr); 2181 if (asr & SBIC_ASR_INT) 2182 break; 2183 delay(1); 2184 } 2185 newlun = 0; /* XXXX */ 2186 if ((asr & SBIC_ASR_INT) == 0) { 2187 2188 DBGPRINTF(("RSLT_NI - no IFFY message? asr %x\n", 2189 asr), reselect_debug); 2190 2191 } else { 2192 GET_SBIC_csr(regs,csr); 2193 CSR_TRACE('n',csr,asr,newtarget); 2194 if ((csr == (SBIC_CSR_MIS | MESG_IN_PHASE)) || 2195 (csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE)) || 2196 (csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE))) { 2197 sbicmsgin(dev); 2198 newlun = dev->sc_msg[0] & 7; 2199 } else { 2200 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2201 csr); 2202 } 2203 } 2204 } 2205 2206 DBGPRINTF(("sbicnext: reselect %s from targ %d lun %d\n", 2207 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2208 newtarget, newlun), 2209 reselect_debug > 1 || 2210 (reselect_debug && csr == SBIC_CSR_RSLT_NI)); 2211 2212 if (dev->sc_nexus) { 2213 DBGPRINTF(("%s: reselect %s with active command\n", 2214 dev->sc_dev.dv_xname, 2215 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"), 2216 reselect_debug > 1); 2217 #if defined(DDB) && defined (DEBUG) 2218 /* Debugger();*/ 2219 #endif 2220 2221 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, 2222 chain); 2223 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2224 dev->sc_nexus = NULL; 2225 } 2226 /* Reload sync values for this target */ 2227 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2228 SET_SBIC_syn(regs, 2229 SBIC_SYN(dev->sc_sync[newtarget].offset, 2230 dev->sc_sync[newtarget].period)); 2231 else 2232 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2233 for (acb = dev->nexus_list.tqh_first; acb; 2234 acb = acb->chain.tqe_next) { 2235 if (acb->xs->xs_periph->periph_target != newtarget || 2236 acb->xs->xs_periph->periph_lun != newlun) 2237 continue; 2238 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2239 dev->sc_nexus = acb; 2240 dev->sc_flags |= SBICF_SELECTED; 2241 dev->target = newtarget; 2242 dev->lun = newlun; 2243 break; 2244 } 2245 if (acb == NULL) { 2246 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2247 dev->sc_dev.dv_xname, 2248 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2249 &dev->nexus_list.tqh_first); 2250 panic("bad reselect in sbic"); 2251 } 2252 if (csr == SBIC_CSR_RSLT_IFY) 2253 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2254 break; 2255 2256 default: 2257 abort: 2258 /* 2259 * Something unexpected happened -- deal with it. 2260 */ 2261 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, 2262 asr); 2263 #ifdef DDB 2264 Debugger(); 2265 #endif 2266 DBG(dev->sc_dmatimo = 0); 2267 2268 if (dev->sc_flags & SBICF_INDMA) { 2269 dev->sc_dmafinish(dev->sc_dmah, dev->sc_dmat, acb); 2270 dev->sc_flags &= ~SBICF_INDMA; 2271 DBG(dev->sc_dmatimo = 0); 2272 } 2273 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2274 sbicerror(dev, regs, csr); 2275 sbicabort(dev, regs, "next"); 2276 sbic_scsidone(acb, -1); 2277 SBIC_TRACE(dev); 2278 return SBIC_STATE_ERROR; 2279 } 2280 2281 SBIC_TRACE(dev); 2282 return SBIC_STATE_RUNNING; 2283 } 2284 2285 static int 2286 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_p regs, int a) 2287 { 2288 unsigned int fs; 2289 2290 /* 2291 * cycle = DIV / (2*CLK) 2292 * DIV = FS+2 2293 * best we can do is 200ns at 20Mhz, 2 cycles 2294 */ 2295 2296 GET_SBIC_myid(regs,fs); 2297 fs = (fs >> 6) + 2; /* DIV */ 2298 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2299 if (a < 2) 2300 a = 8; /* map to Cycles */ 2301 return (fs * a) >> 2; /* in 4 ns units */ 2302 } 2303 2304 static int 2305 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_p regs, int p) 2306 { 2307 register unsigned int fs, ret; 2308 2309 /* Just the inverse of the above */ 2310 2311 GET_SBIC_myid(regs, fs); 2312 fs = (fs >> 6) + 2; /* DIV */ 2313 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2314 2315 ret = p << 2; /* in ns units */ 2316 ret = ret / fs; /* in Cycles */ 2317 if (ret < sbic_min_period) 2318 return sbic_min_period; 2319 2320 /* verify rounding */ 2321 if (sbictoscsiperiod(dev, regs, ret) < p) 2322 ret++; 2323 return (ret >= 8) ? 0 : ret; 2324 } 2325 2326 #ifdef DEBUG 2327 2328 void 2329 sbicdumpstate() 2330 { 2331 u_char csr, asr; 2332 2333 GET_SBIC_asr(debug_sbic_regs,asr); 2334 GET_SBIC_csr(debug_sbic_regs,csr); 2335 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2336 (routine == 1) ? "sbicgo" : 2337 (routine == 2) ? "sbicintr" : 2338 (routine == 3) ? "sbicicmd" : 2339 (routine == 4) ? "sbicnext" : "unknown", 2340 debug_asr, debug_csr, asr, csr); 2341 2342 } 2343 2344 void 2345 sbictimeout(struct sbic_softc *dev) 2346 { 2347 int s, asr; 2348 2349 s = splbio(); 2350 if (dev->sc_dmatimo) { 2351 if (dev->sc_dmatimo > 1) { 2352 printf("%s: dma timeout #%d\n", 2353 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2354 GET_SBIC_asr(&dev->sc_sbicp, asr); 2355 if (asr & SBIC_ASR_INT) { 2356 /* We need to service a missed IRQ */ 2357 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2358 debug_asr, debug_csr, asr); 2359 sbicintr(dev); 2360 } 2361 sbicdumpstate(); 2362 } 2363 dev->sc_dmatimo++; 2364 } 2365 splx(s); 2366 callout_reset(&dev->sc_timo_ch, 30 * hz, 2367 (void *)sbictimeout, dev); 2368 } 2369 2370 void 2371 sbic_dump_acb(struct sbic_acb *acb) 2372 { 2373 u_char *b = (u_char *) &acb->cmd; 2374 int i; 2375 2376 printf("acb@%p ", acb); 2377 if (acb->xs == NULL) { 2378 printf("<unused>\n"); 2379 return; 2380 } 2381 printf("(%d:%d) flags %2x clen %2d cmd ", 2382 acb->xs->xs_periph->periph_target, 2383 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2384 for (i = acb->clen; i; --i) 2385 printf(" %02x", *b++); 2386 printf("\n"); 2387 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2388 acb->xs->datalen); 2389 printf("tcnt %lx\n", acb->sc_tcnt); 2390 } 2391 2392 void 2393 sbic_dump(struct sbic_softc *dev) 2394 { 2395 sbic_regmap_p regs; 2396 u_char csr, asr; 2397 struct sbic_acb *acb; 2398 int s; 2399 int i; 2400 2401 s = splbio(); 2402 regs = &dev->sc_sbicp; 2403 #if CSR_TRACE_SIZE 2404 printf("csr trace: "); 2405 i = csr_traceptr; 2406 do { 2407 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2408 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2409 switch(csr_trace[i].whr) { 2410 case 'g': 2411 printf("go "); break; 2412 case 's': 2413 printf("select "); break; 2414 case 'y': 2415 printf("select+ "); break; 2416 case 'i': 2417 printf("intr "); break; 2418 case 'f': 2419 printf("finish "); break; 2420 case '>': 2421 printf("out "); break; 2422 case '<': 2423 printf("in "); break; 2424 case 'm': 2425 printf("msgin "); break; 2426 case 'x': 2427 printf("msginx "); break; 2428 case 'X': 2429 printf("msginX "); break; 2430 case 'r': 2431 printf("reselect "); break; 2432 case 'I': 2433 printf("icmd "); break; 2434 case 'a': 2435 printf("abort "); break; 2436 default: 2437 printf("? "); 2438 } 2439 switch(csr_trace[i].csr) { 2440 case 0x11: 2441 printf("INITIATOR"); break; 2442 case 0x16: 2443 printf("S_XFERRED"); break; 2444 case 0x20: 2445 printf("MSGIN_ACK"); break; 2446 case 0x41: 2447 printf("DISC"); break; 2448 case 0x42: 2449 printf("SEL_TIMEO"); break; 2450 case 0x80: 2451 printf("RSLT_NI"); break; 2452 case 0x81: 2453 printf("RSLT_IFY"); break; 2454 case 0x85: 2455 printf("DISC_1"); break; 2456 case 0x18: case 0x19: case 0x1a: 2457 case 0x1b: case 0x1e: case 0x1f: 2458 case 0x28: case 0x29: case 0x2a: 2459 case 0x2b: case 0x2e: case 0x2f: 2460 case 0x48: case 0x49: case 0x4a: 2461 case 0x4b: case 0x4e: case 0x4f: 2462 case 0x88: case 0x89: case 0x8a: 2463 case 0x8b: case 0x8e: case 0x8f: 2464 switch(csr_trace[i].csr & 0xf0) { 2465 case 0x10: 2466 printf("DONE_"); break; 2467 case 0x20: 2468 printf("STOP_"); break; 2469 case 0x40: 2470 printf("ERR_"); break; 2471 case 0x80: 2472 printf("REQ_"); break; 2473 } 2474 switch(csr_trace[i].csr & 7) { 2475 case 0: 2476 printf("DATA_OUT"); break; 2477 case 1: 2478 printf("DATA_IN"); break; 2479 case 2: 2480 printf("CMD"); break; 2481 case 3: 2482 printf("STATUS"); break; 2483 case 6: 2484 printf("MSG_OUT"); break; 2485 case 7: 2486 printf("MSG_IN"); break; 2487 default: 2488 printf("invld phs"); 2489 } 2490 break; 2491 default: printf("****"); break; 2492 } 2493 if (csr_trace[i].asr & SBIC_ASR_INT) 2494 printf(" ASR_INT"); 2495 if (csr_trace[i].asr & SBIC_ASR_LCI) 2496 printf(" ASR_LCI"); 2497 if (csr_trace[i].asr & SBIC_ASR_BSY) 2498 printf(" ASR_BSY"); 2499 if (csr_trace[i].asr & SBIC_ASR_CIP) 2500 printf(" ASR_CIP"); 2501 printf("\n"); 2502 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2503 } while (i != csr_traceptr); 2504 #endif 2505 GET_SBIC_asr(regs, asr); 2506 if ((asr & SBIC_ASR_INT) == 0) 2507 GET_SBIC_csr(regs, csr); 2508 else 2509 csr = 0; 2510 printf("%s@%p regs %p asr %x csr %x\n", dev->sc_dev.dv_xname, 2511 dev, regs, asr, csr); 2512 if ((acb = dev->free_list.tqh_first)) { 2513 printf("Free list:\n"); 2514 while (acb) { 2515 sbic_dump_acb(acb); 2516 acb = acb->chain.tqe_next; 2517 } 2518 } 2519 if ((acb = dev->ready_list.tqh_first)) { 2520 printf("Ready list:\n"); 2521 while (acb) { 2522 sbic_dump_acb(acb); 2523 acb = acb->chain.tqe_next; 2524 } 2525 } 2526 if ((acb = dev->nexus_list.tqh_first)) { 2527 printf("Nexus list:\n"); 2528 while (acb) { 2529 sbic_dump_acb(acb); 2530 acb = acb->chain.tqe_next; 2531 } 2532 } 2533 if (dev->sc_nexus) { 2534 printf("nexus:\n"); 2535 sbic_dump_acb(dev->sc_nexus); 2536 } 2537 printf("targ %d lun %d flags %x\n", 2538 dev->target, dev->lun, dev->sc_flags); 2539 for (i = 0; i < 8; ++i) { 2540 if (dev->sc_tinfo[i].cmds > 2) { 2541 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2542 i, dev->sc_tinfo[i].cmds, 2543 dev->sc_tinfo[i].dconns, 2544 dev->sc_tinfo[i].lubusy); 2545 } 2546 } 2547 splx(s); 2548 } 2549 2550 #endif 2551
Indexes created Tue Sep 30 17:09:57 GMT 2025