sbicreg.h revision 1.1.4.2
1 1.1.4.2 reinoud /* $NetBSD: sbicreg.h,v 1.1.4.2 2001/10/05 22:27:59 reinoud Exp $ */ 2 1.1.4.2 reinoud 3 1.1.4.2 reinoud /* 4 1.1.4.2 reinoud * Copyright (c) 1990 The Regents of the University of California. 5 1.1.4.2 reinoud * All rights reserved. 6 1.1.4.2 reinoud * 7 1.1.4.2 reinoud * This code is derived from software contributed to Berkeley by 8 1.1.4.2 reinoud * Van Jacobson of Lawrence Berkeley Laboratory. 9 1.1.4.2 reinoud * 10 1.1.4.2 reinoud * Redistribution and use in source and binary forms, with or without 11 1.1.4.2 reinoud * modification, are permitted provided that the following conditions 12 1.1.4.2 reinoud * are met: 13 1.1.4.2 reinoud * 1. Redistributions of source code must retain the above copyright 14 1.1.4.2 reinoud * notice, this list of conditions and the following disclaimer. 15 1.1.4.2 reinoud * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.4.2 reinoud * notice, this list of conditions and the following disclaimer in the 17 1.1.4.2 reinoud * documentation and/or other materials provided with the distribution. 18 1.1.4.2 reinoud * 3. All advertising materials mentioning features or use of this software 19 1.1.4.2 reinoud * must display the following acknowledgement: 20 1.1.4.2 reinoud * This product includes software developed by the University of 21 1.1.4.2 reinoud * California, Berkeley and its contributors. 22 1.1.4.2 reinoud * 4. Neither the name of the University nor the names of its contributors 23 1.1.4.2 reinoud * may be used to endorse or promote products derived from this software 24 1.1.4.2 reinoud * without specific prior written permission. 25 1.1.4.2 reinoud * 26 1.1.4.2 reinoud * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 1.1.4.2 reinoud * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 1.1.4.2 reinoud * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 1.1.4.2 reinoud * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 1.1.4.2 reinoud * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 1.1.4.2 reinoud * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 1.1.4.2 reinoud * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 1.1.4.2 reinoud * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 1.1.4.2 reinoud * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 1.1.4.2 reinoud * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 1.1.4.2 reinoud * SUCH DAMAGE. 37 1.1.4.2 reinoud * 38 1.1.4.2 reinoud * @(#)scsireg.h 7.3 (Berkeley) 2/5/91 39 1.1.4.2 reinoud */ 40 1.1.4.2 reinoud 41 1.1.4.2 reinoud /* 42 1.1.4.2 reinoud * AMD AM33C93A SCSI interface hardware description. 43 1.1.4.2 reinoud * 44 1.1.4.2 reinoud * Using parts of the Mach scsi driver for the 33C93 45 1.1.4.2 reinoud */ 46 1.1.4.2 reinoud 47 1.1.4.2 reinoud #define SBIC_myid 0 48 1.1.4.2 reinoud #define SBIC_cdbsize 0 49 1.1.4.2 reinoud #define SBIC_control 1 50 1.1.4.2 reinoud #define SBIC_timeo 2 51 1.1.4.2 reinoud #define SBIC_cdb1 3 52 1.1.4.2 reinoud #define SBIC_tsecs 3 53 1.1.4.2 reinoud #define SBIC_cdb2 4 54 1.1.4.2 reinoud #define SBIC_theads 4 55 1.1.4.2 reinoud #define SBIC_cdb3 5 56 1.1.4.2 reinoud #define SBIC_tcyl_hi 5 57 1.1.4.2 reinoud #define SBIC_cdb4 6 58 1.1.4.2 reinoud #define SBIC_tcyl_lo 6 59 1.1.4.2 reinoud #define SBIC_cdb5 7 60 1.1.4.2 reinoud #define SBIC_addr_hi 7 61 1.1.4.2 reinoud #define SBIC_cdb6 8 62 1.1.4.2 reinoud #define SBIC_addr_2 8 63 1.1.4.2 reinoud #define SBIC_cdb7 9 64 1.1.4.2 reinoud #define SBIC_addr_3 9 65 1.1.4.2 reinoud #define SBIC_cdb8 10 66 1.1.4.2 reinoud #define SBIC_addr_lo 10 67 1.1.4.2 reinoud #define SBIC_cdb9 11 68 1.1.4.2 reinoud #define SBIC_secno 11 69 1.1.4.2 reinoud #define SBIC_cdb10 12 70 1.1.4.2 reinoud #define SBIC_headno 12 71 1.1.4.2 reinoud #define SBIC_cdb11 13 72 1.1.4.2 reinoud #define SBIC_cylno_hi 13 73 1.1.4.2 reinoud #define SBIC_cdb12 14 74 1.1.4.2 reinoud #define SBIC_cylno_lo 14 75 1.1.4.2 reinoud #define SBIC_tlun 15 76 1.1.4.2 reinoud #define SBIC_cmd_phase 16 77 1.1.4.2 reinoud #define SBIC_syn 17 78 1.1.4.2 reinoud #define SBIC_count_hi 18 79 1.1.4.2 reinoud #define SBIC_count_med 19 80 1.1.4.2 reinoud #define SBIC_count_lo 20 81 1.1.4.2 reinoud #define SBIC_selid 21 82 1.1.4.2 reinoud #define SBIC_rselid 22 83 1.1.4.2 reinoud #define SBIC_csr 23 84 1.1.4.2 reinoud #define SBIC_cmd 24 85 1.1.4.2 reinoud #define SBIC_data 25 86 1.1.4.2 reinoud /* sbic_asr is addressed directly */ 87 1.1.4.2 reinoud 88 1.1.4.2 reinoud /* 89 1.1.4.2 reinoud * Register defines 90 1.1.4.2 reinoud */ 91 1.1.4.2 reinoud 92 1.1.4.2 reinoud /* 93 1.1.4.2 reinoud * Auxiliary Status Register 94 1.1.4.2 reinoud */ 95 1.1.4.2 reinoud 96 1.1.4.2 reinoud #define SBIC_ASR_INT 0x80 /* Interrupt pending */ 97 1.1.4.2 reinoud #define SBIC_ASR_LCI 0x40 /* Last command ignored */ 98 1.1.4.2 reinoud #define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ 99 1.1.4.2 reinoud #define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ 100 1.1.4.2 reinoud #define SBIC_ASR_xxx 0x0c 101 1.1.4.2 reinoud #define SBIC_ASR_PE 0x02 /* Parity error (even) */ 102 1.1.4.2 reinoud #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ 103 1.1.4.2 reinoud 104 1.1.4.2 reinoud /* 105 1.1.4.2 reinoud * My ID register, and/or CDB Size 106 1.1.4.2 reinoud */ 107 1.1.4.2 reinoud 108 1.1.4.2 reinoud #define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */ 109 1.1.4.2 reinoud /* 11 Mhz is invalid */ 110 1.1.4.2 reinoud #define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */ 111 1.1.4.2 reinoud #define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */ 112 1.1.4.2 reinoud #define SBIC_ID_EHP 0x10 /* Enable host parity */ 113 1.1.4.2 reinoud #define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ 114 1.1.4.2 reinoud #define SBIC_ID_MASK 0x07 115 1.1.4.2 reinoud #define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ 116 1.1.4.2 reinoud 117 1.1.4.2 reinoud /* 118 1.1.4.2 reinoud * Control register 119 1.1.4.2 reinoud */ 120 1.1.4.2 reinoud 121 1.1.4.2 reinoud #define SBIC_CTL_DMA 0x80 /* Single byte dma */ 122 1.1.4.2 reinoud #define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/ 123 1.1.4.2 reinoud #define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ 124 1.1.4.2 reinoud #define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ 125 1.1.4.2 reinoud #define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ 126 1.1.4.2 reinoud #define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ 127 1.1.4.2 reinoud #define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ 128 1.1.4.2 reinoud #define SBIC_CTL_HA 0x02 /* Halt on ATN */ 129 1.1.4.2 reinoud #define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */ 130 1.1.4.2 reinoud 131 1.1.4.2 reinoud /* 132 1.1.4.2 reinoud * Timeout period register 133 1.1.4.2 reinoud * [val in msecs, input clk in 0.1 Mhz] 134 1.1.4.2 reinoud */ 135 1.1.4.2 reinoud 136 1.1.4.2 reinoud #define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1) 137 1.1.4.2 reinoud 138 1.1.4.2 reinoud /* 139 1.1.4.2 reinoud * CDBn registers, note that 140 1.1.4.2 reinoud * cdb11 is used for status byte in target mode (send-status-and-cc) 141 1.1.4.2 reinoud * cdb12 sez if linked command complete, and w/flag if so 142 1.1.4.2 reinoud */ 143 1.1.4.2 reinoud 144 1.1.4.2 reinoud /* 145 1.1.4.2 reinoud * Target LUN register 146 1.1.4.2 reinoud * [holds target status when select-and-xfer] 147 1.1.4.2 reinoud */ 148 1.1.4.2 reinoud 149 1.1.4.2 reinoud #define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */ 150 1.1.4.2 reinoud #define SBIC_TLUN_DOK 0x40 /* Disconnect OK */ 151 1.1.4.2 reinoud #define SBIC_TLUN_xxx 0x38 152 1.1.4.2 reinoud #define SBIC_TLUN_MASK 0x07 153 1.1.4.2 reinoud 154 1.1.4.2 reinoud /* 155 1.1.4.2 reinoud * Command Phase register 156 1.1.4.2 reinoud */ 157 1.1.4.2 reinoud 158 1.1.4.2 reinoud #define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */ 159 1.1.4.2 reinoud #define SBIC_CPH(p) ((p) & SBIC_CPH_MASK) 160 1.1.4.2 reinoud 161 1.1.4.2 reinoud /* 162 1.1.4.2 reinoud * FIFO register 163 1.1.4.2 reinoud */ 164 1.1.4.2 reinoud 165 1.1.4.2 reinoud #define SBIC_FIFO_DEEP 12 166 1.1.4.2 reinoud 167 1.1.4.2 reinoud /* 168 1.1.4.2 reinoud * maximum possible size in TC registers. Since this is 24 bit, it's easy 169 1.1.4.2 reinoud */ 170 1.1.4.2 reinoud #define SBIC_TC_MAX ((1 << 24) - 1) 171 1.1.4.2 reinoud 172 1.1.4.2 reinoud /* 173 1.1.4.2 reinoud * Synchronous xfer register 174 1.1.4.2 reinoud */ 175 1.1.4.2 reinoud 176 1.1.4.2 reinoud #define SBIC_SYN_OFF_MASK 0x0f 177 1.1.4.2 reinoud #define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP 178 1.1.4.2 reinoud #define SBIC_SYN_PER_MASK 0x70 179 1.1.4.2 reinoud #define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */ 180 1.1.4.2 reinoud 181 1.1.4.2 reinoud #define SBIC_SYN(o,p) \ 182 1.1.4.2 reinoud (((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK)) 183 1.1.4.2 reinoud 184 1.1.4.2 reinoud /* 185 1.1.4.2 reinoud * Transfer count register 186 1.1.4.2 reinoud * optimal access macros depend on addressing 187 1.1.4.2 reinoud */ 188 1.1.4.2 reinoud 189 1.1.4.2 reinoud /* 190 1.1.4.2 reinoud * Destination ID (selid) register 191 1.1.4.2 reinoud */ 192 1.1.4.2 reinoud 193 1.1.4.2 reinoud #define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */ 194 1.1.4.2 reinoud #define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */ 195 1.1.4.2 reinoud #define SBIC_SID_FROM_SCSI 0x40 196 1.1.4.2 reinoud #define SBIC_SID_TO_SCSI 0x00 197 1.1.4.2 reinoud #define SBIC_SID_xxx 0x38 198 1.1.4.2 reinoud #define SBIC_SID_IDMASK 0x07 199 1.1.4.2 reinoud 200 1.1.4.2 reinoud /* 201 1.1.4.2 reinoud * Source ID (rselid) register 202 1.1.4.2 reinoud */ 203 1.1.4.2 reinoud 204 1.1.4.2 reinoud #define SBIC_RID_ER 0x80 /* Enable reselection */ 205 1.1.4.2 reinoud #define SBIC_RID_ES 0x40 /* Enable selection */ 206 1.1.4.2 reinoud #define SBIC_RID_DSP 0x20 /* Disable select parity */ 207 1.1.4.2 reinoud #define SBIC_RID_SIV 0x08 /* Source ID valid */ 208 1.1.4.2 reinoud #define SBIC_RID_MASK 0x07 209 1.1.4.2 reinoud 210 1.1.4.2 reinoud /* 211 1.1.4.2 reinoud * Status register 212 1.1.4.2 reinoud */ 213 1.1.4.2 reinoud 214 1.1.4.2 reinoud #define SBIC_CSR_CAUSE 0xf0 215 1.1.4.2 reinoud #define SBIC_CSR_RESET 0x00 /* chip was reset */ 216 1.1.4.2 reinoud #define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */ 217 1.1.4.2 reinoud #define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/ 218 1.1.4.2 reinoud #define SBIC_CSR_CMD_ERR 0x40 /* end with error */ 219 1.1.4.2 reinoud #define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */ 220 1.1.4.2 reinoud 221 1.1.4.2 reinoud 222 1.1.4.2 reinoud #define SBIC_CSR_QUALIFIER 0x0f 223 1.1.4.2 reinoud /* Reset State Interrupts */ 224 1.1.4.2 reinoud #define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/ 225 1.1.4.2 reinoud #define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/ 226 1.1.4.2 reinoud /* Successful Completion Interrupts */ 227 1.1.4.2 reinoud #define SBIC_CSR_TARGET 0x10 /* reselect complete */ 228 1.1.4.2 reinoud #define SBIC_CSR_INITIATOR 0x11 /* select complete */ 229 1.1.4.2 reinoud #define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */ 230 1.1.4.2 reinoud #define SBIC_CSR_W_ATN 0x14 /* ditto */ 231 1.1.4.2 reinoud #define SBIC_CSR_XLATED 0x15 /* translate address cmd */ 232 1.1.4.2 reinoud #define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/ 233 1.1.4.2 reinoud #define SBIC_CSR_XFERRED 0x18 /* phase in low bits */ 234 1.1.4.2 reinoud /* Paused or Aborted Interrupts */ 235 1.1.4.2 reinoud #define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/ 236 1.1.4.2 reinoud #define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */ 237 1.1.4.2 reinoud #define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */ 238 1.1.4.2 reinoud #define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */ 239 1.1.4.2 reinoud #define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */ 240 1.1.4.2 reinoud #define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */ 241 1.1.4.2 reinoud #define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */ 242 1.1.4.2 reinoud /* Terminated Interrupts */ 243 1.1.4.2 reinoud #define SBIC_CSR_CMD_INVALID 0x40 244 1.1.4.2 reinoud #define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */ 245 1.1.4.2 reinoud #define SBIC_CSR_SEL_TIMEO 0x42 246 1.1.4.2 reinoud #define SBIC_CSR_PE 0x43 /* parity error */ 247 1.1.4.2 reinoud #define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */ 248 1.1.4.2 reinoud #define SBIC_CSR_XLATE_TOOBIG 0x45 249 1.1.4.2 reinoud #define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */ 250 1.1.4.2 reinoud #define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */ 251 1.1.4.2 reinoud #define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */ 252 1.1.4.2 reinoud /* Service Required Interrupts */ 253 1.1.4.2 reinoud #define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */ 254 1.1.4.2 reinoud #define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */ 255 1.1.4.2 reinoud #define SBIC_CSR_SLT 0x82 /* selected, no ATN */ 256 1.1.4.2 reinoud #define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */ 257 1.1.4.2 reinoud #define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */ 258 1.1.4.2 reinoud #define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */ 259 1.1.4.2 reinoud #define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */ 260 1.1.4.2 reinoud #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */ 261 1.1.4.2 reinoud 262 1.1.4.2 reinoud #define SBIC_PHASE(csr) ((csr) & PHASE_MASK) 263 1.1.4.2 reinoud 264 1.1.4.2 reinoud /* 265 1.1.4.2 reinoud * Command register (command codes) 266 1.1.4.2 reinoud */ 267 1.1.4.2 reinoud 268 1.1.4.2 reinoud #define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */ 269 1.1.4.2 reinoud #define SBIC_CMD_MASK 0x7f 270 1.1.4.2 reinoud 271 1.1.4.2 reinoud /* Miscellaneous */ 272 1.1.4.2 reinoud #define SBIC_CMD_RESET 0x00 /* (DTI) lev I */ 273 1.1.4.2 reinoud #define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */ 274 1.1.4.2 reinoud #define SBIC_CMD_DISC 0x04 /* ( TI) lev I */ 275 1.1.4.2 reinoud #define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */ 276 1.1.4.2 reinoud #define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */ 277 1.1.4.2 reinoud #define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */ 278 1.1.4.2 reinoud 279 1.1.4.2 reinoud /* Initiator state */ 280 1.1.4.2 reinoud #define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */ 281 1.1.4.2 reinoud #define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */ 282 1.1.4.2 reinoud #define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */ 283 1.1.4.2 reinoud #define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */ 284 1.1.4.2 reinoud 285 1.1.4.2 reinoud /* Target state */ 286 1.1.4.2 reinoud #define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */ 287 1.1.4.2 reinoud #define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */ 288 1.1.4.2 reinoud #define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */ 289 1.1.4.2 reinoud #define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */ 290 1.1.4.2 reinoud #define SBIC_CMD_RCV 0x13 /* ( T ) lev II */ 291 1.1.4.2 reinoud #define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */ 292 1.1.4.2 reinoud #define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */ 293 1.1.4.2 reinoud #define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */ 294 1.1.4.2 reinoud #define SBIC_CMD_SND 0x17 /* ( T ) lev II */ 295 1.1.4.2 reinoud 296 1.1.4.2 reinoud /* Disconnected state */ 297 1.1.4.2 reinoud #define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */ 298 1.1.4.2 reinoud #define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */ 299 1.1.4.2 reinoud #define SBIC_CMD_SEL 0x07 /* (D ) lev II */ 300 1.1.4.2 reinoud #define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */ 301 1.1.4.2 reinoud #define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */ 302 1.1.4.2 reinoud #define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */ 303 1.1.4.2 reinoud #define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */ 304 1.1.4.2 reinoud #define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */ 305 1.1.4.2 reinoud 306 1.1.4.2 reinoud /* approximate, but we won't do SBT on selects */ 307 1.1.4.2 reinoud #define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa)) 308 1.1.4.2 reinoud 309 1.1.4.2 reinoud #define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA 310 1.1.4.2 reinoud 311 1.1.4.2 reinoud typedef struct { 312 1.1.4.2 reinoud bus_space_tag_t sc_sbiciot; 313 1.1.4.2 reinoud bus_space_handle_t sc_sbicioh; 314 1.1.4.2 reinoud } sbic_regmap, *sbic_regmap_p; 315 1.1.4.2 reinoud 316 1.1.4.2 reinoud #define SBIC_ASR 0 317 1.1.4.2 reinoud #define SBIC_ADDR 0 318 1.1.4.2 reinoud #define SBIC_VAL 1 319 1.1.4.2 reinoud 320 1.1.4.2 reinoud #define sbic_read_reg(regs,regno,val) do { \ 321 1.1.4.2 reinoud bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 322 1.1.4.2 reinoud (regno)); \ 323 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 324 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); \ 325 1.1.4.2 reinoud (val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \ 326 1.1.4.2 reinoud SBIC_VAL); \ 327 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 328 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_READ); \ 329 1.1.4.2 reinoud } while (0) 330 1.1.4.2 reinoud 331 1.1.4.2 reinoud #define sbic_write_reg(regs,regno,val) do { \ 332 1.1.4.2 reinoud bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 333 1.1.4.2 reinoud (regno)); \ 334 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 335 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE); \ 336 1.1.4.2 reinoud bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \ 337 1.1.4.2 reinoud (val)); \ 338 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 339 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE); \ 340 1.1.4.2 reinoud } while (0) 341 1.1.4.2 reinoud 342 1.1.4.2 reinoud #define SET_SBIC_myid(regs,val) sbic_write_reg(regs,SBIC_myid,val) 343 1.1.4.2 reinoud #define GET_SBIC_myid(regs,val) sbic_read_reg(regs,SBIC_myid,val) 344 1.1.4.2 reinoud #define SET_SBIC_cdbsize(regs,val) sbic_write_reg(regs,SBIC_cdbsize,val) 345 1.1.4.2 reinoud #define GET_SBIC_cdbsize(regs,val) sbic_read_reg(regs,SBIC_cdbsize,val) 346 1.1.4.2 reinoud #define SET_SBIC_control(regs,val) sbic_write_reg(regs,SBIC_control,val) 347 1.1.4.2 reinoud #define GET_SBIC_control(regs,val) sbic_read_reg(regs,SBIC_control,val) 348 1.1.4.2 reinoud #define SET_SBIC_timeo(regs,val) sbic_write_reg(regs,SBIC_timeo,val) 349 1.1.4.2 reinoud #define GET_SBIC_timeo(regs,val) sbic_read_reg(regs,SBIC_timeo,val) 350 1.1.4.2 reinoud #define SET_SBIC_cdb1(regs,val) sbic_write_reg(regs,SBIC_cdb1,val) 351 1.1.4.2 reinoud #define GET_SBIC_cdb1(regs,val) sbic_read_reg(regs,SBIC_cdb1,val) 352 1.1.4.2 reinoud #define SET_SBIC_cdb2(regs,val) sbic_write_reg(regs,SBIC_cdb2,val) 353 1.1.4.2 reinoud #define GET_SBIC_cdb2(regs,val) sbic_read_reg(regs,SBIC_cdb2,val) 354 1.1.4.2 reinoud #define SET_SBIC_cdb3(regs,val) sbic_write_reg(regs,SBIC_cdb3,val) 355 1.1.4.2 reinoud #define GET_SBIC_cdb3(regs,val) sbic_read_reg(regs,SBIC_cdb3,val) 356 1.1.4.2 reinoud #define SET_SBIC_cdb4(regs,val) sbic_write_reg(regs,SBIC_cdb4,val) 357 1.1.4.2 reinoud #define GET_SBIC_cdb4(regs,val) sbic_read_reg(regs,SBIC_cdb4,val) 358 1.1.4.2 reinoud #define SET_SBIC_cdb5(regs,val) sbic_write_reg(regs,SBIC_cdb5,val) 359 1.1.4.2 reinoud #define GET_SBIC_cdb5(regs,val) sbic_read_reg(regs,SBIC_cdb5,val) 360 1.1.4.2 reinoud #define SET_SBIC_cdb6(regs,val) sbic_write_reg(regs,SBIC_cdb6,val) 361 1.1.4.2 reinoud #define GET_SBIC_cdb6(regs,val) sbic_read_reg(regs,SBIC_cdb6,val) 362 1.1.4.2 reinoud #define SET_SBIC_cdb7(regs,val) sbic_write_reg(regs,SBIC_cdb7,val) 363 1.1.4.2 reinoud #define GET_SBIC_cdb7(regs,val) sbic_read_reg(regs,SBIC_cdb7,val) 364 1.1.4.2 reinoud #define SET_SBIC_cdb8(regs,val) sbic_write_reg(regs,SBIC_cdb8,val) 365 1.1.4.2 reinoud #define GET_SBIC_cdb8(regs,val) sbic_read_reg(regs,SBIC_cdb8,val) 366 1.1.4.2 reinoud #define SET_SBIC_cdb9(regs,val) sbic_write_reg(regs,SBIC_cdb9,val) 367 1.1.4.2 reinoud #define GET_SBIC_cdb9(regs,val) sbic_read_reg(regs,SBIC_cdb9,val) 368 1.1.4.2 reinoud #define SET_SBIC_cdb10(regs,val) sbic_write_reg(regs,SBIC_cdb10,val) 369 1.1.4.2 reinoud #define GET_SBIC_cdb10(regs,val) sbic_read_reg(regs,SBIC_cdb10,val) 370 1.1.4.2 reinoud #define SET_SBIC_cdb11(regs,val) sbic_write_reg(regs,SBIC_cdb11,val) 371 1.1.4.2 reinoud #define GET_SBIC_cdb11(regs,val) sbic_read_reg(regs,SBIC_cdb11,val) 372 1.1.4.2 reinoud #define SET_SBIC_cdb12(regs,val) sbic_write_reg(regs,SBIC_cdb12,val) 373 1.1.4.2 reinoud #define GET_SBIC_cdb12(regs,val) sbic_read_reg(regs,SBIC_cdb12,val) 374 1.1.4.2 reinoud #define SET_SBIC_tlun(regs,val) sbic_write_reg(regs,SBIC_tlun,val) 375 1.1.4.2 reinoud #define GET_SBIC_tlun(regs,val) sbic_read_reg(regs,SBIC_tlun,val) 376 1.1.4.2 reinoud #define SET_SBIC_cmd_phase(regs,val) sbic_write_reg(regs,SBIC_cmd_phase,val) 377 1.1.4.2 reinoud #define GET_SBIC_cmd_phase(regs,val) sbic_read_reg(regs,SBIC_cmd_phase,val) 378 1.1.4.2 reinoud #define SET_SBIC_syn(regs,val) sbic_write_reg(regs,SBIC_syn,val) 379 1.1.4.2 reinoud #define GET_SBIC_syn(regs,val) sbic_read_reg(regs,SBIC_syn,val) 380 1.1.4.2 reinoud #define SET_SBIC_count_hi(regs,val) sbic_write_reg(regs,SBIC_count_hi,val) 381 1.1.4.2 reinoud #define GET_SBIC_count_hi(regs,val) sbic_read_reg(regs,SBIC_count_hi,val) 382 1.1.4.2 reinoud #define SET_SBIC_count_med(regs,val) sbic_write_reg(regs,SBIC_count_med,val) 383 1.1.4.2 reinoud #define GET_SBIC_count_med(regs,val) sbic_read_reg(regs,SBIC_count_med,val) 384 1.1.4.2 reinoud #define SET_SBIC_count_lo(regs,val) sbic_write_reg(regs,SBIC_count_lo,val) 385 1.1.4.2 reinoud #define GET_SBIC_count_lo(regs,val) sbic_read_reg(regs,SBIC_count_lo,val) 386 1.1.4.2 reinoud #define SET_SBIC_selid(regs,val) sbic_write_reg(regs,SBIC_selid,val) 387 1.1.4.2 reinoud #define GET_SBIC_selid(regs,val) sbic_read_reg(regs,SBIC_selid,val) 388 1.1.4.2 reinoud #define SET_SBIC_rselid(regs,val) sbic_write_reg(regs,SBIC_rselid,val) 389 1.1.4.2 reinoud #define GET_SBIC_rselid(regs,val) sbic_read_reg(regs,SBIC_rselid,val) 390 1.1.4.2 reinoud #define SET_SBIC_csr(regs,val) sbic_write_reg(regs,SBIC_csr,val) 391 1.1.4.2 reinoud #define GET_SBIC_csr(regs,val) sbic_read_reg(regs,SBIC_csr,val) 392 1.1.4.2 reinoud #define SET_SBIC_cmd(regs,val) sbic_write_reg(regs,SBIC_cmd,val) 393 1.1.4.2 reinoud #define GET_SBIC_cmd(regs,val) sbic_read_reg(regs,SBIC_cmd,val) 394 1.1.4.2 reinoud #define SET_SBIC_data(regs,val) sbic_write_reg(regs,SBIC_data,val) 395 1.1.4.2 reinoud #define GET_SBIC_data(regs,val) sbic_read_reg(regs,SBIC_data,val) 396 1.1.4.2 reinoud 397 1.1.4.2 reinoud #define SBIC_TC_PUT(regs,val) do { \ 398 1.1.4.2 reinoud sbic_write_reg(regs,SBIC_count_hi,((val)>>16)); \ 399 1.1.4.2 reinoud bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \ 400 1.1.4.2 reinoud (val) >> 8); \ 401 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \ 402 1.1.4.2 reinoud 1, BUS_SPACE_BARRIER_WRITE); \ 403 1.1.4.2 reinoud bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \ 404 1.1.4.2 reinoud (val)); \ 405 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 406 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE); \ 407 1.1.4.2 reinoud } while (0) 408 1.1.4.2 reinoud 409 1.1.4.2 reinoud #define SBIC_TC_GET(regs,val) do { \ 410 1.1.4.2 reinoud sbic_read_reg(regs,SBIC_count_hi,(val)); \ 411 1.1.4.2 reinoud (val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \ 412 1.1.4.2 reinoud regs->sc_sbicioh, SBIC_VAL); \ 413 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \ 414 1.1.4.2 reinoud 1, BUS_SPACE_BARRIER_READ); \ 415 1.1.4.2 reinoud (val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \ 416 1.1.4.2 reinoud regs->sc_sbicioh, SBIC_VAL); \ 417 1.1.4.2 reinoud } while (0) 418 1.1.4.2 reinoud 419 1.1.4.2 reinoud #define SBIC_LOAD_COMMAND(regs,cmd,cmdsize) do { \ 420 1.1.4.2 reinoud bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ADDR, \ 421 1.1.4.2 reinoud SBIC_cdb1); \ 422 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 423 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE); \ 424 1.1.4.2 reinoud bus_space_write_multi_1(regs->sc_sbiciot, regs->sbic_ioh, SBIC_VAL, \ 425 1.1.4.2 reinoud (char *)(cmd), cmdsize); \ 426 1.1.4.2 reinoud bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \ 427 1.1.4.2 reinoud 2, BUS_SPACE_BARRIER_WRITE); \ 428 1.1.4.2 reinoud } while (0) 429 1.1.4.2 reinoud 430 1.1.4.2 reinoud #define GET_SBIC_asr(regs,val) \ 431 1.1.4.2 reinoud (val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \ 432 1.1.4.2 reinoud SBIC_ASR) 433 1.1.4.2 reinoud 434 1.1.4.2 reinoud #define WAIT_CIP(regs) do { \ 435 1.1.4.2 reinoud while (bus_space_read_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ASR) \ 436 1.1.4.2 reinoud & SBIC_ASR_CIP) \ 437 1.1.4.2 reinoud ; \ 438 1.1.4.2 reinoud } while (0) 439 1.1.4.2 reinoud 440 1.1.4.2 reinoud /* transmit a byte in programmed I/O mode */ 441 1.1.4.2 reinoud #define SEND_BYTE(regs, ch) do { \ 442 1.1.4.2 reinoud WAIT_CIP(regs); \ 443 1.1.4.2 reinoud SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 444 1.1.4.2 reinoud SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \ 445 1.1.4.2 reinoud SET_SBIC_data(regs, ch); \ 446 1.1.4.2 reinoud } while (0) 447 1.1.4.2 reinoud 448 1.1.4.2 reinoud /* receive a byte in programmed I/O mode */ 449 1.1.4.2 reinoud #define RECV_BYTE(regs, ch) do { \ 450 1.1.4.2 reinoud WAIT_CIP(regs); \ 451 1.1.4.2 reinoud SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 452 1.1.4.2 reinoud SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \ 453 1.1.4.2 reinoud GET_SBIC_data(regs, ch); \ 454 1.1.4.2 reinoud } while (0) 455
Indexes created Fri Oct 31 11:10:07 GMT 2025