bus_defs.h revision 1.1
1 /* $NetBSD: bus_defs.h,v 1.1 2011/07/01 17:09:58 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #ifndef _ALGOR_BUS_DEFS_H_ 61 #define _ALGOR_BUS_DEFS_H_ 62 63 #include <sys/types.h> 64 65 #ifdef _KERNEL 66 /* 67 * Addresses (in bus space). 68 */ 69 typedef u_long bus_addr_t; 70 typedef u_long bus_size_t; 71 72 /* 73 * Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled. 74 */ 75 #if defined(DEBUG) && !defined(BUS_SPACE_DEBUG) 76 #define BUS_SPACE_DEBUG 77 #endif 78 79 #ifdef BUS_SPACE_DEBUG 80 #include <sys/systm.h> /* for printf() prototype */ 81 /* 82 * Macros for checking the aligned-ness of pointers passed to bus 83 * space ops. Strict alignment is required by the MIPS architecture, 84 * and a trap will occur if unaligned access is performed. These 85 * may aid in the debugging of a broken device driver by displaying 86 * useful information about the problem. 87 */ 88 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 89 ((((u_long)(p)) & (sizeof(t)-1)) == 0) 90 91 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 92 ({ \ 93 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 94 printf("%s 0x%lx not aligned to %zu bytes %s:%d\n", \ 95 d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \ 96 } \ 97 (void) 0; \ 98 }) 99 100 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 101 #else 102 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0 103 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 104 #endif /* BUS_SPACE_DEBUG */ 105 #endif /* _KERNEL */ 106 107 struct mips_bus_space_translation; 108 109 /* 110 * Access methods for bus space. 111 */ 112 typedef struct algor_bus_space *bus_space_tag_t; 113 typedef u_long bus_space_handle_t; 114 115 struct algor_bus_space { 116 /* cookie */ 117 void *bs_cookie; 118 119 /* mapping/unmapping */ 120 int (*bs_map)(void *, bus_addr_t, bus_size_t, 121 int, bus_space_handle_t *, int); 122 void (*bs_unmap)(void *, bus_space_handle_t, 123 bus_size_t, int); 124 int (*bs_subregion)(void *, bus_space_handle_t, 125 bus_size_t, bus_size_t, bus_space_handle_t *); 126 127 /* ALGOR SPECIFIC MAPPING METHOD */ 128 int (*bs_translate)(void *, bus_addr_t, bus_size_t, 129 int, struct mips_bus_space_translation *); 130 int (*bs_get_window)(void *, int, 131 struct mips_bus_space_translation *); 132 133 /* allocation/deallocation */ 134 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 135 bus_size_t, bus_size_t, bus_size_t, int, 136 bus_addr_t *, bus_space_handle_t *); 137 void (*bs_free)(void *, bus_space_handle_t, 138 bus_size_t); 139 140 /* get kernel virtual address */ 141 void * (*bs_vaddr)(void *, bus_space_handle_t); 142 143 /* mmap for user */ 144 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 145 146 /* barrier */ 147 void (*bs_barrier)(void *, bus_space_handle_t, 148 bus_size_t, bus_size_t, int); 149 150 /* read (single) */ 151 u_int8_t (*bs_r_1)(void *, bus_space_handle_t, 152 bus_size_t); 153 u_int16_t (*bs_r_2)(void *, bus_space_handle_t, 154 bus_size_t); 155 u_int32_t (*bs_r_4)(void *, bus_space_handle_t, 156 bus_size_t); 157 u_int64_t (*bs_r_8)(void *, bus_space_handle_t, 158 bus_size_t); 159 160 /* read multiple */ 161 void (*bs_rm_1)(void *, bus_space_handle_t, 162 bus_size_t, u_int8_t *, bus_size_t); 163 void (*bs_rm_2)(void *, bus_space_handle_t, 164 bus_size_t, u_int16_t *, bus_size_t); 165 void (*bs_rm_4)(void *, bus_space_handle_t, 166 bus_size_t, u_int32_t *, bus_size_t); 167 void (*bs_rm_8)(void *, bus_space_handle_t, 168 bus_size_t, u_int64_t *, bus_size_t); 169 170 /* read region */ 171 void (*bs_rr_1)(void *, bus_space_handle_t, 172 bus_size_t, u_int8_t *, bus_size_t); 173 void (*bs_rr_2)(void *, bus_space_handle_t, 174 bus_size_t, u_int16_t *, bus_size_t); 175 void (*bs_rr_4)(void *, bus_space_handle_t, 176 bus_size_t, u_int32_t *, bus_size_t); 177 void (*bs_rr_8)(void *, bus_space_handle_t, 178 bus_size_t, u_int64_t *, bus_size_t); 179 180 /* write (single) */ 181 void (*bs_w_1)(void *, bus_space_handle_t, 182 bus_size_t, u_int8_t); 183 void (*bs_w_2)(void *, bus_space_handle_t, 184 bus_size_t, u_int16_t); 185 void (*bs_w_4)(void *, bus_space_handle_t, 186 bus_size_t, u_int32_t); 187 void (*bs_w_8)(void *, bus_space_handle_t, 188 bus_size_t, u_int64_t); 189 190 /* write multiple */ 191 void (*bs_wm_1)(void *, bus_space_handle_t, 192 bus_size_t, const u_int8_t *, bus_size_t); 193 void (*bs_wm_2)(void *, bus_space_handle_t, 194 bus_size_t, const u_int16_t *, bus_size_t); 195 void (*bs_wm_4)(void *, bus_space_handle_t, 196 bus_size_t, const u_int32_t *, bus_size_t); 197 void (*bs_wm_8)(void *, bus_space_handle_t, 198 bus_size_t, const u_int64_t *, bus_size_t); 199 200 /* write region */ 201 void (*bs_wr_1)(void *, bus_space_handle_t, 202 bus_size_t, const u_int8_t *, bus_size_t); 203 void (*bs_wr_2)(void *, bus_space_handle_t, 204 bus_size_t, const u_int16_t *, bus_size_t); 205 void (*bs_wr_4)(void *, bus_space_handle_t, 206 bus_size_t, const u_int32_t *, bus_size_t); 207 void (*bs_wr_8)(void *, bus_space_handle_t, 208 bus_size_t, const u_int64_t *, bus_size_t); 209 210 /* set multiple */ 211 void (*bs_sm_1)(void *, bus_space_handle_t, 212 bus_size_t, u_int8_t, bus_size_t); 213 void (*bs_sm_2)(void *, bus_space_handle_t, 214 bus_size_t, u_int16_t, bus_size_t); 215 void (*bs_sm_4)(void *, bus_space_handle_t, 216 bus_size_t, u_int32_t, bus_size_t); 217 void (*bs_sm_8)(void *, bus_space_handle_t, 218 bus_size_t, u_int64_t, bus_size_t); 219 220 /* set region */ 221 void (*bs_sr_1)(void *, bus_space_handle_t, 222 bus_size_t, u_int8_t, bus_size_t); 223 void (*bs_sr_2)(void *, bus_space_handle_t, 224 bus_size_t, u_int16_t, bus_size_t); 225 void (*bs_sr_4)(void *, bus_space_handle_t, 226 bus_size_t, u_int32_t, bus_size_t); 227 void (*bs_sr_8)(void *, bus_space_handle_t, 228 bus_size_t, u_int64_t, bus_size_t); 229 230 /* copy */ 231 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 232 bus_space_handle_t, bus_size_t, bus_size_t); 233 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 234 bus_space_handle_t, bus_size_t, bus_size_t); 235 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 236 bus_space_handle_t, bus_size_t, bus_size_t); 237 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 238 bus_space_handle_t, bus_size_t, bus_size_t); 239 }; 240 241 /* 242 * Translation of an MIPS bus address; INTERNAL USE ONLY. 243 */ 244 struct mips_bus_space_translation { 245 bus_addr_t mbst_bus_start; /* start of bus window */ 246 bus_addr_t mbst_bus_end; /* end of bus window */ 247 paddr_t mbst_sys_start; /* start of sysBus window */ 248 paddr_t mbst_sys_end; /* end of sysBus window */ 249 int mbst_align_stride;/* alignment stride */ 250 int mbst_flags; /* flags; see below */ 251 }; 252 253 #define BUS_SPACE_MAP_CACHEABLE 0x01 254 #define BUS_SPACE_MAP_LINEAR 0x02 255 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 256 257 #ifdef _KERNEL 258 259 #define BUS_SPACE_BARRIER_READ 0x01 260 #define BUS_SPACE_BARRIER_WRITE 0x02 261 262 #define __BUS_SPACE_HAS_STREAM_METHODS 1 263 264 /* 265 * Flags used in various bus DMA methods. 266 */ 267 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 268 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 269 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 270 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 271 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 272 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 273 #define BUS_DMA_BUS2 0x020 274 #define BUS_DMA_BUS3 0x040 275 #define BUS_DMA_BUS4 0x080 276 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 277 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 278 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 279 280 /* 281 * Private flags stored in the DMA map. 282 */ 283 #define ALGOR_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 284 285 /* Forwards needed by prototypes below. */ 286 struct mbuf; 287 struct uio; 288 289 /* 290 * Operations performed by bus_dmamap_sync(). 291 */ 292 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 293 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 294 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 295 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 296 297 typedef struct algor_bus_dma_tag *bus_dma_tag_t; 298 typedef struct algor_bus_dmamap *bus_dmamap_t; 299 300 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 301 302 /* 303 * bus_dma_segment_t 304 * 305 * Describes a single contiguous DMA transaction. Values 306 * are suitable for programming into DMA registers. 307 */ 308 struct algor_bus_dma_segment { 309 bus_addr_t ds_addr; /* DMA address */ 310 bus_size_t ds_len; /* length of transfer */ 311 bus_addr_t _ds_vaddr; /* virtual address, 0 if invalid */ 312 }; 313 typedef struct algor_bus_dma_segment bus_dma_segment_t; 314 315 /* 316 * bus_dma_tag_t 317 * 318 * A machine-dependent opaque type describing the implementation of 319 * DMA for a given bus. 320 */ 321 struct algor_bus_dma_tag { 322 void *_cookie; /* cookie used in the guts */ 323 324 bus_addr_t _wbase; /* DMA window base */ 325 bus_addr_t _physbase; /* physical base of the window */ 326 bus_size_t _wsize; /* size of the window */ 327 328 /* 329 * DMA mapping methods. 330 */ 331 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 332 bus_size_t, bus_size_t, int, bus_dmamap_t *); 333 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 334 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 335 bus_size_t, struct proc *, int); 336 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 337 struct mbuf *, int); 338 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 339 struct uio *, int); 340 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 341 bus_dma_segment_t *, int, bus_size_t, int); 342 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 343 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 344 bus_addr_t, bus_size_t, int); 345 346 /* 347 * DMA memory utility functions. 348 */ 349 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 350 bus_size_t, bus_dma_segment_t *, int, int *, int); 351 void (*_dmamem_free)(bus_dma_tag_t, 352 bus_dma_segment_t *, int); 353 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 354 int, size_t, void **, int); 355 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 356 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 357 int, off_t, int, int); 358 }; 359 360 /* 361 * bus_dmamap_t 362 * 363 * Describes a DMA mapping. 364 */ 365 struct algor_bus_dmamap { 366 /* 367 * PRIVATE MEMBERS: not for use my machine-independent code. 368 */ 369 bus_size_t _dm_size; /* largest DMA transfer mappable */ 370 int _dm_segcnt; /* number of segs this map can map */ 371 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 372 bus_size_t _dm_boundary; /* don't cross this */ 373 int _dm_flags; /* misc. flags */ 374 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 375 376 /* 377 * Private cookie to be used by the DMA back-end. 378 */ 379 void *_dm_cookie; 380 381 /* 382 * PUBLIC MEMBERS: these are used by machine-independent code. 383 */ 384 bus_size_t dm_maxsegsz; /* largest possible segment */ 385 bus_size_t dm_mapsize; /* size of the mapping */ 386 int dm_nsegs; /* # valid segments in mapping */ 387 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 388 }; 389 390 #endif /* _KERNEL */ 391 392 #endif /* _ALGOR_BUS_DEFS_H_ */ 393
Indexes created Thu Sep 25 16:09:42 GMT 2025