vtpbc.c revision 1.3
1 /* $NetBSD: vtpbc.c,v 1.3 2001/06/14 18:52:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Support for the V3 Semiconductor i960 PCI bus controller. This appears 41 * on some MIPS boards (notably Algorithmics P-4032 and P-5064). 42 * 43 * Some help was provided by the Algorithmics PMON sources. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 #include <machine/locore.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <algor/pci/vtpbcreg.h> 58 #include <algor/pci/vtpbcvar.h> 59 60 struct vtpbc_config vtpbc_configuration; 61 62 #define PCI_CONF_LOCK(s) (s) = splhigh() 63 #define PCI_CONF_UNLOCK(s) splx((s)) 64 65 const char *vtpbc_revs[] = { 66 "A", 67 "B0", 68 "B1", 69 "B2", 70 "C0", 71 }; 72 const int vtpbc_nrevs = sizeof(vtpbc_revs) / sizeof(vtpbc_revs[0]); 73 74 void vtpbc_attach_hook(struct device *, struct device *, 75 struct pcibus_attach_args *); 76 int vtpbc_bus_maxdevs(void *, int); 77 pcitag_t vtpbc_make_tag(void *, int, int, int); 78 void vtpbc_decompose_tag(void *, pcitag_t, int *, int *, int *); 79 pcireg_t vtpbc_conf_read(void *, pcitag_t, int); 80 void vtpbc_conf_write(void *, pcitag_t, int, pcireg_t); 81 82 /* 83 * vtpbc_init: 84 * 85 * Initialize the V3 PCI controller's software state. We 86 * simply use the existing windows that the firmware has 87 * set up for us. 88 */ 89 void 90 vtpbc_init(pci_chipset_tag_t pc, struct vtpbc_config *vt) 91 { 92 93 pc->pc_conf_v = vt; 94 pc->pc_attach_hook = vtpbc_attach_hook; 95 pc->pc_bus_maxdevs = vtpbc_bus_maxdevs; 96 pc->pc_make_tag = vtpbc_make_tag; 97 pc->pc_decompose_tag = vtpbc_decompose_tag; 98 pc->pc_conf_read = vtpbc_conf_read; 99 pc->pc_conf_write = vtpbc_conf_write; 100 101 vt->vt_rev = V96X_PCI_CC_REV(vt) & V96X_PCI_CC_REV_VREV; 102 103 /* 104 * Determine the PCI I/O space base that our PCI 105 * I/O window maps to. NOTE: We disable this on 106 * PBC rev < B2. 107 * 108 * Also note that PMON has disabled the I/O space 109 * if the old-style PCI address map is in-use. 110 */ 111 if (vt->vt_rev < V96X_VREV_B2) 112 vt->vt_pci_iobase = (bus_addr_t) -1; 113 else { 114 if ((V96X_LB_BASE2(vt) & V96X_LB_BASEx_ENABLE) == 0) 115 vt->vt_pci_iobase = (bus_addr_t) -1; 116 else 117 vt->vt_pci_iobase = 118 (V96X_LB_MAP2(vt) & V96X_LB_MAPx_MAP_ADR) << 16; 119 } 120 121 /* 122 * Determine the PCI memory space base that our PCI 123 * memory window maps to. 124 */ 125 vt->vt_pci_membase = (V96X_LB_MAP1(vt) & V96X_LB_MAPx_MAP_ADR) << 16; 126 127 /* 128 * Determine the PCI window base that maps host RAM for 129 * DMA. 130 */ 131 vt->vt_dma_winbase = V96X_PCI_BASE1(vt) & 0xfffffff0; 132 } 133 134 void 135 vtpbc_attach_hook(struct device *parent, struct device *self, 136 struct pcibus_attach_args *pba) 137 { 138 } 139 140 int 141 vtpbc_bus_maxdevs(void *v, int busno) 142 { 143 144 return (32); 145 } 146 147 pcitag_t 148 vtpbc_make_tag(void *v, int b, int d, int f) 149 { 150 151 return ((b << 16) | (d << 11) | (f << 8)); 152 } 153 154 void 155 vtpbc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 156 { 157 158 if (bp != NULL) 159 *bp = (tag >> 16) & 0xff; 160 if (dp != NULL) 161 *dp = (tag >> 11) & 0x1f; 162 if (fp != NULL) 163 *fp = (tag >> 8) & 0x7; 164 } 165 166 static int 167 vtpbc_conf_addr(struct vtpbc_config *vt, pcitag_t tag, int offset, 168 u_int32_t *cfgoff, u_int32_t *ad_low) 169 { 170 int b, d, f; 171 172 vtpbc_decompose_tag(vt, tag, &b, &d, &f); 173 174 if (b == 0) { 175 if (d > (31 - vt->vt_adbase)) 176 return (1); 177 *cfgoff = (1UL << (d + vt->vt_adbase)) | (f << 8) | 178 offset; 179 *ad_low = 0; 180 } else if (vt->vt_rev >= V96X_VREV_C0) { 181 *cfgoff = tag | offset; 182 *ad_low = V96X_LB_MAPx_AD_LOW_EN; 183 } else 184 return (1); 185 186 return (0); 187 } 188 189 pcireg_t 190 vtpbc_conf_read(void *v, pcitag_t tag, int offset) 191 { 192 struct vtpbc_config *vt = v; 193 pcireg_t data; 194 u_int32_t cfgoff, ad_low; 195 int s; 196 u_int16_t errbits; 197 198 if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low)) 199 return ((pcireg_t) -1); 200 201 PCI_CONF_LOCK(s); 202 203 /* high 12 bits of address go into map register */ 204 V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) | 205 ad_low | V96X_LB_TYPE_CONF; 206 207 /* clear aborts */ 208 V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT; 209 210 wbflush(); 211 212 /* low 20 bits of address are offset into config space */ 213 data = *(__volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff)); 214 215 errbits = V96X_PCI_STAT(vt) & 216 (V96X_PCI_STAT_M_ABORT|V96X_PCI_STAT_T_ABORT); 217 if (errbits) { 218 V96X_PCI_STAT(vt) |= errbits; 219 data = (pcireg_t) -1; 220 } 221 222 PCI_CONF_UNLOCK(s); 223 224 return (data); 225 } 226 227 void 228 vtpbc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 229 { 230 struct vtpbc_config *vt = v; 231 u_int32_t cfgoff, ad_low; 232 int s; 233 234 if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low)) 235 panic("vtpbc_conf_write"); 236 237 PCI_CONF_LOCK(s); 238 239 /* high 12 bits of address go into map register */ 240 V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) | 241 ad_low | V96X_LB_TYPE_CONF; 242 243 /* clear aborts */ 244 V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT; 245 246 wbflush(); 247 248 /* low 20 bits of address are offset into config space */ 249 *(__volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff)) = data; 250 251 /* wait for FIFO to drain */ 252 while (V96X_FIFO_STAT(vt) & V96X_FIFO_STAT_L2P_WR) 253 /* spin */ ; 254 255 PCI_CONF_UNLOCK(s); 256 } 257
Indexes created Tue Sep 23 02:09:52 GMT 2025