alpha_cpu.h revision 1.42.2.3
1 1.42.2.3 nathanw /* $NetBSD: alpha_cpu.h,v 1.42.2.3 2003/01/14 21:00:46 nathanw Exp $ */ 2 1.42.2.2 nathanw 3 1.42.2.2 nathanw /* 4 1.42.2.2 nathanw * Copyright (c) 1996 Carnegie-Mellon University. 5 1.42.2.2 nathanw * All rights reserved. 6 1.42.2.2 nathanw * 7 1.42.2.2 nathanw * Author: Chris G. Demetriou 8 1.42.2.2 nathanw * 9 1.42.2.2 nathanw * Permission to use, copy, modify and distribute this software and 10 1.42.2.2 nathanw * its documentation is hereby granted, provided that both the copyright 11 1.42.2.2 nathanw * notice and this permission notice appear in all copies of the 12 1.42.2.2 nathanw * software, derivative works or modified versions, and any portions 13 1.42.2.2 nathanw * thereof, and that both notices appear in supporting documentation. 14 1.42.2.2 nathanw * 15 1.42.2.2 nathanw * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 1.42.2.2 nathanw * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 1.42.2.2 nathanw * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 1.42.2.2 nathanw * 19 1.42.2.2 nathanw * Carnegie Mellon requests users of this software to return to 20 1.42.2.2 nathanw * 21 1.42.2.2 nathanw * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 1.42.2.2 nathanw * School of Computer Science 23 1.42.2.2 nathanw * Carnegie Mellon University 24 1.42.2.2 nathanw * Pittsburgh PA 15213-3890 25 1.42.2.2 nathanw * 26 1.42.2.2 nathanw * any improvements or extensions that they make and grant Carnegie the 27 1.42.2.2 nathanw * rights to redistribute these changes. 28 1.42.2.2 nathanw */ 29 1.42.2.2 nathanw 30 1.42.2.2 nathanw #ifndef __ALPHA_ALPHA_CPU_H__ 31 1.42.2.2 nathanw #define __ALPHA_ALPHA_CPU_H__ 32 1.42.2.2 nathanw 33 1.42.2.2 nathanw /* 34 1.42.2.2 nathanw * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 35 1.42.2.2 nathanw * 36 1.42.2.2 nathanw * Definitions for: 37 1.42.2.2 nathanw * 38 1.42.2.2 nathanw * Process Control Block 39 1.42.2.2 nathanw * Interrupt/Exception/Syscall Stack Frame 40 1.42.2.2 nathanw * Processor Status Register 41 1.42.2.2 nathanw * Machine Check Error Summary Register 42 1.42.2.2 nathanw * Machine Check Logout Area 43 1.42.2.2 nathanw * Per CPU state Management of Machine Check Handling 44 1.42.2.2 nathanw * Virtual Memory Management 45 1.42.2.2 nathanw * Kernel Entry Vectors 46 1.42.2.2 nathanw * MMCSR Fault Type Codes 47 1.42.2.2 nathanw * Translation Buffer Invalidation 48 1.42.2.2 nathanw * 49 1.42.2.2 nathanw * and miscellaneous PALcode operations. 50 1.42.2.2 nathanw */ 51 1.42.2.2 nathanw 52 1.42.2.2 nathanw 53 1.42.2.2 nathanw /* 54 1.42.2.2 nathanw * Process Control Block definitions [OSF/1 PALcode Specific] 55 1.42.2.2 nathanw */ 56 1.42.2.2 nathanw 57 1.42.2.2 nathanw struct alpha_pcb { 58 1.42.2.2 nathanw unsigned long apcb_ksp; /* kernel stack ptr */ 59 1.42.2.2 nathanw unsigned long apcb_usp; /* user stack ptr */ 60 1.42.2.2 nathanw unsigned long apcb_ptbr; /* page table base reg */ 61 1.42.2.2 nathanw unsigned int apcb_cpc; /* charged process cycles */ 62 1.42.2.2 nathanw unsigned int apcb_asn; /* address space number */ 63 1.42.2.2 nathanw unsigned long apcb_unique; /* process unique value */ 64 1.42.2.2 nathanw #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */ 65 1.42.2.2 nathanw unsigned long apcb_flags; /* flags; see below */ 66 1.42.2.2 nathanw unsigned long apcb_decrsv0; /* DEC reserved */ 67 1.42.2.2 nathanw unsigned long apcb_decrsv1; /* DEC reserved */ 68 1.42.2.2 nathanw }; 69 1.42.2.2 nathanw 70 1.42.2.2 nathanw #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 71 1.42.2.2 nathanw #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 72 1.42.2.2 nathanw 73 1.42.2.2 nathanw /* 74 1.42.2.2 nathanw * Interrupt/Exception/Syscall "Hardware" (really PALcode) 75 1.42.2.2 nathanw * Stack Frame definitions 76 1.42.2.2 nathanw * 77 1.42.2.2 nathanw * These are quadword offsets from the sp on kernel entry, i.e. 78 1.42.2.2 nathanw * to get to the value in question you access (sp + (offset * 8)). 79 1.42.2.2 nathanw * 80 1.42.2.2 nathanw * On syscall entry, A0-A2 aren't written to memory but space 81 1.42.2.2 nathanw * _is_ reserved for them. 82 1.42.2.2 nathanw */ 83 1.42.2.2 nathanw 84 1.42.2.2 nathanw #define ALPHA_HWFRAME_PS 0 /* processor status register */ 85 1.42.2.2 nathanw #define ALPHA_HWFRAME_PC 1 /* program counter */ 86 1.42.2.2 nathanw #define ALPHA_HWFRAME_GP 2 /* global pointer */ 87 1.42.2.2 nathanw #define ALPHA_HWFRAME_A0 3 /* a0 */ 88 1.42.2.2 nathanw #define ALPHA_HWFRAME_A1 4 /* a1 */ 89 1.42.2.2 nathanw #define ALPHA_HWFRAME_A2 5 /* a2 */ 90 1.42.2.2 nathanw 91 1.42.2.2 nathanw #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 92 1.42.2.2 nathanw 93 1.42.2.2 nathanw /* 94 1.42.2.2 nathanw * Processor Status Register [OSF/1 PALcode Specific] 95 1.42.2.2 nathanw * 96 1.42.2.2 nathanw * Includes user/kernel mode bit, interrupt priority levels, etc. 97 1.42.2.2 nathanw */ 98 1.42.2.2 nathanw 99 1.42.2.2 nathanw #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 100 1.42.2.2 nathanw #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 101 1.42.2.2 nathanw 102 1.42.2.2 nathanw #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 103 1.42.2.2 nathanw #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 104 1.42.2.2 nathanw #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 105 1.42.2.2 nathanw #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 106 1.42.2.2 nathanw #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 107 1.42.2.2 nathanw 108 1.42.2.2 nathanw #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 109 1.42.2.2 nathanw 110 1.42.2.2 nathanw /* Convenience constants: what must be set/clear in user mode */ 111 1.42.2.2 nathanw #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 112 1.42.2.2 nathanw #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 113 1.42.2.2 nathanw 114 1.42.2.2 nathanw /* 115 1.42.2.2 nathanw * Interrupt Type Code Definitions [OSF/1 PALcode Specific] 116 1.42.2.2 nathanw */ 117 1.42.2.2 nathanw 118 1.42.2.2 nathanw #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */ 119 1.42.2.2 nathanw #define ALPHA_INTR_CLOCK 1 /* clock interrupt */ 120 1.42.2.2 nathanw #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */ 121 1.42.2.2 nathanw #define ALPHA_INTR_DEVICE 3 /* device interrupt */ 122 1.42.2.2 nathanw #define ALPHA_INTR_PERF 4 /* performance counter */ 123 1.42.2.2 nathanw #define ALPHA_INTR_PASSIVE 5 /* passive release */ 124 1.42.2.2 nathanw 125 1.42.2.2 nathanw /* 126 1.42.2.2 nathanw * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 127 1.42.2.2 nathanw * 128 1.42.2.2 nathanw * The following bits are values as read. On write, _PCE, _SCE, and 129 1.42.2.2 nathanw * _MIP are "write 1 to clear." 130 1.42.2.2 nathanw */ 131 1.42.2.2 nathanw 132 1.42.2.2 nathanw #define ALPHA_MCES_IMP \ 133 1.42.2.2 nathanw 0xffffffff00000000 /* impl. dependent */ 134 1.42.2.2 nathanw #define ALPHA_MCES_RSVD \ 135 1.42.2.2 nathanw 0x00000000ffffffe0 /* reserved */ 136 1.42.2.2 nathanw #define ALPHA_MCES_DSC \ 137 1.42.2.2 nathanw 0x0000000000000010 /* disable system correctable error reporting */ 138 1.42.2.2 nathanw #define ALPHA_MCES_DPC \ 139 1.42.2.2 nathanw 0x0000000000000008 /* disable processor correctable error reporting */ 140 1.42.2.2 nathanw #define ALPHA_MCES_PCE \ 141 1.42.2.2 nathanw 0x0000000000000004 /* processor correctable error in progress */ 142 1.42.2.2 nathanw #define ALPHA_MCES_SCE \ 143 1.42.2.2 nathanw 0x0000000000000002 /* system correctable error in progress */ 144 1.42.2.2 nathanw #define ALPHA_MCES_MIP \ 145 1.42.2.2 nathanw 0x0000000000000001 /* machine check in progress */ 146 1.42.2.2 nathanw 147 1.42.2.2 nathanw /* 148 1.42.2.2 nathanw * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 149 1.42.2.2 nathanw * 150 1.42.2.2 nathanw * Note that these are *generic* OSF/1 PALcode specific defines. There are 151 1.42.2.2 nathanw * platform variations to these entities. 152 1.42.2.2 nathanw */ 153 1.42.2.2 nathanw 154 1.42.2.2 nathanw struct alpha_logout_area { 155 1.42.2.2 nathanw unsigned int la_frame_size; /* frame size */ 156 1.42.2.2 nathanw unsigned int la_flags; /* flags; see below */ 157 1.42.2.2 nathanw unsigned int la_cpu_offset; /* offset to cpu area */ 158 1.42.2.2 nathanw unsigned int la_system_offset; /* offset to system area */ 159 1.42.2.2 nathanw }; 160 1.42.2.2 nathanw 161 1.42.2.2 nathanw #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 162 1.42.2.2 nathanw #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 163 1.42.2.2 nathanw #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 164 1.42.2.2 nathanw 165 1.42.2.2 nathanw #define ALPHA_LOGOUT_NOT_BUILT \ 166 1.42.2.2 nathanw (struct alpha_logout_area *)0xffffffffffffffff) 167 1.42.2.2 nathanw 168 1.42.2.2 nathanw #define ALPHA_LOGOUT_PAL_AREA(lap) \ 169 1.42.2.2 nathanw (unsigned long *)((unsigned char *)(lap) + 16) 170 1.42.2.2 nathanw #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 171 1.42.2.2 nathanw ((lap)->la_cpu_offset - 16) 172 1.42.2.2 nathanw #define ALPHA_LOGOUT_CPU_AREA(lap) \ 173 1.42.2.2 nathanw (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 174 1.42.2.2 nathanw #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 175 1.42.2.2 nathanw ((lap)->la_system_offset - (lap)->la_cpu_offset) 176 1.42.2.2 nathanw #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 177 1.42.2.2 nathanw (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 178 1.42.2.2 nathanw #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 179 1.42.2.2 nathanw ((lap)->la_frame_size - (lap)->la_system_offset) 180 1.42.2.2 nathanw 181 1.42.2.2 nathanw /* types of machine checks */ 182 1.42.2.2 nathanw #define ALPHA_SYS_ERROR 0x620 /* System correctable error */ 183 1.42.2.2 nathanw #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */ 184 1.42.2.2 nathanw #define ALPHA_SYS_MCHECK 0x660 /* System machine check */ 185 1.42.2.2 nathanw #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */ 186 1.42.2.2 nathanw 187 1.42.2.2 nathanw /* 188 1.42.2.2 nathanw * Virtual Memory Management definitions [OSF/1 PALcode Specific] 189 1.42.2.2 nathanw * 190 1.42.2.2 nathanw * Includes user and kernel space addresses and information, 191 1.42.2.2 nathanw * page table entry definitions, etc. 192 1.42.2.2 nathanw * 193 1.42.2.2 nathanw * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 194 1.42.2.2 nathanw */ 195 1.42.2.2 nathanw 196 1.42.2.2 nathanw #define ALPHA_PGSHIFT 13 197 1.42.2.2 nathanw #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 198 1.42.2.2 nathanw 199 1.42.2.2 nathanw #define ALPHA_USEG_BASE 0 /* virtual */ 200 1.42.2.2 nathanw #define ALPHA_USEG_END 0x000003ffffffffff 201 1.42.2.2 nathanw 202 1.42.2.2 nathanw #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 203 1.42.2.2 nathanw #define ALPHA_K0SEG_END 0xfffffdffffffffff 204 1.42.2.2 nathanw #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 205 1.42.2.2 nathanw #define ALPHA_K1SEG_END 0xffffffffffffffff 206 1.42.2.2 nathanw 207 1.42.2.2 nathanw #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 208 1.42.2.2 nathanw #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 209 1.42.2.2 nathanw 210 1.42.2.2 nathanw #define ALPHA_PTE_VALID 0x0001 211 1.42.2.2 nathanw 212 1.42.2.2 nathanw #define ALPHA_PTE_FAULT_ON_READ 0x0002 213 1.42.2.2 nathanw #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 214 1.42.2.2 nathanw #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 215 1.42.2.2 nathanw 216 1.42.2.2 nathanw #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 217 1.42.2.2 nathanw #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 218 1.42.2.2 nathanw 219 1.42.2.2 nathanw #define ALPHA_PTE_PROT 0xff00 220 1.42.2.2 nathanw #define ALPHA_PTE_KR 0x0100 221 1.42.2.2 nathanw #define ALPHA_PTE_UR 0x0200 222 1.42.2.2 nathanw #define ALPHA_PTE_KW 0x1000 223 1.42.2.2 nathanw #define ALPHA_PTE_UW 0x2000 224 1.42.2.2 nathanw 225 1.42.2.2 nathanw #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 226 1.42.2.2 nathanw 227 1.42.2.2 nathanw #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000 228 1.42.2.2 nathanw #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */ 229 1.42.2.2 nathanw 230 1.42.2.2 nathanw #define ALPHA_PTE_PFN 0xffffffff00000000 231 1.42.2.2 nathanw 232 1.42.2.2 nathanw #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 233 1.42.2.2 nathanw #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 234 1.42.2.2 nathanw 235 1.42.2.2 nathanw typedef unsigned long alpha_pt_entry_t; 236 1.42.2.2 nathanw 237 1.42.2.2 nathanw /* 238 1.42.2.2 nathanw * Kernel Entry Vectors. [OSF/1 PALcode Specific] 239 1.42.2.2 nathanw */ 240 1.42.2.2 nathanw 241 1.42.2.2 nathanw #define ALPHA_KENTRY_INT 0 242 1.42.2.2 nathanw #define ALPHA_KENTRY_ARITH 1 243 1.42.2.2 nathanw #define ALPHA_KENTRY_MM 2 244 1.42.2.2 nathanw #define ALPHA_KENTRY_IF 3 245 1.42.2.2 nathanw #define ALPHA_KENTRY_UNA 4 246 1.42.2.2 nathanw #define ALPHA_KENTRY_SYS 5 247 1.42.2.2 nathanw 248 1.42.2.2 nathanw /* 249 1.42.2.2 nathanw * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 250 1.42.2.2 nathanw */ 251 1.42.2.2 nathanw 252 1.42.2.2 nathanw #define ALPHA_MMCSR_INVALTRANS 0 253 1.42.2.2 nathanw #define ALPHA_MMCSR_ACCESS 1 254 1.42.2.2 nathanw #define ALPHA_MMCSR_FOR 2 255 1.42.2.2 nathanw #define ALPHA_MMCSR_FOE 3 256 1.42.2.2 nathanw #define ALPHA_MMCSR_FOW 4 257 1.42.2.2 nathanw 258 1.42.2.2 nathanw /* 259 1.42.2.2 nathanw * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 260 1.42.2.2 nathanw */ 261 1.42.2.2 nathanw 262 1.42.2.2 nathanw #define ALPHA_IF_CODE_BPT 0 263 1.42.2.2 nathanw #define ALPHA_IF_CODE_BUGCHK 1 264 1.42.2.2 nathanw #define ALPHA_IF_CODE_GENTRAP 2 265 1.42.2.2 nathanw #define ALPHA_IF_CODE_FEN 3 266 1.42.2.2 nathanw #define ALPHA_IF_CODE_OPDEC 4 267 1.42.2.2 nathanw 268 1.42.2.2 nathanw #ifdef _KERNEL 269 1.42.2.2 nathanw 270 1.42.2.2 nathanw /* 271 1.42.2.2 nathanw * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 272 1.42.2.2 nathanw */ 273 1.42.2.2 nathanw 274 1.42.2.2 nathanw #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 275 1.42.2.2 nathanw #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 276 1.42.2.2 nathanw #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 277 1.42.2.2 nathanw #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 278 1.42.2.2 nathanw #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 279 1.42.2.2 nathanw 280 1.42.2.2 nathanw #endif /* _KERNEL */ 281 1.42.2.2 nathanw 282 1.42.2.2 nathanw /* 283 1.42.2.2 nathanw * Bits used in the amask instruction [EV56 and later] 284 1.42.2.2 nathanw */ 285 1.42.2.2 nathanw 286 1.42.2.2 nathanw #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */ 287 1.42.2.2 nathanw #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */ 288 1.42.2.2 nathanw #define ALPHA_AMASK_CIX 0x0004 /* count extension */ 289 1.42.2.2 nathanw #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */ 290 1.42.2.2 nathanw #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */ 291 1.42.2.2 nathanw 292 1.42.2.2 nathanw #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \ 293 1.42.2.2 nathanw ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \ 294 1.42.2.2 nathanw ALPHA_AMASK_PAT) 295 1.42.2.2 nathanw 296 1.42.2.2 nathanw #define ALPHA_AMASK_BITS \ 297 1.42.2.2 nathanw "\20\12PAT\11MVI\3CIX\2FIX\1BWX" 298 1.42.2.2 nathanw 299 1.42.2.2 nathanw /* 300 1.42.2.2 nathanw * Chip family IDs returned by implver instruction 301 1.42.2.2 nathanw */ 302 1.42.2.2 nathanw 303 1.42.2.2 nathanw #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */ 304 1.42.2.2 nathanw #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */ 305 1.42.2.2 nathanw #define ALPHA_IMPLVER_EV6 2 /* EV6 */ 306 1.42.2.2 nathanw 307 1.42.2.2 nathanw #ifdef _KERNEL 308 1.42.2.2 nathanw 309 1.42.2.2 nathanw /* 310 1.42.2.2 nathanw * Maximum processor ID we allow from `whami', and related constants. 311 1.42.2.2 nathanw * 312 1.42.2.2 nathanw * XXX This is not really processor or PALcode specific, but this is 313 1.42.2.2 nathanw * a convenient place to put these definitions. 314 1.42.2.2 nathanw * 315 1.42.2.2 nathanw * XXX This is clipped at 63 so that we can use `long's for proc bitmasks. 316 1.42.2.2 nathanw */ 317 1.42.2.2 nathanw 318 1.42.2.2 nathanw #define ALPHA_WHAMI_MAXID 63 319 1.42.2.2 nathanw #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1) 320 1.42.2.2 nathanw 321 1.42.2.2 nathanw /* 322 1.42.2.2 nathanw * Misc. support routines. 323 1.42.2.2 nathanw */ 324 1.42.2.2 nathanw const char *alpha_dsr_sysname(void); 325 1.42.2.2 nathanw 326 1.42.2.2 nathanw /* 327 1.42.2.2 nathanw * Stubs for Alpha instructions normally inaccessible from C. 328 1.42.2.2 nathanw */ 329 1.42.2.2 nathanw unsigned long alpha_amask(unsigned long); 330 1.42.2.2 nathanw unsigned long alpha_implver(void); 331 1.42.2.2 nathanw 332 1.42.2.2 nathanw #endif /* _KERNEL */ 333 1.42.2.2 nathanw 334 1.42.2.2 nathanw /* XXX Expose the insn wrappers to userspace, for now. */ 335 1.42.2.2 nathanw 336 1.42.2.2 nathanw static __inline unsigned long 337 1.42.2.2 nathanw alpha_rpcc(void) 338 1.42.2.2 nathanw { 339 1.42.2.2 nathanw unsigned long v0; 340 1.42.2.2 nathanw 341 1.42.2.2 nathanw __asm __volatile("rpcc %0" : "=r" (v0)); 342 1.42.2.2 nathanw return (v0); 343 1.42.2.2 nathanw } 344 1.42.2.2 nathanw 345 1.42.2.2 nathanw #define alpha_mb() __asm __volatile("mb" : : : "memory") 346 1.42.2.2 nathanw #define alpha_wmb() __asm __volatile("mb" : : : "memory") /* XXX */ 347 1.42.2.2 nathanw 348 1.42.2.2 nathanw #if defined(_KERNEL) || defined(_STANDALONE) 349 1.42.2.2 nathanw 350 1.42.2.2 nathanw /* 351 1.42.2.2 nathanw * Stubs for OSF/1 PALcode operations. 352 1.42.2.2 nathanw */ 353 1.42.2.2 nathanw #include <machine/pal.h> 354 1.42.2.2 nathanw 355 1.42.2.2 nathanw void alpha_pal_cflush(unsigned long); 356 1.42.2.2 nathanw void alpha_pal_halt(void) __attribute__((__noreturn__)); 357 1.42.2.2 nathanw unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */ 358 1.42.2.2 nathanw void alpha_pal_wrent(void *, unsigned long); 359 1.42.2.2 nathanw void alpha_pal_wrvptptr(unsigned long); 360 1.42.2.2 nathanw 361 1.42.2.2 nathanw #define alpha_pal_draina() __asm __volatile("call_pal %0 # PAL_draina" \ 362 1.42.2.2 nathanw : : "i" (PAL_draina) : "memory") 363 1.42.2.2 nathanw 364 1.42.2.2 nathanw #define alpha_pal_imb() __asm __volatile("call_pal %0 # PAL_imb" \ 365 1.42.2.2 nathanw : : "i" (PAL_imb) : "memory") 366 1.42.2.2 nathanw 367 1.42.2.2 nathanw static __inline unsigned long 368 1.42.2.2 nathanw alpha_pal_rdmces(void) 369 1.42.2.2 nathanw { 370 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 371 1.42.2.2 nathanw 372 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_rdmces" 373 1.42.2.2 nathanw : "=r" (v0) 374 1.42.2.2 nathanw : "i" (PAL_OSF1_rdmces) 375 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 376 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 377 1.42.2.2 nathanw 378 1.42.2.2 nathanw return (v0); 379 1.42.2.2 nathanw } 380 1.42.2.2 nathanw 381 1.42.2.2 nathanw static __inline unsigned long 382 1.42.2.2 nathanw alpha_pal_rdps(void) 383 1.42.2.2 nathanw { 384 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 385 1.42.2.2 nathanw 386 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_rdps" 387 1.42.2.2 nathanw : "=r" (v0) 388 1.42.2.2 nathanw : "i" (PAL_OSF1_rdps) 389 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 390 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 391 1.42.2.2 nathanw 392 1.42.2.2 nathanw return (v0); 393 1.42.2.2 nathanw } 394 1.42.2.2 nathanw 395 1.42.2.2 nathanw static __inline unsigned long 396 1.42.2.3 nathanw alpha_pal_rdunique(void) 397 1.42.2.3 nathanw { 398 1.42.2.3 nathanw register unsigned long v0 __asm("$0"); 399 1.42.2.3 nathanw 400 1.42.2.3 nathanw __asm __volatile("call_pal %1 # PAL_rdunique" 401 1.42.2.3 nathanw : "=r" (v0) 402 1.42.2.3 nathanw : "i" (PAL_rdunique)); 403 1.42.2.3 nathanw 404 1.42.2.3 nathanw return (v0); 405 1.42.2.3 nathanw } 406 1.42.2.3 nathanw 407 1.42.2.3 nathanw static __inline unsigned long 408 1.42.2.2 nathanw alpha_pal_rdusp(void) 409 1.42.2.2 nathanw { 410 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 411 1.42.2.2 nathanw 412 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_rdusp" 413 1.42.2.2 nathanw : "=r" (v0) 414 1.42.2.2 nathanw : "i" (PAL_OSF1_rdusp) 415 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 416 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 417 1.42.2.2 nathanw 418 1.42.2.2 nathanw return (v0); 419 1.42.2.2 nathanw } 420 1.42.2.2 nathanw 421 1.42.2.2 nathanw static __inline unsigned long 422 1.42.2.2 nathanw alpha_pal_rdval(void) 423 1.42.2.2 nathanw { 424 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 425 1.42.2.2 nathanw 426 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_rdval" 427 1.42.2.2 nathanw : "=r" (v0) 428 1.42.2.2 nathanw : "i" (PAL_OSF1_rdval) 429 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 430 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 431 1.42.2.2 nathanw 432 1.42.2.2 nathanw return (v0); 433 1.42.2.2 nathanw } 434 1.42.2.2 nathanw 435 1.42.2.2 nathanw static __inline unsigned long 436 1.42.2.2 nathanw alpha_pal_swpctx(unsigned long ctx) 437 1.42.2.2 nathanw { 438 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = ctx; 439 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 440 1.42.2.2 nathanw 441 1.42.2.2 nathanw __asm __volatile("call_pal %2 # PAL_OSF1_swpctx" 442 1.42.2.2 nathanw : "=r" (a0), "=r" (v0) 443 1.42.2.2 nathanw : "i" (PAL_OSF1_swpctx), "0" (a0) 444 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 445 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25", "memory"); 446 1.42.2.2 nathanw 447 1.42.2.2 nathanw return (v0); 448 1.42.2.2 nathanw } 449 1.42.2.2 nathanw 450 1.42.2.2 nathanw static __inline unsigned long 451 1.42.2.2 nathanw alpha_pal_swpipl(unsigned long ipl) 452 1.42.2.2 nathanw { 453 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = ipl; 454 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 455 1.42.2.2 nathanw 456 1.42.2.2 nathanw __asm __volatile("call_pal %2 # PAL_OSF1_swpipl" 457 1.42.2.2 nathanw : "=r" (a0), "=r" (v0) 458 1.42.2.2 nathanw : "i" (PAL_OSF1_swpipl), "0" (a0) 459 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 460 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25", "memory"); 461 1.42.2.2 nathanw 462 1.42.2.2 nathanw return (v0); 463 1.42.2.2 nathanw } 464 1.42.2.2 nathanw 465 1.42.2.2 nathanw static __inline void 466 1.42.2.2 nathanw alpha_pal_tbi(unsigned long op, vaddr_t va) 467 1.42.2.2 nathanw { 468 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = op; 469 1.42.2.2 nathanw register unsigned long a1 __asm("$17") = va; 470 1.42.2.2 nathanw 471 1.42.2.2 nathanw __asm __volatile("call_pal %2 # PAL_OSF1_tbi" 472 1.42.2.2 nathanw : "=r" (a0), "=r" (a1) 473 1.42.2.2 nathanw : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1) 474 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above), a1 (above) */ 475 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 476 1.42.2.2 nathanw } 477 1.42.2.2 nathanw 478 1.42.2.2 nathanw static __inline unsigned long 479 1.42.2.2 nathanw alpha_pal_whami(void) 480 1.42.2.2 nathanw { 481 1.42.2.2 nathanw register unsigned long v0 __asm("$0"); 482 1.42.2.2 nathanw 483 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_whami" 484 1.42.2.2 nathanw : "=r" (v0) 485 1.42.2.2 nathanw : "i" (PAL_OSF1_whami) 486 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 487 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 488 1.42.2.2 nathanw 489 1.42.2.2 nathanw return (v0); 490 1.42.2.2 nathanw } 491 1.42.2.2 nathanw 492 1.42.2.2 nathanw static __inline void 493 1.42.2.2 nathanw alpha_pal_wrfen(unsigned long onoff) 494 1.42.2.2 nathanw { 495 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = onoff; 496 1.42.2.2 nathanw 497 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_wrfen" 498 1.42.2.2 nathanw : "=r" (a0) 499 1.42.2.2 nathanw : "i" (PAL_OSF1_wrfen), "0" (a0) 500 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 501 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 502 1.42.2.2 nathanw } 503 1.42.2.2 nathanw 504 1.42.2.2 nathanw static __inline void 505 1.42.2.2 nathanw alpha_pal_wripir(unsigned long cpu_id) 506 1.42.2.2 nathanw { 507 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = cpu_id; 508 1.42.2.2 nathanw 509 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_ipir" 510 1.42.2.2 nathanw : "=r" (a0) 511 1.42.2.2 nathanw : "i" (PAL_ipir), "0" (a0) 512 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 513 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 514 1.42.2.2 nathanw } 515 1.42.2.2 nathanw 516 1.42.2.2 nathanw static __inline void 517 1.42.2.3 nathanw alpha_pal_wrunique(unsigned long unique) 518 1.42.2.3 nathanw { 519 1.42.2.3 nathanw register unsigned long a0 __asm("$16") = unique; 520 1.42.2.3 nathanw 521 1.42.2.3 nathanw __asm __volatile("call_pal %1 # PAL_wrunique" 522 1.42.2.3 nathanw : "=r" (a0) 523 1.42.2.3 nathanw : "i" (PAL_wrunique), "0" (a0)); 524 1.42.2.3 nathanw } 525 1.42.2.3 nathanw 526 1.42.2.3 nathanw static __inline void 527 1.42.2.2 nathanw alpha_pal_wrusp(unsigned long usp) 528 1.42.2.2 nathanw { 529 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = usp; 530 1.42.2.2 nathanw 531 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_wrusp" 532 1.42.2.2 nathanw : "=r" (a0) 533 1.42.2.2 nathanw : "i" (PAL_OSF1_wrusp), "0" (a0) 534 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 535 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 536 1.42.2.2 nathanw } 537 1.42.2.2 nathanw 538 1.42.2.2 nathanw static __inline void 539 1.42.2.2 nathanw alpha_pal_wrmces(unsigned long mces) 540 1.42.2.2 nathanw { 541 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = mces; 542 1.42.2.2 nathanw 543 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_wrmces" 544 1.42.2.2 nathanw : "=r" (a0) 545 1.42.2.2 nathanw : "i" (PAL_OSF1_wrmces), "0" (a0) 546 1.42.2.2 nathanw /* clobbers t0, t8..t11 */ 547 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 548 1.42.2.2 nathanw } 549 1.42.2.2 nathanw 550 1.42.2.2 nathanw static __inline void 551 1.42.2.2 nathanw alpha_pal_wrval(unsigned long val) 552 1.42.2.2 nathanw { 553 1.42.2.2 nathanw register unsigned long a0 __asm("$16") = val; 554 1.42.2.2 nathanw 555 1.42.2.2 nathanw __asm __volatile("call_pal %1 # PAL_OSF1_wrval" 556 1.42.2.2 nathanw : "=r" (a0) 557 1.42.2.2 nathanw : "i" (PAL_OSF1_wrval), "0" (a0) 558 1.42.2.2 nathanw /* clobbers t0, t8..t11, a0 (above) */ 559 1.42.2.2 nathanw : "$1", "$22", "$23", "$24", "$25"); 560 1.42.2.2 nathanw } 561 1.42.2.2 nathanw 562 1.42.2.2 nathanw #endif /* _KERNEL */ 563 1.42.2.2 nathanw 564 1.42.2.2 nathanw #endif /* __ALPHA_ALPHA_CPU_H__ */ 565
Indexes created Thu Oct 30 16:09:53 GMT 2025