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alpha_cpu.h revision 1.1 
      1 /*	$NetBSD: alpha_cpu.h,v 1.1 1996/07/09 00:40:58 cgd Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #ifndef __ALPHA_ALPHA_CPU_H__
     31 #define	__ALPHA_ALPHA_CPU_H__
     32 
     33 /*
     34  * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
     35  *
     36  * Definitions for:
     37  *
     38  *	Processor Status Register
     39  *	Virtual Memory Management
     40  *	Translation Buffer Invalidation
     41  *
     42  * and miscellaneous PALcode operations.
     43  */
     44 
     45 
     46 /*
     47  * Processor Status Register [OSF/1 PALcode Specific]
     48  *
     49  * Includes user/kernel mode bit, interrupt priority levels, etc.
     50  */
     51 
     52 #define	ALPHA_PSL_USERMODE	0x0008		/* set -> user mode */
     53 #define	ALPHA_PSL_IPL_MASK	0x0007		/* interrupt level mask */
     54 
     55 #define	ALPHA_PSL_IPL_0		0x0000		/* all interrupts enabled */
     56 #define	ALPHA_PSL_IPL_SOFT	0x0001		/* software ints disabled */
     57 #define	ALPHA_PSL_IPL_IO	0x0004		/* I/O dev ints disabled */
     58 #define	ALPHA_PSL_IPL_CLOCK	0x0005		/* clock ints disabled */
     59 #define	ALPHA_PSL_IPL_HIGH	0x0006		/* all but mchecks disabled */
     60 
     61 #define	ALPHA_PSL_MUST_BE_ZERO	0xfffffffffffffff0
     62 
     63 /* Convenience constants: what must be set/clear in user mode */
     64 #define	ALPHA_PSL_USERSET	ALPHA_PSL_USERMODE
     65 #define	ALPHA_PSL_USERCLR	(ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
     66 
     67 typedef unsigned long alpha_psl_t;
     68 
     69 /*
     70  * Virtual Memory Management [OSF/1 PALcode Specific]
     71  *
     72  * Includes user and kernel space addresses and information,
     73  * page table entry definitions, etc.
     74  *
     75  * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
     76  */
     77 
     78 #define	ALPHA_PGSHIFT		13
     79 
     80 #define	ALPHA_USEG_BASE		0			/* virtual */
     81 #define	ALPHA_USEG_END		0x000003ffffffffff
     82 
     83 #define	ALPHA_K0SEG_BASE	0xfffffc0000000000	/* direct-mapped */
     84 #define	ALPHA_K0SEG_END		0xfffffe0000000000
     85 #define	ALPHA_K1SEG_BASE	ALPHA_K0SEG_END		/* virtual */
     86 #define	ALPHA_K1SEG_END		0xffffffffffffffff
     87 
     88 #define ALPHA_K0SEG_TO_PHYS(x)	((x) & 0x00000003ffffffff)
     89 #define ALPHA_PHYS_TO_K0SEG(x)	((x) | ALPHA_K0SEG_BASE)
     90 
     91 #define	ALPHA_PTE_VALID			0x0001
     92 
     93 #define	ALPHA_PTE_FAULT_ON_READ		0x0002
     94 #define	ALPHA_PTE_FAULT_ON_WRITE	0x0004
     95 #define	ALPHA_PTE_FAULT_ON_EXECUTE	0x0008
     96 
     97 #define	ALPHA_PTE_ASM			0x0010		/* addr. space match */
     98 #define	ALPHA_PTE_GRANULARITY		0x0060		/* granularity hint */
     99 
    100 #define	ALPHA_PTE_PROT			0xff00
    101 #define	ALPHA_PTE_KR			0x0100
    102 #define	ALPHA_PTE_UR			0x0200
    103 #define	ALPHA_PTE_KW			0x1000
    104 #define	ALPHA_PTE_UW			0x2000
    105 
    106 #define	ALPHA_PTE_WRITE			(ALPHA_PTE_KW | ALPHA_PTE_KW)
    107 
    108 #define	ALPHA_PTE_SOFTWARE		0xffff0000
    109 
    110 #define	ALPHA_PTE_PFN			0xffffffff00000000
    111 
    112 #define	ALPHA_PTE_TO_PFN(pte)		((pte) >> 32)
    113 #define	ALPHA_PTE_FROM_PFN(pfn)		((pfn) << 32)
    114 
    115 typedef unsigned long alpha_pt_entry_t;
    116 
    117 
    118 /*
    119  * Translation Buffer Invalidation [OSF/1 PALcode Specific]
    120  */
    121 
    122 #define	TBIA()		alpha_pal_tbi(-2, 0)		/* all TB entries */
    123 #define	TBIAP()		alpha_pal_tbi(-1, 0)		/* all per-process */
    124 #define	TBISI(va)	alpha_pal_tbi(1, (va))		/* ITB entry for va */
    125 #define	TBISD(va)	alpha_pal_tbi(2, (va))		/* DTB entry for va */
    126 #define	TBIS(va)	alpha_pal_tbi(3, (va))		/* all for va */
    127 
    128 
    129 /*
    130  * Stubs for Alpha instructions normally inaccessible from C.
    131  */
    132 void		alpha_mb __P((void));
    133 void		alpha_wmb __P((void));
    134 
    135 /*
    136  * Stubs for OSF/1 PALcode operations.
    137  */
    138 void		alpha_pal_imb __P((void));
    139 alpha_psl_t	alpha_pal_swpipl __P((alpha_psl_t));
    140 alpha_psl_t	_alpha_pal_swpipl __P((alpha_psl_t));	/* for profiling */
    141 void		alpha_pal_tbi __P((unsigned long, vm_offset_t));
    142 void		alpha_pal_halt __P((void)) __attribute__((__noreturn__));
    143 
    144 #endif __ALPHA_ALPHA_CPU_H__
    145