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alpha_cpu.h revision 1.11 
      1 /* $NetBSD: alpha_cpu.h,v 1.11 1997/09/03 23:09:05 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #ifndef __ALPHA_ALPHA_CPU_H__
     31 #define	__ALPHA_ALPHA_CPU_H__
     32 
     33 /*
     34  * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
     35  *
     36  * Definitions for:
     37  *
     38  *	Process Control Block
     39  *	Interrupt/Exception/Syscall Stack Frame
     40  *	Processor Status Register
     41  *	Machine Check Error Summary Register
     42  *	Machine Check Logout Area
     43  *	Virtual Memory Management
     44  *	Kernel Entry Vectors
     45  *	MMCSR Fault Type Codes
     46  *	Translation Buffer Invalidation
     47  *
     48  * and miscellaneous PALcode operations.
     49  */
     50 
     51 
     52 /*
     53  * Process Control Block definitions [OSF/1 PALcode Specific]
     54  */
     55 
     56 struct alpha_pcb {
     57 	unsigned long	apcb_ksp;	/* kernel stack ptr */
     58 	unsigned long	apcb_usp;	/* user stack ptr */
     59 	unsigned long	apcb_ptbr;	/* page table base reg */
     60 	unsigned int	apcb_cpc;	/* charged process cycles */
     61 	unsigned int	apcb_asn;	/* address space number */
     62 	unsigned long	apcb_unique;	/* process unique value */
     63 	unsigned long	apcb_flags;	/* flags; see below */
     64 	unsigned long	apcb_decrsv0;	/* DEC reserved */
     65 	unsigned long	apcb_decrsv1;	/* DEC reserved */
     66 };
     67 
     68 #define	ALPHA_PCB_FLAGS_FEN	0x0000000000000001
     69 #define	ALPHA_PCB_FLAGS_PME	0x4000000000000000
     70 
     71 /*
     72  * Interrupt/Exception/Syscall "Hardware" (really PALcode)
     73  * Stack Frame definitions
     74  *
     75  * These are quadword offsets from the sp on kernel entry, i.e.
     76  * to get to the value in question you access (sp + (offset * 8)).
     77  *
     78  * On syscall entry, A0-A2 aren't written to memory but space
     79  * _is_ reserved for them.
     80  */
     81 
     82 #define	ALPHA_HWFRAME_PS	0	/* processor status register */
     83 #define	ALPHA_HWFRAME_PC	1	/* program counter */
     84 #define	ALPHA_HWFRAME_GP	2	/* global pointer */
     85 #define	ALPHA_HWFRAME_A0	3	/* a0 */
     86 #define	ALPHA_HWFRAME_A1	4	/* a1 */
     87 #define	ALPHA_HWFRAME_A2	5	/* a2 */
     88 
     89 #define	ALPHA_HWFRAME_SIZE	6	/* 6 8-byte words */
     90 
     91 /*
     92  * Processor Status Register [OSF/1 PALcode Specific]
     93  *
     94  * Includes user/kernel mode bit, interrupt priority levels, etc.
     95  */
     96 
     97 #define	ALPHA_PSL_USERMODE	0x0008		/* set -> user mode */
     98 #define	ALPHA_PSL_IPL_MASK	0x0007		/* interrupt level mask */
     99 
    100 #define	ALPHA_PSL_IPL_0		0x0000		/* all interrupts enabled */
    101 #define	ALPHA_PSL_IPL_SOFT	0x0001		/* software ints disabled */
    102 #define	ALPHA_PSL_IPL_IO	0x0004		/* I/O dev ints disabled */
    103 #define	ALPHA_PSL_IPL_CLOCK	0x0005		/* clock ints disabled */
    104 #define	ALPHA_PSL_IPL_HIGH	0x0006		/* all but mchecks disabled */
    105 
    106 #define	ALPHA_PSL_MUST_BE_ZERO	0xfffffffffffffff0
    107 
    108 /* Convenience constants: what must be set/clear in user mode */
    109 #define	ALPHA_PSL_USERSET	ALPHA_PSL_USERMODE
    110 #define	ALPHA_PSL_USERCLR	(ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
    111 
    112 /*
    113  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    114  *
    115  * The following bits are values as read.  On write, _PCE, _SCE, and
    116  * _MIP are "write 1 to clear."
    117  */
    118 
    119 #define	ALPHA_MCES_IMP							\
    120     0xffffffff00000000	/* impl. dependent */
    121 #define	ALPHA_MCES_RSVD							\
    122     0x00000000ffffffe0	/* reserved */
    123 #define	ALPHA_MCES_DSC							\
    124     0x0000000000000010	/* disable system correctable error reporting */
    125 #define	ALPHA_MCES_DPC							\
    126     0x0000000000000008	/* disable processor correctable error reporting */
    127 #define	ALPHA_MCES_PCE							\
    128     0x0000000000000004	/* processor correctable error in progress */
    129 #define	ALPHA_MCES_SCE							\
    130     0x0000000000000002	/* system correctable error in progress */
    131 #define	ALPHA_MCES_MIP							\
    132     0x0000000000000001	/* machine check in progress */
    133 
    134 /*
    135  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    136  */
    137 
    138 struct alpha_logout_area {
    139 	unsigned int	la_frame_size;		/* frame size */
    140 	unsigned int	la_flags;		/* flags; see below */
    141 	unsigned int	la_cpu_offset;		/* offset to cpu area */
    142 	unsigned int	la_system_offset;	/* offset to system area */
    143 };
    144 
    145 #define	ALPHA_LOGOUT_FLAGS_RETRY	0x80000000	/* OK to continue */
    146 #define	ALPHA_LOGOUT_FLAGS_SE		0x40000000	/* second error */
    147 #define	ALPHA_LOGOUT_FLAGS_SBZ		0x3fffffff	/* should be zero */
    148 
    149 #define	ALPHA_LOGOUT_NOT_BUILT						\
    150     (struct alpha_logout_area *)0xffffffffffffffff)
    151 
    152 #define	ALPHA_LOGOUT_PAL_AREA(lap)					\
    153     (unsigned long *)((unsigned char *)(lap) + 16)
    154 #define	ALPHA_LOGOUT_PAL_SIZE(lap)					\
    155     ((lap)->la_cpu_offset - 16)
    156 #define	ALPHA_LOGOUT_CPU_AREA(lap)					\
    157     (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
    158 #define	ALPHA_LOGOUT_CPU_SIZE(lap)					\
    159     ((lap)->la_system_offset - (lap)->la_cpu_offset)
    160 #define	ALPHA_LOGOUT_SYSTEM_AREA(lap)					\
    161     (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
    162 #define	ALPHA_LOGOUT_SYSTEM_SIZE(lap)					\
    163     ((lap)->la_frame_size - (lap)->la_system_offset)
    164 
    165 /*
    166  * Virtual Memory Management definitions [OSF/1 PALcode Specific]
    167  *
    168  * Includes user and kernel space addresses and information,
    169  * page table entry definitions, etc.
    170  *
    171  * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
    172  */
    173 
    174 #define	ALPHA_PGSHIFT		13
    175 #define	ALPHA_PGBYTES		(1 << ALPHA_PGSHIFT)
    176 
    177 #define	ALPHA_USEG_BASE		0			/* virtual */
    178 #define	ALPHA_USEG_END		0x000003ffffffffff
    179 
    180 #define	ALPHA_K0SEG_BASE	0xfffffc0000000000	/* direct-mapped */
    181 #define	ALPHA_K0SEG_END		0xfffffdffffffffff
    182 #define	ALPHA_K1SEG_BASE	0xfffffe0000000000	/* virtual */
    183 #define	ALPHA_K1SEG_END		0xffffffffffffffff
    184 
    185 #define ALPHA_K0SEG_TO_PHYS(x)	((x) & ~ALPHA_K0SEG_BASE)
    186 #define ALPHA_PHYS_TO_K0SEG(x)	((x) | ALPHA_K0SEG_BASE)
    187 
    188 #define	ALPHA_PTE_VALID			0x0001
    189 
    190 #define	ALPHA_PTE_FAULT_ON_READ		0x0002
    191 #define	ALPHA_PTE_FAULT_ON_WRITE	0x0004
    192 #define	ALPHA_PTE_FAULT_ON_EXECUTE	0x0008
    193 
    194 #define	ALPHA_PTE_ASM			0x0010		/* addr. space match */
    195 #define	ALPHA_PTE_GRANULARITY		0x0060		/* granularity hint */
    196 
    197 #define	ALPHA_PTE_PROT			0xff00
    198 #define	ALPHA_PTE_KR			0x0100
    199 #define	ALPHA_PTE_UR			0x0200
    200 #define	ALPHA_PTE_KW			0x1000
    201 #define	ALPHA_PTE_UW			0x2000
    202 
    203 #define	ALPHA_PTE_WRITE			(ALPHA_PTE_KW | ALPHA_PTE_UW)
    204 
    205 #define	ALPHA_PTE_SOFTWARE		0xffff0000
    206 
    207 #define	ALPHA_PTE_PFN			0xffffffff00000000
    208 
    209 #define	ALPHA_PTE_TO_PFN(pte)		((pte) >> 32)
    210 #define	ALPHA_PTE_FROM_PFN(pfn)		((pfn) << 32)
    211 
    212 typedef unsigned long alpha_pt_entry_t;
    213 
    214 /*
    215  * Kernel Entry Vectors.  [OSF/1 PALcode Specific]
    216  */
    217 
    218 #define	ALPHA_KENTRY_INT	0
    219 #define	ALPHA_KENTRY_ARITH	1
    220 #define	ALPHA_KENTRY_MM		2
    221 #define	ALPHA_KENTRY_IF		3
    222 #define	ALPHA_KENTRY_UNA	4
    223 #define	ALPHA_KENTRY_SYS	5
    224 
    225 /*
    226  * MMCSR Fault Type Codes.  [OSF/1 PALcode Specific]
    227  */
    228 
    229 #define	ALPHA_MMCSR_INVALTRANS	0
    230 #define	ALPHA_MMCSR_ACCESS	1
    231 #define	ALPHA_MMCSR_FOR		2
    232 #define	ALPHA_MMCSR_FOE		3
    233 #define	ALPHA_MMCSR_FOW		4
    234 
    235 /*
    236  * Instruction Fault Type Codes.  [OSF/1 PALcode Specific]
    237  */
    238 
    239 #define	ALPHA_IF_CODE_BPT	0
    240 #define	ALPHA_IF_CODE_BUGCHK	1
    241 #define	ALPHA_IF_CODE_GENTRAP	2
    242 #define	ALPHA_IF_CODE_FEN	3
    243 #define	ALPHA_IF_CODE_OPDEC	4
    244 
    245 /*
    246  * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
    247  */
    248 
    249 #define	ALPHA_TBIA()	alpha_pal_tbi(-2, 0)		/* all TB entries */
    250 #define	ALPHA_TBIAP()	alpha_pal_tbi(-1, 0)		/* all per-process */
    251 #define	ALPHA_TBISI(va)	alpha_pal_tbi(1, (va))		/* ITB entry for va */
    252 #define	ALPHA_TBISD(va)	alpha_pal_tbi(2, (va))		/* DTB entry for va */
    253 #define	ALPHA_TBIS(va)	alpha_pal_tbi(3, (va))		/* all for va */
    254 
    255 /*
    256  * Stubs for Alpha instructions normally inaccessible from C.
    257  */
    258 unsigned long	alpha_rpcc __P((void));
    259 void		alpha_mb __P((void));
    260 void		alpha_wmb __P((void));
    261 
    262 /*
    263  * Stubs for OSF/1 PALcode operations.
    264  */
    265 void		alpha_pal_imb __P((void));
    266 void		alpha_pal_cflush __P((unsigned long));
    267 void		alpha_pal_draina __P((void));
    268 void		alpha_pal_halt __P((void)) __attribute__((__noreturn__));
    269 unsigned long	alpha_pal_rdmces __P((void));
    270 unsigned long	alpha_pal_rdps __P((void));
    271 unsigned long	alpha_pal_rdusp __P((void));
    272 unsigned long	alpha_pal_rdval __P((void));
    273 unsigned long	alpha_pal_swpipl __P((unsigned long));
    274 unsigned long	_alpha_pal_swpipl __P((unsigned long));	/* for profiling */
    275 void		alpha_pal_tbi __P((unsigned long, vm_offset_t));
    276 unsigned long	alpha_pal_whami __P((void));
    277 void		alpha_pal_wrent __P((void *, unsigned long));
    278 void		alpha_pal_wrfen __P((unsigned long));
    279 void		alpha_pal_wripir __P((unsigned long));
    280 void		alpha_pal_wrusp __P((unsigned long));
    281 void		alpha_pal_wrvptptr __P((unsigned long));
    282 void		alpha_pal_wrmces __P((unsigned long));
    283 void		alpha_pal_wrval __P((unsigned long));
    284 
    285 #endif /* __ALPHA_ALPHA_CPU_H__ */
    286