alpha_cpu.h revision 1.16
1 /* $NetBSD: alpha_cpu.h,v 1.16 1998/02/13 00:12:52 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #ifndef __ALPHA_ALPHA_CPU_H__ 31 #define __ALPHA_ALPHA_CPU_H__ 32 33 /* 34 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 35 * 36 * Definitions for: 37 * 38 * Process Control Block 39 * Interrupt/Exception/Syscall Stack Frame 40 * Processor Status Register 41 * Machine Check Error Summary Register 42 * Machine Check Logout Area 43 * Virtual Memory Management 44 * Kernel Entry Vectors 45 * MMCSR Fault Type Codes 46 * Translation Buffer Invalidation 47 * 48 * and miscellaneous PALcode operations. 49 */ 50 51 52 /* 53 * Process Control Block definitions [OSF/1 PALcode Specific] 54 */ 55 56 struct alpha_pcb { 57 unsigned long apcb_ksp; /* kernel stack ptr */ 58 unsigned long apcb_usp; /* user stack ptr */ 59 unsigned long apcb_ptbr; /* page table base reg */ 60 unsigned int apcb_cpc; /* charged process cycles */ 61 unsigned int apcb_asn; /* address space number */ 62 unsigned long apcb_unique; /* process unique value */ 63 unsigned long apcb_flags; /* flags; see below */ 64 unsigned long apcb_decrsv0; /* DEC reserved */ 65 unsigned long apcb_decrsv1; /* DEC reserved */ 66 }; 67 68 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 69 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 70 71 /* 72 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 73 * Stack Frame definitions 74 * 75 * These are quadword offsets from the sp on kernel entry, i.e. 76 * to get to the value in question you access (sp + (offset * 8)). 77 * 78 * On syscall entry, A0-A2 aren't written to memory but space 79 * _is_ reserved for them. 80 */ 81 82 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 83 #define ALPHA_HWFRAME_PC 1 /* program counter */ 84 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 85 #define ALPHA_HWFRAME_A0 3 /* a0 */ 86 #define ALPHA_HWFRAME_A1 4 /* a1 */ 87 #define ALPHA_HWFRAME_A2 5 /* a2 */ 88 89 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 90 91 /* 92 * Processor Status Register [OSF/1 PALcode Specific] 93 * 94 * Includes user/kernel mode bit, interrupt priority levels, etc. 95 */ 96 97 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 98 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 99 100 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 101 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 102 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 103 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 104 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 105 106 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 107 108 /* Convenience constants: what must be set/clear in user mode */ 109 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 110 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 111 112 /* 113 * Interrupt Type Code Definitions [OSF/1 PALcode Specific] 114 */ 115 116 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */ 117 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */ 118 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */ 119 #define ALPHA_INTR_DEVICE 3 /* device interrupt */ 120 #define ALPHA_INTR_PERF 4 /* performance counter */ 121 #define ALPHA_INTR_PASSIVE 5 /* passive release */ 122 123 /* 124 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 125 * 126 * The following bits are values as read. On write, _PCE, _SCE, and 127 * _MIP are "write 1 to clear." 128 */ 129 130 #define ALPHA_MCES_IMP \ 131 0xffffffff00000000 /* impl. dependent */ 132 #define ALPHA_MCES_RSVD \ 133 0x00000000ffffffe0 /* reserved */ 134 #define ALPHA_MCES_DSC \ 135 0x0000000000000010 /* disable system correctable error reporting */ 136 #define ALPHA_MCES_DPC \ 137 0x0000000000000008 /* disable processor correctable error reporting */ 138 #define ALPHA_MCES_PCE \ 139 0x0000000000000004 /* processor correctable error in progress */ 140 #define ALPHA_MCES_SCE \ 141 0x0000000000000002 /* system correctable error in progress */ 142 #define ALPHA_MCES_MIP \ 143 0x0000000000000001 /* machine check in progress */ 144 145 /* 146 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 147 */ 148 149 struct alpha_logout_area { 150 unsigned int la_frame_size; /* frame size */ 151 unsigned int la_flags; /* flags; see below */ 152 unsigned int la_cpu_offset; /* offset to cpu area */ 153 unsigned int la_system_offset; /* offset to system area */ 154 }; 155 156 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 157 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 158 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 159 160 #define ALPHA_LOGOUT_NOT_BUILT \ 161 (struct alpha_logout_area *)0xffffffffffffffff) 162 163 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 164 (unsigned long *)((unsigned char *)(lap) + 16) 165 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 166 ((lap)->la_cpu_offset - 16) 167 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 168 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 169 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 170 ((lap)->la_system_offset - (lap)->la_cpu_offset) 171 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 172 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 173 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 174 ((lap)->la_frame_size - (lap)->la_system_offset) 175 176 /* 177 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 178 * 179 * Includes user and kernel space addresses and information, 180 * page table entry definitions, etc. 181 * 182 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 183 */ 184 185 #define ALPHA_PGSHIFT 13 186 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 187 188 #define ALPHA_USEG_BASE 0 /* virtual */ 189 #define ALPHA_USEG_END 0x000003ffffffffff 190 191 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 192 #define ALPHA_K0SEG_END 0xfffffdffffffffff 193 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 194 #define ALPHA_K1SEG_END 0xffffffffffffffff 195 196 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 197 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 198 199 #define ALPHA_PTE_VALID 0x0001 200 201 #define ALPHA_PTE_FAULT_ON_READ 0x0002 202 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 203 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 204 205 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 206 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 207 208 #define ALPHA_PTE_PROT 0xff00 209 #define ALPHA_PTE_KR 0x0100 210 #define ALPHA_PTE_UR 0x0200 211 #define ALPHA_PTE_KW 0x1000 212 #define ALPHA_PTE_UW 0x2000 213 214 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 215 216 #define ALPHA_PTE_SOFTWARE 0xffff0000 217 218 #define ALPHA_PTE_PFN 0xffffffff00000000 219 220 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 221 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 222 223 typedef unsigned long alpha_pt_entry_t; 224 225 /* 226 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 227 */ 228 229 #define ALPHA_KENTRY_INT 0 230 #define ALPHA_KENTRY_ARITH 1 231 #define ALPHA_KENTRY_MM 2 232 #define ALPHA_KENTRY_IF 3 233 #define ALPHA_KENTRY_UNA 4 234 #define ALPHA_KENTRY_SYS 5 235 236 /* 237 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 238 */ 239 240 #define ALPHA_MMCSR_INVALTRANS 0 241 #define ALPHA_MMCSR_ACCESS 1 242 #define ALPHA_MMCSR_FOR 2 243 #define ALPHA_MMCSR_FOE 3 244 #define ALPHA_MMCSR_FOW 4 245 246 /* 247 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 248 */ 249 250 #define ALPHA_IF_CODE_BPT 0 251 #define ALPHA_IF_CODE_BUGCHK 1 252 #define ALPHA_IF_CODE_GENTRAP 2 253 #define ALPHA_IF_CODE_FEN 3 254 #define ALPHA_IF_CODE_OPDEC 4 255 256 /* 257 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 258 */ 259 260 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 261 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 262 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 263 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 264 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 265 266 /* 267 * Bits used in the amask instruction [EV56 and later] 268 */ 269 270 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */ 271 #define ALPHA_AMASK_CIX 0x0002 /* count extension */ 272 #define ALPHA_AMASK_MAX 0x0100 /* multimedia extension */ 273 274 /* 275 * Chip family IDs returned by implver instruction 276 */ 277 278 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */ 279 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */ 280 #define ALPHA_IMPLVER_EV6 2 /* EV6 */ 281 282 /* 283 * Misc. support routines. 284 */ 285 const char *alpha_dsr_sysname __P((void)); 286 287 /* 288 * Stubs for Alpha instructions normally inaccessible from C. 289 */ 290 unsigned long alpha_amask __P((unsigned long)); 291 unsigned long alpha_implver __P((void)); 292 unsigned long alpha_rpcc __P((void)); 293 void alpha_mb __P((void)); 294 void alpha_wmb __P((void)); 295 296 u_int8_t alpha_ldbu __P((volatile u_int8_t *)); 297 u_int16_t alpha_ldwu __P((volatile u_int16_t *)); 298 void alpha_stb __P((volatile u_int8_t *, u_int8_t)); 299 void alpha_stw __P((volatile u_int16_t *, u_int16_t)); 300 u_int8_t alpha_sextb __P((u_int8_t)); 301 u_int16_t alpha_sextw __P((u_int16_t)); 302 303 /* 304 * Stubs for OSF/1 PALcode operations. 305 */ 306 void alpha_pal_imb __P((void)); 307 void alpha_pal_cflush __P((unsigned long)); 308 void alpha_pal_draina __P((void)); 309 void alpha_pal_halt __P((void)) __attribute__((__noreturn__)); 310 unsigned long alpha_pal_rdmces __P((void)); 311 unsigned long alpha_pal_rdps __P((void)); 312 unsigned long alpha_pal_rdusp __P((void)); 313 unsigned long alpha_pal_rdval __P((void)); 314 unsigned long alpha_pal_swpipl __P((unsigned long)); 315 unsigned long _alpha_pal_swpipl __P((unsigned long)); /* for profiling */ 316 void alpha_pal_tbi __P((unsigned long, vm_offset_t)); 317 unsigned long alpha_pal_whami __P((void)); 318 void alpha_pal_wrent __P((void *, unsigned long)); 319 void alpha_pal_wrfen __P((unsigned long)); 320 void alpha_pal_wripir __P((unsigned long)); 321 void alpha_pal_wrusp __P((unsigned long)); 322 void alpha_pal_wrvptptr __P((unsigned long)); 323 void alpha_pal_wrmces __P((unsigned long)); 324 void alpha_pal_wrval __P((unsigned long)); 325 326 #endif /* __ALPHA_ALPHA_CPU_H__ */ 327
Indexes created Tue Sep 30 11:09:46 GMT 2025