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alpha_cpu.h revision 1.20 
      1 /* $NetBSD: alpha_cpu.h,v 1.20 1998/07/08 16:46:51 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #ifndef __ALPHA_ALPHA_CPU_H__
     31 #define	__ALPHA_ALPHA_CPU_H__
     32 
     33 /*
     34  * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
     35  *
     36  * Definitions for:
     37  *
     38  *	Process Control Block
     39  *	Interrupt/Exception/Syscall Stack Frame
     40  *	Processor Status Register
     41  *	Machine Check Error Summary Register
     42  *	Machine Check Logout Area
     43  *	Per CPU state Management of Machine Check Handling
     44  *	Virtual Memory Management
     45  *	Kernel Entry Vectors
     46  *	MMCSR Fault Type Codes
     47  *	Translation Buffer Invalidation
     48  *
     49  * and miscellaneous PALcode operations.
     50  */
     51 
     52 
     53 /*
     54  * Process Control Block definitions [OSF/1 PALcode Specific]
     55  */
     56 
     57 struct alpha_pcb {
     58 	unsigned long	apcb_ksp;	/* kernel stack ptr */
     59 	unsigned long	apcb_usp;	/* user stack ptr */
     60 	unsigned long	apcb_ptbr;	/* page table base reg */
     61 	unsigned int	apcb_cpc;	/* charged process cycles */
     62 	unsigned int	apcb_asn;	/* address space number */
     63 	unsigned long	apcb_unique;	/* process unique value */
     64 	unsigned long	apcb_flags;	/* flags; see below */
     65 	unsigned long	apcb_decrsv0;	/* DEC reserved */
     66 	unsigned long	apcb_decrsv1;	/* DEC reserved */
     67 };
     68 
     69 #define	ALPHA_PCB_FLAGS_FEN	0x0000000000000001
     70 #define	ALPHA_PCB_FLAGS_PME	0x4000000000000000
     71 
     72 /*
     73  * Interrupt/Exception/Syscall "Hardware" (really PALcode)
     74  * Stack Frame definitions
     75  *
     76  * These are quadword offsets from the sp on kernel entry, i.e.
     77  * to get to the value in question you access (sp + (offset * 8)).
     78  *
     79  * On syscall entry, A0-A2 aren't written to memory but space
     80  * _is_ reserved for them.
     81  */
     82 
     83 #define	ALPHA_HWFRAME_PS	0	/* processor status register */
     84 #define	ALPHA_HWFRAME_PC	1	/* program counter */
     85 #define	ALPHA_HWFRAME_GP	2	/* global pointer */
     86 #define	ALPHA_HWFRAME_A0	3	/* a0 */
     87 #define	ALPHA_HWFRAME_A1	4	/* a1 */
     88 #define	ALPHA_HWFRAME_A2	5	/* a2 */
     89 
     90 #define	ALPHA_HWFRAME_SIZE	6	/* 6 8-byte words */
     91 
     92 /*
     93  * Processor Status Register [OSF/1 PALcode Specific]
     94  *
     95  * Includes user/kernel mode bit, interrupt priority levels, etc.
     96  */
     97 
     98 #define	ALPHA_PSL_USERMODE	0x0008		/* set -> user mode */
     99 #define	ALPHA_PSL_IPL_MASK	0x0007		/* interrupt level mask */
    100 
    101 #define	ALPHA_PSL_IPL_0		0x0000		/* all interrupts enabled */
    102 #define	ALPHA_PSL_IPL_SOFT	0x0001		/* software ints disabled */
    103 #define	ALPHA_PSL_IPL_IO	0x0004		/* I/O dev ints disabled */
    104 #define	ALPHA_PSL_IPL_CLOCK	0x0005		/* clock ints disabled */
    105 #define	ALPHA_PSL_IPL_HIGH	0x0006		/* all but mchecks disabled */
    106 
    107 #define	ALPHA_PSL_MUST_BE_ZERO	0xfffffffffffffff0
    108 
    109 /* Convenience constants: what must be set/clear in user mode */
    110 #define	ALPHA_PSL_USERSET	ALPHA_PSL_USERMODE
    111 #define	ALPHA_PSL_USERCLR	(ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
    112 
    113 /*
    114  * Interrupt Type Code Definitions [OSF/1 PALcode Specific]
    115  */
    116 
    117 #define	ALPHA_INTR_XPROC	0	/* interprocessor interrupt */
    118 #define	ALPHA_INTR_CLOCK	1	/* clock interrupt */
    119 #define	ALPHA_INTR_ERROR	2	/* correctable error or mcheck */
    120 #define	ALPHA_INTR_DEVICE	3	/* device interrupt */
    121 #define	ALPHA_INTR_PERF		4	/* performance counter */
    122 #define	ALPHA_INTR_PASSIVE	5	/* passive release */
    123 
    124 /*
    125  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    126  *
    127  * The following bits are values as read.  On write, _PCE, _SCE, and
    128  * _MIP are "write 1 to clear."
    129  */
    130 
    131 #define	ALPHA_MCES_IMP							\
    132     0xffffffff00000000	/* impl. dependent */
    133 #define	ALPHA_MCES_RSVD							\
    134     0x00000000ffffffe0	/* reserved */
    135 #define	ALPHA_MCES_DSC							\
    136     0x0000000000000010	/* disable system correctable error reporting */
    137 #define	ALPHA_MCES_DPC							\
    138     0x0000000000000008	/* disable processor correctable error reporting */
    139 #define	ALPHA_MCES_PCE							\
    140     0x0000000000000004	/* processor correctable error in progress */
    141 #define	ALPHA_MCES_SCE							\
    142     0x0000000000000002	/* system correctable error in progress */
    143 #define	ALPHA_MCES_MIP							\
    144     0x0000000000000001	/* machine check in progress */
    145 
    146 /*
    147  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    148  *
    149  * Note that these are *generic* OSF/1 PALcode specific defines. There are
    150  * platform variations to these entities.
    151  */
    152 
    153 struct alpha_logout_area {
    154 	unsigned int	la_frame_size;		/* frame size */
    155 	unsigned int	la_flags;		/* flags; see below */
    156 	unsigned int	la_cpu_offset;		/* offset to cpu area */
    157 	unsigned int	la_system_offset;	/* offset to system area */
    158 };
    159 
    160 #define	ALPHA_LOGOUT_FLAGS_RETRY	0x80000000	/* OK to continue */
    161 #define	ALPHA_LOGOUT_FLAGS_SE		0x40000000	/* second error */
    162 #define	ALPHA_LOGOUT_FLAGS_SBZ		0x3fffffff	/* should be zero */
    163 
    164 #define	ALPHA_LOGOUT_NOT_BUILT						\
    165     (struct alpha_logout_area *)0xffffffffffffffff)
    166 
    167 #define	ALPHA_LOGOUT_PAL_AREA(lap)					\
    168     (unsigned long *)((unsigned char *)(lap) + 16)
    169 #define	ALPHA_LOGOUT_PAL_SIZE(lap)					\
    170     ((lap)->la_cpu_offset - 16)
    171 #define	ALPHA_LOGOUT_CPU_AREA(lap)					\
    172     (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
    173 #define	ALPHA_LOGOUT_CPU_SIZE(lap)					\
    174     ((lap)->la_system_offset - (lap)->la_cpu_offset)
    175 #define	ALPHA_LOGOUT_SYSTEM_AREA(lap)					\
    176     (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
    177 #define	ALPHA_LOGOUT_SYSTEM_SIZE(lap)					\
    178     ((lap)->la_frame_size - (lap)->la_system_offset)
    179 
    180 /* types of machine checks */
    181 #define	ALPHA_SYS_ERROR		0x620	/* System correctable error	*/
    182 #define	ALPHA_PROC_ERROR	0x630	/* Processor correctable error	*/
    183 #define	ALPHA_SYS_MCHECK	0x660	/* System machine check		*/
    184 #define	ALPHA_PROC_MCHECK	0x670	/* Processor machine check	*/
    185 
    186 /* Per-CPU info for handling machine checks, an array of which		*/
    187 /* is allocated early in startup					*/
    188 struct mchkinfo {
    189 	volatile u_int		mc_expected;	/* machine check expected */
    190 	volatile u_int		mc_received;	/* machine check received */
    191 	/*
    192 	 * We don't really need more info at this time.
    193 	 */
    194 };
    195 
    196 /*
    197  * Virtual Memory Management definitions [OSF/1 PALcode Specific]
    198  *
    199  * Includes user and kernel space addresses and information,
    200  * page table entry definitions, etc.
    201  *
    202  * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
    203  */
    204 
    205 #define	ALPHA_PGSHIFT		13
    206 #define	ALPHA_PGBYTES		(1 << ALPHA_PGSHIFT)
    207 
    208 #define	ALPHA_USEG_BASE		0			/* virtual */
    209 #define	ALPHA_USEG_END		0x000003ffffffffff
    210 
    211 #define	ALPHA_K0SEG_BASE	0xfffffc0000000000	/* direct-mapped */
    212 #define	ALPHA_K0SEG_END		0xfffffdffffffffff
    213 #define	ALPHA_K1SEG_BASE	0xfffffe0000000000	/* virtual */
    214 #define	ALPHA_K1SEG_END		0xffffffffffffffff
    215 
    216 #define ALPHA_K0SEG_TO_PHYS(x)	((x) & ~ALPHA_K0SEG_BASE)
    217 #define ALPHA_PHYS_TO_K0SEG(x)	((x) | ALPHA_K0SEG_BASE)
    218 
    219 #define	ALPHA_PTE_VALID			0x0001
    220 
    221 #define	ALPHA_PTE_FAULT_ON_READ		0x0002
    222 #define	ALPHA_PTE_FAULT_ON_WRITE	0x0004
    223 #define	ALPHA_PTE_FAULT_ON_EXECUTE	0x0008
    224 
    225 #define	ALPHA_PTE_ASM			0x0010		/* addr. space match */
    226 #define	ALPHA_PTE_GRANULARITY		0x0060		/* granularity hint */
    227 
    228 #define	ALPHA_PTE_PROT			0xff00
    229 #define	ALPHA_PTE_KR			0x0100
    230 #define	ALPHA_PTE_UR			0x0200
    231 #define	ALPHA_PTE_KW			0x1000
    232 #define	ALPHA_PTE_UW			0x2000
    233 
    234 #define	ALPHA_PTE_WRITE			(ALPHA_PTE_KW | ALPHA_PTE_UW)
    235 
    236 #define	ALPHA_PTE_SOFTWARE		0x00000000ffff0000
    237 
    238 #define	ALPHA_PTE_PFN			0xffffffff00000000
    239 
    240 #define	ALPHA_PTE_TO_PFN(pte)		((pte) >> 32)
    241 #define	ALPHA_PTE_FROM_PFN(pfn)		((pfn) << 32)
    242 
    243 typedef unsigned long alpha_pt_entry_t;
    244 
    245 /*
    246  * Kernel Entry Vectors.  [OSF/1 PALcode Specific]
    247  */
    248 
    249 #define	ALPHA_KENTRY_INT	0
    250 #define	ALPHA_KENTRY_ARITH	1
    251 #define	ALPHA_KENTRY_MM		2
    252 #define	ALPHA_KENTRY_IF		3
    253 #define	ALPHA_KENTRY_UNA	4
    254 #define	ALPHA_KENTRY_SYS	5
    255 
    256 /*
    257  * MMCSR Fault Type Codes.  [OSF/1 PALcode Specific]
    258  */
    259 
    260 #define	ALPHA_MMCSR_INVALTRANS	0
    261 #define	ALPHA_MMCSR_ACCESS	1
    262 #define	ALPHA_MMCSR_FOR		2
    263 #define	ALPHA_MMCSR_FOE		3
    264 #define	ALPHA_MMCSR_FOW		4
    265 
    266 /*
    267  * Instruction Fault Type Codes.  [OSF/1 PALcode Specific]
    268  */
    269 
    270 #define	ALPHA_IF_CODE_BPT	0
    271 #define	ALPHA_IF_CODE_BUGCHK	1
    272 #define	ALPHA_IF_CODE_GENTRAP	2
    273 #define	ALPHA_IF_CODE_FEN	3
    274 #define	ALPHA_IF_CODE_OPDEC	4
    275 
    276 /*
    277  * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
    278  */
    279 
    280 #define	ALPHA_TBIA()	alpha_pal_tbi(-2, 0)		/* all TB entries */
    281 #define	ALPHA_TBIAP()	alpha_pal_tbi(-1, 0)		/* all per-process */
    282 #define	ALPHA_TBISI(va)	alpha_pal_tbi(1, (va))		/* ITB entry for va */
    283 #define	ALPHA_TBISD(va)	alpha_pal_tbi(2, (va))		/* DTB entry for va */
    284 #define	ALPHA_TBIS(va)	alpha_pal_tbi(3, (va))		/* all for va */
    285 
    286 /*
    287  * Bits used in the amask instruction [EV56 and later]
    288  */
    289 
    290 #define	ALPHA_AMASK_BWX		0x0001		/* byte/word extension */
    291 #define	ALPHA_AMASK_CIX		0x0002		/* count extension */
    292 #define	ALPHA_AMASK_MAX		0x0100		/* multimedia extension */
    293 
    294 /*
    295  * Chip family IDs returned by implver instruction
    296  */
    297 
    298 #define	ALPHA_IMPLVER_EV4	0		/* LCA/EV4/EV45 */
    299 #define	ALPHA_IMPLVER_EV5	1		/* EV5/EV56/PCA56 */
    300 #define	ALPHA_IMPLVER_EV6	2		/* EV6 */
    301 
    302 /*
    303  * Misc. support routines.
    304  */
    305 const char	*alpha_dsr_sysname __P((void));
    306 
    307 /*
    308  * Stubs for Alpha instructions normally inaccessible from C.
    309  */
    310 unsigned long	alpha_amask __P((unsigned long));
    311 unsigned long	alpha_implver __P((void));
    312 unsigned long	alpha_rpcc __P((void));
    313 void		alpha_mb __P((void));
    314 void		alpha_wmb __P((void));
    315 
    316 u_int8_t	alpha_ldbu __P((volatile u_int8_t *));
    317 u_int16_t	alpha_ldwu __P((volatile u_int16_t *));
    318 void		alpha_stb __P((volatile u_int8_t *, u_int8_t));
    319 void		alpha_stw __P((volatile u_int16_t *, u_int16_t));
    320 u_int8_t	alpha_sextb __P((u_int8_t));
    321 u_int16_t	alpha_sextw __P((u_int16_t));
    322 
    323 /*
    324  * Stubs for atomic operations that must be implemented in assembly.
    325  */
    326 void		alpha_atomic_setbits_q __P((unsigned long *, unsigned long));
    327 void		alpha_atomic_clearbits_q __P((unsigned long *, unsigned long));
    328 
    329 /*
    330  * Stubs for OSF/1 PALcode operations.
    331  */
    332 void		alpha_pal_imb __P((void));
    333 void		alpha_pal_cflush __P((unsigned long));
    334 void		alpha_pal_draina __P((void));
    335 void		alpha_pal_halt __P((void)) __attribute__((__noreturn__));
    336 unsigned long	alpha_pal_rdmces __P((void));
    337 unsigned long	alpha_pal_rdps __P((void));
    338 unsigned long	alpha_pal_rdusp __P((void));
    339 unsigned long	alpha_pal_rdval __P((void));
    340 unsigned long	alpha_pal_swpctx __P((unsigned long));
    341 unsigned long	alpha_pal_swpipl __P((unsigned long));
    342 unsigned long	_alpha_pal_swpipl __P((unsigned long));	/* for profiling */
    343 void		alpha_pal_tbi __P((unsigned long, vm_offset_t));
    344 unsigned long	alpha_pal_whami __P((void));
    345 void		alpha_pal_wrent __P((void *, unsigned long));
    346 void		alpha_pal_wrfen __P((unsigned long));
    347 void		alpha_pal_wripir __P((unsigned long));
    348 void		alpha_pal_wrusp __P((unsigned long));
    349 void		alpha_pal_wrvptptr __P((unsigned long));
    350 void		alpha_pal_wrmces __P((unsigned long));
    351 void		alpha_pal_wrval __P((unsigned long));
    352 
    353 #endif /* __ALPHA_ALPHA_CPU_H__ */
    354