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alpha_cpu.h revision 1.40 
      1 /* $NetBSD: alpha_cpu.h,v 1.40 2000/06/08 02:53:47 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #ifndef __ALPHA_ALPHA_CPU_H__
     31 #define	__ALPHA_ALPHA_CPU_H__
     32 
     33 /*
     34  * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
     35  *
     36  * Definitions for:
     37  *
     38  *	Process Control Block
     39  *	Interrupt/Exception/Syscall Stack Frame
     40  *	Processor Status Register
     41  *	Machine Check Error Summary Register
     42  *	Machine Check Logout Area
     43  *	Per CPU state Management of Machine Check Handling
     44  *	Virtual Memory Management
     45  *	Kernel Entry Vectors
     46  *	MMCSR Fault Type Codes
     47  *	Translation Buffer Invalidation
     48  *
     49  * and miscellaneous PALcode operations.
     50  */
     51 
     52 
     53 /*
     54  * Process Control Block definitions [OSF/1 PALcode Specific]
     55  */
     56 
     57 struct alpha_pcb {
     58 	unsigned long	apcb_ksp;	/* kernel stack ptr */
     59 	unsigned long	apcb_usp;	/* user stack ptr */
     60 	unsigned long	apcb_ptbr;	/* page table base reg */
     61 	unsigned int	apcb_cpc;	/* charged process cycles */
     62 	unsigned int	apcb_asn;	/* address space number */
     63 	unsigned long	apcb_unique;	/* process unique value */
     64 #define	apcb_backup_ksp	apcb_unique	/* backup kernel stack ptr */
     65 	unsigned long	apcb_flags;	/* flags; see below */
     66 	unsigned long	apcb_decrsv0;	/* DEC reserved */
     67 	unsigned long	apcb_decrsv1;	/* DEC reserved */
     68 };
     69 
     70 #define	ALPHA_PCB_FLAGS_FEN	0x0000000000000001
     71 #define	ALPHA_PCB_FLAGS_PME	0x4000000000000000
     72 
     73 /*
     74  * Interrupt/Exception/Syscall "Hardware" (really PALcode)
     75  * Stack Frame definitions
     76  *
     77  * These are quadword offsets from the sp on kernel entry, i.e.
     78  * to get to the value in question you access (sp + (offset * 8)).
     79  *
     80  * On syscall entry, A0-A2 aren't written to memory but space
     81  * _is_ reserved for them.
     82  */
     83 
     84 #define	ALPHA_HWFRAME_PS	0	/* processor status register */
     85 #define	ALPHA_HWFRAME_PC	1	/* program counter */
     86 #define	ALPHA_HWFRAME_GP	2	/* global pointer */
     87 #define	ALPHA_HWFRAME_A0	3	/* a0 */
     88 #define	ALPHA_HWFRAME_A1	4	/* a1 */
     89 #define	ALPHA_HWFRAME_A2	5	/* a2 */
     90 
     91 #define	ALPHA_HWFRAME_SIZE	6	/* 6 8-byte words */
     92 
     93 /*
     94  * Processor Status Register [OSF/1 PALcode Specific]
     95  *
     96  * Includes user/kernel mode bit, interrupt priority levels, etc.
     97  */
     98 
     99 #define	ALPHA_PSL_USERMODE	0x0008		/* set -> user mode */
    100 #define	ALPHA_PSL_IPL_MASK	0x0007		/* interrupt level mask */
    101 
    102 #define	ALPHA_PSL_IPL_0		0x0000		/* all interrupts enabled */
    103 #define	ALPHA_PSL_IPL_SOFT	0x0001		/* software ints disabled */
    104 #define	ALPHA_PSL_IPL_IO	0x0004		/* I/O dev ints disabled */
    105 #define	ALPHA_PSL_IPL_CLOCK	0x0005		/* clock ints disabled */
    106 #define	ALPHA_PSL_IPL_HIGH	0x0006		/* all but mchecks disabled */
    107 
    108 #define	ALPHA_PSL_MUST_BE_ZERO	0xfffffffffffffff0
    109 
    110 /* Convenience constants: what must be set/clear in user mode */
    111 #define	ALPHA_PSL_USERSET	ALPHA_PSL_USERMODE
    112 #define	ALPHA_PSL_USERCLR	(ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
    113 
    114 /*
    115  * Interrupt Type Code Definitions [OSF/1 PALcode Specific]
    116  */
    117 
    118 #define	ALPHA_INTR_XPROC	0	/* interprocessor interrupt */
    119 #define	ALPHA_INTR_CLOCK	1	/* clock interrupt */
    120 #define	ALPHA_INTR_ERROR	2	/* correctable error or mcheck */
    121 #define	ALPHA_INTR_DEVICE	3	/* device interrupt */
    122 #define	ALPHA_INTR_PERF		4	/* performance counter */
    123 #define	ALPHA_INTR_PASSIVE	5	/* passive release */
    124 
    125 /*
    126  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    127  *
    128  * The following bits are values as read.  On write, _PCE, _SCE, and
    129  * _MIP are "write 1 to clear."
    130  */
    131 
    132 #define	ALPHA_MCES_IMP							\
    133     0xffffffff00000000	/* impl. dependent */
    134 #define	ALPHA_MCES_RSVD							\
    135     0x00000000ffffffe0	/* reserved */
    136 #define	ALPHA_MCES_DSC							\
    137     0x0000000000000010	/* disable system correctable error reporting */
    138 #define	ALPHA_MCES_DPC							\
    139     0x0000000000000008	/* disable processor correctable error reporting */
    140 #define	ALPHA_MCES_PCE							\
    141     0x0000000000000004	/* processor correctable error in progress */
    142 #define	ALPHA_MCES_SCE							\
    143     0x0000000000000002	/* system correctable error in progress */
    144 #define	ALPHA_MCES_MIP							\
    145     0x0000000000000001	/* machine check in progress */
    146 
    147 /*
    148  * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
    149  *
    150  * Note that these are *generic* OSF/1 PALcode specific defines. There are
    151  * platform variations to these entities.
    152  */
    153 
    154 struct alpha_logout_area {
    155 	unsigned int	la_frame_size;		/* frame size */
    156 	unsigned int	la_flags;		/* flags; see below */
    157 	unsigned int	la_cpu_offset;		/* offset to cpu area */
    158 	unsigned int	la_system_offset;	/* offset to system area */
    159 };
    160 
    161 #define	ALPHA_LOGOUT_FLAGS_RETRY	0x80000000	/* OK to continue */
    162 #define	ALPHA_LOGOUT_FLAGS_SE		0x40000000	/* second error */
    163 #define	ALPHA_LOGOUT_FLAGS_SBZ		0x3fffffff	/* should be zero */
    164 
    165 #define	ALPHA_LOGOUT_NOT_BUILT						\
    166     (struct alpha_logout_area *)0xffffffffffffffff)
    167 
    168 #define	ALPHA_LOGOUT_PAL_AREA(lap)					\
    169     (unsigned long *)((unsigned char *)(lap) + 16)
    170 #define	ALPHA_LOGOUT_PAL_SIZE(lap)					\
    171     ((lap)->la_cpu_offset - 16)
    172 #define	ALPHA_LOGOUT_CPU_AREA(lap)					\
    173     (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
    174 #define	ALPHA_LOGOUT_CPU_SIZE(lap)					\
    175     ((lap)->la_system_offset - (lap)->la_cpu_offset)
    176 #define	ALPHA_LOGOUT_SYSTEM_AREA(lap)					\
    177     (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
    178 #define	ALPHA_LOGOUT_SYSTEM_SIZE(lap)					\
    179     ((lap)->la_frame_size - (lap)->la_system_offset)
    180 
    181 /* types of machine checks */
    182 #define	ALPHA_SYS_ERROR		0x620	/* System correctable error	*/
    183 #define	ALPHA_PROC_ERROR	0x630	/* Processor correctable error	*/
    184 #define	ALPHA_SYS_MCHECK	0x660	/* System machine check		*/
    185 #define	ALPHA_PROC_MCHECK	0x670	/* Processor machine check	*/
    186 
    187 /*
    188  * Virtual Memory Management definitions [OSF/1 PALcode Specific]
    189  *
    190  * Includes user and kernel space addresses and information,
    191  * page table entry definitions, etc.
    192  *
    193  * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
    194  */
    195 
    196 #define	ALPHA_PGSHIFT		13
    197 #define	ALPHA_PGBYTES		(1 << ALPHA_PGSHIFT)
    198 
    199 #define	ALPHA_USEG_BASE		0			/* virtual */
    200 #define	ALPHA_USEG_END		0x000003ffffffffff
    201 
    202 #define	ALPHA_K0SEG_BASE	0xfffffc0000000000	/* direct-mapped */
    203 #define	ALPHA_K0SEG_END		0xfffffdffffffffff
    204 #define	ALPHA_K1SEG_BASE	0xfffffe0000000000	/* virtual */
    205 #define	ALPHA_K1SEG_END		0xffffffffffffffff
    206 
    207 #define ALPHA_K0SEG_TO_PHYS(x)	((x) & ~ALPHA_K0SEG_BASE)
    208 #define ALPHA_PHYS_TO_K0SEG(x)	((x) | ALPHA_K0SEG_BASE)
    209 
    210 #define	ALPHA_PTE_VALID			0x0001
    211 
    212 #define	ALPHA_PTE_FAULT_ON_READ		0x0002
    213 #define	ALPHA_PTE_FAULT_ON_WRITE	0x0004
    214 #define	ALPHA_PTE_FAULT_ON_EXECUTE	0x0008
    215 
    216 #define	ALPHA_PTE_ASM			0x0010		/* addr. space match */
    217 #define	ALPHA_PTE_GRANULARITY		0x0060		/* granularity hint */
    218 
    219 #define	ALPHA_PTE_PROT			0xff00
    220 #define	ALPHA_PTE_KR			0x0100
    221 #define	ALPHA_PTE_UR			0x0200
    222 #define	ALPHA_PTE_KW			0x1000
    223 #define	ALPHA_PTE_UW			0x2000
    224 
    225 #define	ALPHA_PTE_WRITE			(ALPHA_PTE_KW | ALPHA_PTE_UW)
    226 
    227 #define	ALPHA_PTE_SOFTWARE		0x00000000ffff0000
    228 #define	ALPHA_PTE_PALCODE		(~ALPHA_PTE_SOFTWARE) /* shorthand */
    229 
    230 #define	ALPHA_PTE_PFN			0xffffffff00000000
    231 
    232 #define	ALPHA_PTE_TO_PFN(pte)		((pte) >> 32)
    233 #define	ALPHA_PTE_FROM_PFN(pfn)		((pfn) << 32)
    234 
    235 typedef unsigned long alpha_pt_entry_t;
    236 
    237 /*
    238  * Kernel Entry Vectors.  [OSF/1 PALcode Specific]
    239  */
    240 
    241 #define	ALPHA_KENTRY_INT	0
    242 #define	ALPHA_KENTRY_ARITH	1
    243 #define	ALPHA_KENTRY_MM		2
    244 #define	ALPHA_KENTRY_IF		3
    245 #define	ALPHA_KENTRY_UNA	4
    246 #define	ALPHA_KENTRY_SYS	5
    247 
    248 /*
    249  * MMCSR Fault Type Codes.  [OSF/1 PALcode Specific]
    250  */
    251 
    252 #define	ALPHA_MMCSR_INVALTRANS	0
    253 #define	ALPHA_MMCSR_ACCESS	1
    254 #define	ALPHA_MMCSR_FOR		2
    255 #define	ALPHA_MMCSR_FOE		3
    256 #define	ALPHA_MMCSR_FOW		4
    257 
    258 /*
    259  * Instruction Fault Type Codes.  [OSF/1 PALcode Specific]
    260  */
    261 
    262 #define	ALPHA_IF_CODE_BPT	0
    263 #define	ALPHA_IF_CODE_BUGCHK	1
    264 #define	ALPHA_IF_CODE_GENTRAP	2
    265 #define	ALPHA_IF_CODE_FEN	3
    266 #define	ALPHA_IF_CODE_OPDEC	4
    267 
    268 /*
    269  * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
    270  */
    271 
    272 #define	ALPHA_TBIA()	alpha_pal_tbi(-2, 0)		/* all TB entries */
    273 #define	ALPHA_TBIAP()	alpha_pal_tbi(-1, 0)		/* all per-process */
    274 #define	ALPHA_TBISI(va)	alpha_pal_tbi(1, (va))		/* ITB entry for va */
    275 #define	ALPHA_TBISD(va)	alpha_pal_tbi(2, (va))		/* DTB entry for va */
    276 #define	ALPHA_TBIS(va)	alpha_pal_tbi(3, (va))		/* all for va */
    277 
    278 /*
    279  * Bits used in the amask instruction [EV56 and later]
    280  */
    281 
    282 #define	ALPHA_AMASK_BWX		0x0001		/* byte/word extension */
    283 #define	ALPHA_AMASK_FIX		0x0002		/* floating point conv. ext. */
    284 #define	ALPHA_AMASK_CIX		0x0004		/* count extension */
    285 #define	ALPHA_AMASK_MVI		0x0100		/* multimedia extension */
    286 #define	ALPHA_AMASK_PAT		0x0200		/* precise arith. traps */
    287 
    288 #define	ALPHA_AMASK_ALL		(ALPHA_AMASK_BWX|ALPHA_AMASK_FIX|	\
    289 				 ALPHA_AMASK_CIX|ALPHA_AMASK_MVI|	\
    290 				 ALPHA_AMASK_PAT)
    291 
    292 #define	ALPHA_AMASK_BITS						\
    293     "\20\12PAT\11MVI\3CIX\2FIX\1BWX"
    294 
    295 /*
    296  * Chip family IDs returned by implver instruction
    297  */
    298 
    299 #define	ALPHA_IMPLVER_EV4	0		/* LCA/EV4/EV45 */
    300 #define	ALPHA_IMPLVER_EV5	1		/* EV5/EV56/PCA56 */
    301 #define	ALPHA_IMPLVER_EV6	2		/* EV6 */
    302 
    303 /*
    304  * Maximum processor ID we allow from `whami', and related constants.
    305  *
    306  * XXX This is not really processor or PALcode specific, but this is
    307  * a convenient place to put these definitions.
    308  *
    309  * XXX This is clipped at 63 so that we can use `long's for proc bitmasks.
    310  */
    311 
    312 #define	ALPHA_WHAMI_MAXID	63
    313 #define	ALPHA_MAXPROCS		(ALPHA_WHAMI_MAXID + 1)
    314 
    315 /*
    316  * Misc. support routines.
    317  */
    318 const char	*alpha_dsr_sysname __P((void));
    319 
    320 /*
    321  * Stubs for Alpha instructions normally inaccessible from C.
    322  */
    323 unsigned long	alpha_amask(unsigned long);
    324 unsigned long	alpha_implver(void);
    325 
    326 static __inline unsigned long
    327 alpha_rpcc(void)
    328 {
    329 	unsigned long v0;
    330 
    331 	__asm __volatile("rpcc %0" : "=r" (v0));
    332 	return (v0);
    333 }
    334 
    335 #define	alpha_mb()	__asm __volatile("mb" : : : "memory")
    336 #define	alpha_wmb()	__asm __volatile("mb" : : : "memory")	/* XXX */
    337 
    338 /*
    339  * Stubs for OSF/1 PALcode operations.
    340  */
    341 #include <machine/pal.h>
    342 
    343 void		alpha_pal_cflush(unsigned long);
    344 void		alpha_pal_halt(void) __attribute__((__noreturn__));
    345 unsigned long	_alpha_pal_swpipl(unsigned long);	/* for profiling */
    346 void		alpha_pal_wrent(void *, unsigned long);
    347 void		alpha_pal_wrvptptr(unsigned long);
    348 
    349 #define	alpha_pal_draina() __asm __volatile("call_pal %0 # PAL_draina"	\
    350 				: : "i" (PAL_draina) : "memory")
    351 
    352 #define	alpha_pal_imb()	__asm __volatile("call_pal %0 # PAL_imb"	\
    353 				: : "i" (PAL_imb) : "memory")
    354 
    355 static __inline unsigned long
    356 alpha_pal_rdmces(void)
    357 {
    358 	register unsigned long v0 __asm("$0");
    359 
    360 	__asm __volatile("call_pal %1 # PAL_OSF1_rdmces"
    361 		: "=r" (v0)
    362 		: "i" (PAL_OSF1_rdmces)
    363 		/* clobbers t0, t8..t11 */
    364 		: "$1", "$22", "$23", "$24", "$25");
    365 
    366 	return (v0);
    367 }
    368 
    369 static __inline unsigned long
    370 alpha_pal_rdps(void)
    371 {
    372 	register unsigned long v0 __asm("$0");
    373 
    374 	__asm __volatile("call_pal %1 # PAL_OSF1_rdps"
    375 		: "=r" (v0)
    376 		: "i" (PAL_OSF1_rdps)
    377 		/* clobbers t0, t8..t11 */
    378 		: "$1", "$22", "$23", "$24", "$25");
    379 
    380 	return (v0);
    381 }
    382 
    383 static __inline unsigned long
    384 alpha_pal_rdusp(void)
    385 {
    386 	register unsigned long v0 __asm("$0");
    387 
    388 	__asm __volatile("call_pal %1 # PAL_OSF1_rdusp"
    389 		: "=r" (v0)
    390 		: "i" (PAL_OSF1_rdusp)
    391 		/* clobbers t0, t8..t11 */
    392 		: "$1", "$22", "$23", "$24", "$25");
    393 
    394 	return (v0);
    395 }
    396 
    397 static __inline unsigned long
    398 alpha_pal_rdval(void)
    399 {
    400 	register unsigned long v0 __asm("$0");
    401 
    402 	__asm __volatile("call_pal %1 # PAL_OSF1_rdval"
    403 		: "=r" (v0)
    404 		: "i" (PAL_OSF1_rdval)
    405 		/* clobbers t0, t8..t11 */
    406 		: "$1", "$22", "$23", "$24", "$25");
    407 
    408 	return (v0);
    409 }
    410 
    411 static __inline unsigned long
    412 alpha_pal_swpctx(unsigned long ctx)
    413 {
    414 	register unsigned long a0 __asm("$16") = ctx;
    415 	register unsigned long v0 __asm("$0");
    416 
    417 	__asm __volatile("call_pal %2 # PAL_OSF1_swpctx"
    418 		: "=r" (a0), "=r" (v0)
    419 		: "i" (PAL_OSF1_swpctx), "0" (a0)
    420 		/* clobbers t0, t8..t11, a0 (above) */
    421 		: "$1", "$22", "$23", "$24", "$25");
    422 
    423 	return (v0);
    424 }
    425 
    426 static __inline unsigned long
    427 alpha_pal_swpipl(unsigned long ipl)
    428 {
    429 	register unsigned long a0 __asm("$16") = ipl;
    430 	register unsigned long v0 __asm("$0");
    431 
    432 	__asm __volatile("call_pal %2 # PAL_OSF1_swpipl"
    433 		: "=r" (a0), "=r" (v0)
    434 		: "i" (PAL_OSF1_swpipl), "0" (a0)
    435 		/* clobbers t0, t8..t11, a0 (above) */
    436 		: "$1", "$22", "$23", "$24", "$25");
    437 
    438 	return (v0);
    439 }
    440 
    441 static __inline void
    442 alpha_pal_tbi(unsigned long op, vaddr_t va)
    443 {
    444 	register unsigned long a0 __asm("$16") = op;
    445 	register unsigned long a1 __asm("$17") = va;
    446 
    447 	__asm __volatile("call_pal %2 # PAL_OSF1_tbi"
    448 		: "=r" (a0), "=r" (a1)
    449 		: "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1)
    450 		/* clobbers t0, t8..t11, a0 (above), a1 (above) */
    451 		: "$1", "$22", "$23", "$24", "$25");
    452 }
    453 
    454 static __inline unsigned long
    455 alpha_pal_whami(void)
    456 {
    457 	register unsigned long v0 __asm("$0");
    458 
    459 	__asm __volatile("call_pal %1 # PAL_OSF1_whami"
    460 		: "=r" (v0)
    461 		: "i" (PAL_OSF1_whami)
    462 		/* clobbers t0, t8..t11 */
    463 		: "$1", "$22", "$23", "$24", "$25");
    464 
    465 	return (v0);
    466 }
    467 
    468 static __inline void
    469 alpha_pal_wrfen(unsigned long onoff)
    470 {
    471 	register unsigned long a0 __asm("$16") = onoff;
    472 
    473 	__asm __volatile("call_pal %1 # PAL_OSF1_wrfen"
    474 		: "=r" (a0)
    475 		: "i" (PAL_OSF1_wrfen), "0" (a0)
    476 		/* clobbers t0, t8..t11, a0 (above) */
    477 		: "$1", "$22", "$23", "$24", "$25");
    478 }
    479 
    480 static __inline void
    481 alpha_pal_wripir(unsigned long cpu_id)
    482 {
    483 	register unsigned long a0 __asm("$16") = cpu_id;
    484 
    485 	__asm __volatile("call_pal %1 # PAL_ipir"
    486 		: "=r" (a0)
    487 		: "i" (PAL_ipir), "0" (a0)
    488 		/* clobbers t0, t8..t11, a0 (above) */
    489 		: "$1", "$22", "$23", "$24", "$25");
    490 }
    491 
    492 static __inline void
    493 alpha_pal_wrusp(unsigned long usp)
    494 {
    495 	register unsigned long a0 __asm("$16") = usp;
    496 
    497 	__asm __volatile("call_pal %1 # PAL_OSF1_wrusp"
    498 		: "=r" (a0)
    499 		: "i" (PAL_OSF1_wrusp), "0" (a0)
    500 		/* clobbers t0, t8..t11, a0 (above) */
    501 		: "$1", "$22", "$23", "$24", "$25");
    502 }
    503 
    504 static __inline void
    505 alpha_pal_wrmces(unsigned long mces)
    506 {
    507 	register unsigned long a0 __asm("$16") = mces;
    508 
    509 	__asm __volatile("call_pal %1 # PAL_OSF1_wrmces"
    510 		: "=r" (a0)
    511 		: "i" (PAL_OSF1_wrmces), "0" (a0)
    512 		/* clobbers t0, t8..t11 */
    513 		: "$1", "$22", "$23", "$24", "$25");
    514 }
    515 
    516 static __inline void
    517 alpha_pal_wrval(unsigned long val)
    518 {
    519 	register unsigned long a0 __asm("$16") = val;
    520 
    521 	__asm __volatile("call_pal %1 # PAL_OSF1_wrval"
    522 		: "=r" (a0)
    523 		: "i" (PAL_OSF1_wrval), "0" (a0)
    524 		/* clobbers t0, t8..t11, a0 (above) */
    525 		: "$1", "$22", "$23", "$24", "$25");
    526 }
    527 
    528 #endif /* __ALPHA_ALPHA_CPU_H__ */
    529