alpha_cpu.h revision 1.52
1 /* $NetBSD: alpha_cpu.h,v 1.52 2020/09/29 01:17:22 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #ifndef __ALPHA_ALPHA_CPU_H__ 31 #define __ALPHA_ALPHA_CPU_H__ 32 33 /* 34 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 35 * 36 * Definitions for: 37 * 38 * Process Control Block 39 * Interrupt/Exception/Syscall Stack Frame 40 * Processor Status Register 41 * Machine Check Error Summary Register 42 * Machine Check Logout Area 43 * Per CPU state Management of Machine Check Handling 44 * Virtual Memory Management 45 * Kernel Entry Vectors 46 * MMCSR Fault Type Codes 47 * Translation Buffer Invalidation 48 * 49 * and miscellaneous PALcode operations. 50 */ 51 52 53 /* 54 * Process Control Block definitions [OSF/1 PALcode Specific] 55 */ 56 57 struct alpha_pcb { 58 unsigned long apcb_ksp; /* kernel stack ptr */ 59 unsigned long apcb_usp; /* user stack ptr */ 60 unsigned long apcb_ptbr; /* page table base reg */ 61 unsigned int apcb_cpc; /* charged process cycles */ 62 unsigned int apcb_asn; /* address space number */ 63 unsigned long apcb_unique; /* process unique value */ 64 #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */ 65 unsigned long apcb_flags; /* flags; see below */ 66 unsigned long apcb_decrsv0; /* DEC reserved */ 67 unsigned long apcb_decrsv1; /* DEC reserved */ 68 }; 69 70 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 71 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 72 73 /* 74 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 75 * Stack Frame definitions 76 * 77 * These are quadword offsets from the sp on kernel entry, i.e. 78 * to get to the value in question you access (sp + (offset * 8)). 79 * 80 * On syscall entry, A0-A2 aren't written to memory but space 81 * _is_ reserved for them. 82 */ 83 84 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 85 #define ALPHA_HWFRAME_PC 1 /* program counter */ 86 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 87 #define ALPHA_HWFRAME_A0 3 /* a0 */ 88 #define ALPHA_HWFRAME_A1 4 /* a1 */ 89 #define ALPHA_HWFRAME_A2 5 /* a2 */ 90 91 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 92 93 /* 94 * Processor Status Register [OSF/1 PALcode Specific] 95 * 96 * Includes user/kernel mode bit, interrupt priority levels, etc. 97 * 98 * Processor Status Summary 99 * --------------------------------------------------------------------------- 100 * PS<mode> PS<IPL> Mode Use 101 * --------------------------------------------------------------------------- 102 * 1 0 User User software 103 * 0 0 Kernel System software 104 * 0 1 Kernel System software 105 * 0 2 Kernel System software 106 * 0 3 Kernel Low priority device interrupts 107 * 0 4 Kernel High priority device interrupts 108 * 0 5 Kernel Clock, inter-proc interrupts 109 * 0 6 Kernel Real-time device interrupts 110 * 0 6 Kernel Correctable error reporting 111 * 0 7 Kernel Machine checks 112 */ 113 114 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 115 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 116 117 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 118 #define ALPHA_PSL_IPL_SOFT_LO 0x0001 /* low pri soft ints disabled */ 119 #define ALPHA_PSL_IPL_SOFT_HI 0x0002 /* hi pri soft ints disabled */ 120 #define ALPHA_PSL_IPL_IO_LO 0x0003 /* low pri dev ints disabled */ 121 #define ALPHA_PSL_IPL_IO_HI 0x0004 /* hi pri dev ints disabled */ 122 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 123 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 124 #define ALPHA_PSL_IPL_MCHECK 0x0007 /* machine checks disabled */ 125 126 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 127 128 /* Convenience constants: what must be set/clear in user mode */ 129 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 130 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 131 132 /* 133 * Interrupt Type Code Definitions [OSF/1 PALcode Specific] 134 */ 135 136 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */ 137 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */ 138 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */ 139 #define ALPHA_INTR_DEVICE 3 /* device interrupt */ 140 #define ALPHA_INTR_PERF 4 /* performance counter */ 141 #define ALPHA_INTR_PASSIVE 5 /* passive release */ 142 143 /* 144 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 145 * 146 * The following bits are values as read. On write, _PCE, _SCE, and 147 * _MIP are "write 1 to clear." 148 */ 149 150 #define ALPHA_MCES_IMP \ 151 0xffffffff00000000 /* impl. dependent */ 152 #define ALPHA_MCES_RSVD \ 153 0x00000000ffffffe0 /* reserved */ 154 #define ALPHA_MCES_DSC \ 155 0x0000000000000010 /* disable system correctable error reporting */ 156 #define ALPHA_MCES_DPC \ 157 0x0000000000000008 /* disable processor correctable error reporting */ 158 #define ALPHA_MCES_PCE \ 159 0x0000000000000004 /* processor correctable error in progress */ 160 #define ALPHA_MCES_SCE \ 161 0x0000000000000002 /* system correctable error in progress */ 162 #define ALPHA_MCES_MIP \ 163 0x0000000000000001 /* machine check in progress */ 164 165 /* 166 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 167 * 168 * Note that these are *generic* OSF/1 PALcode specific defines. There are 169 * platform variations to these entities. 170 */ 171 172 struct alpha_logout_area { 173 unsigned int la_frame_size; /* frame size */ 174 unsigned int la_flags; /* flags; see below */ 175 unsigned int la_cpu_offset; /* offset to cpu area */ 176 unsigned int la_system_offset; /* offset to system area */ 177 }; 178 179 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 180 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 181 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 182 183 #define ALPHA_LOGOUT_NOT_BUILT \ 184 (struct alpha_logout_area *)0xffffffffffffffff) 185 186 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 187 (unsigned long *)((unsigned char *)(lap) + 16) 188 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 189 ((lap)->la_cpu_offset - 16) 190 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 191 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 192 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 193 ((lap)->la_system_offset - (lap)->la_cpu_offset) 194 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 195 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 196 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 197 ((lap)->la_frame_size - (lap)->la_system_offset) 198 199 /* types of machine checks */ 200 #define ALPHA_SYS_ERROR 0x620 /* System correctable error */ 201 #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */ 202 #define ALPHA_SYS_MCHECK 0x660 /* System machine check */ 203 #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */ 204 #define ALPHA_ENV_MCHECK 0x680 /* Environmental error */ 205 206 /* 207 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 208 * 209 * Includes user and kernel space addresses and information, 210 * page table entry definitions, etc. 211 * 212 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 213 */ 214 215 #define ALPHA_PGSHIFT 13 216 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 217 218 #define ALPHA_USEG_BASE 0 /* virtual */ 219 #define ALPHA_USEG_END 0x000003ffffffffff 220 221 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 222 #define ALPHA_K0SEG_END 0xfffffdffffffffff 223 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 224 #define ALPHA_K1SEG_END 0xffffffffffffffff 225 226 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 227 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 228 229 #define ALPHA_PTE_VALID 0x0001 230 231 #define ALPHA_PTE_FAULT_ON_READ 0x0002 232 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 233 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 234 235 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 236 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 237 238 #define ALPHA_PTE_PROT 0xff00 239 #define ALPHA_PTE_KR 0x0100 240 #define ALPHA_PTE_UR 0x0200 241 #define ALPHA_PTE_KW 0x1000 242 #define ALPHA_PTE_UW 0x2000 243 244 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 245 246 #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000 247 #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */ 248 249 #define ALPHA_PTE_PFN 0xffffffff00000000 250 251 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 252 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 253 254 typedef unsigned long alpha_pt_entry_t; 255 256 /* 257 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 258 */ 259 260 #define ALPHA_KENTRY_INT 0 261 #define ALPHA_KENTRY_ARITH 1 262 #define ALPHA_KENTRY_MM 2 263 #define ALPHA_KENTRY_IF 3 264 #define ALPHA_KENTRY_UNA 4 265 #define ALPHA_KENTRY_SYS 5 266 267 /* 268 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 269 */ 270 271 #define ALPHA_MMCSR_INVALTRANS 0 272 #define ALPHA_MMCSR_ACCESS 1 273 #define ALPHA_MMCSR_FOR 2 274 #define ALPHA_MMCSR_FOE 3 275 #define ALPHA_MMCSR_FOW 4 276 277 /* 278 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 279 */ 280 281 #define ALPHA_IF_CODE_BPT 0 282 #define ALPHA_IF_CODE_BUGCHK 1 283 #define ALPHA_IF_CODE_GENTRAP 2 284 #define ALPHA_IF_CODE_FEN 3 285 #define ALPHA_IF_CODE_OPDEC 4 286 287 #ifdef _KERNEL 288 289 /* 290 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 291 */ 292 293 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 294 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 295 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 296 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 297 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 298 299 #endif /* _KERNEL */ 300 301 /* 302 * Bits used in the amask instruction [EV56 and later] 303 */ 304 305 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */ 306 #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */ 307 #define ALPHA_AMASK_CIX 0x0004 /* count extension */ 308 #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */ 309 #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */ 310 #define ALPHA_AMASK_PMI 0x1000 /* prefetch w/ modify intent */ 311 312 #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \ 313 ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \ 314 ALPHA_AMASK_PAT|ALPHA_AMASK_PMI) 315 316 #define ALPHA_AMASK_BITS \ 317 "\20\17PMI\12PAT\11MVI\3CIX\2FIX\1BWX" 318 319 /* 320 * Chip family IDs returned by implver instruction 321 */ 322 323 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */ 324 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */ 325 #define ALPHA_IMPLVER_EV6 2 /* EV6 */ 326 #define ALPHA_IMPLVER_EV7 3 /* EV7/EV79 */ 327 328 #ifdef _KERNEL 329 330 /* 331 * Maximum processor ID we allow from `whami', and related constants. 332 * 333 * XXX This is not really processor or PALcode specific, but this is 334 * a convenient place to put these definitions. 335 * 336 * XXX This is clipped at 63 so that we can use `long's for proc bitmasks. 337 */ 338 339 #define ALPHA_WHAMI_MAXID 63 340 #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1) 341 342 /* 343 * Misc. support routines. 344 */ 345 const char *alpha_dsr_sysname(void); 346 347 /* 348 * Stubs for Alpha instructions normally inaccessible from C. 349 */ 350 unsigned long alpha_amask(unsigned long); 351 unsigned long alpha_implver(void); 352 353 #endif /* _KERNEL */ 354 355 /* XXX Expose the insn wrappers to userspace, for now. */ 356 357 static __inline unsigned long 358 alpha_rpcc(void) 359 { 360 unsigned long v0; 361 362 __asm volatile("rpcc %0" : "=r" (v0)); 363 return (v0); 364 } 365 366 #define alpha_mb() __asm volatile("mb" : : : "memory") 367 #define alpha_wmb() __asm volatile("mb" : : : "memory") /* XXX */ 368 369 #if defined(_KERNEL) || defined(_STANDALONE) 370 371 /* 372 * Stubs for OSF/1 PALcode operations. 373 */ 374 #include <machine/pal.h> 375 376 void alpha_pal_cflush(unsigned long); 377 void alpha_pal_halt(void) __attribute__((__noreturn__)); 378 unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */ 379 void alpha_pal_wrent(void *, unsigned long); 380 void alpha_pal_wrvptptr(unsigned long); 381 unsigned long alpha_pal_wtint(unsigned long); 382 383 #define alpha_pal_draina() __asm volatile("call_pal %0 # PAL_draina" \ 384 : : "i" (PAL_draina) : "memory") 385 386 #define alpha_pal_imb() __asm volatile("call_pal %0 # PAL_imb" \ 387 : : "i" (PAL_imb) : "memory") 388 389 static __inline unsigned long 390 alpha_pal_rdmces(void) 391 { 392 register unsigned long v0 __asm("$0"); 393 394 __asm volatile("call_pal %1 # PAL_OSF1_rdmces" 395 : "=r" (v0) 396 : "i" (PAL_OSF1_rdmces) 397 /* clobbers t0, t8..t11 */ 398 : "$1", "$22", "$23", "$24", "$25"); 399 400 return (v0); 401 } 402 403 static __inline unsigned long 404 alpha_pal_rdps(void) 405 { 406 register unsigned long v0 __asm("$0"); 407 408 __asm volatile("call_pal %1 # PAL_OSF1_rdps" 409 : "=r" (v0) 410 : "i" (PAL_OSF1_rdps) 411 /* clobbers t0, t8..t11 */ 412 : "$1", "$22", "$23", "$24", "$25"); 413 414 return (v0); 415 } 416 417 static __inline unsigned long 418 alpha_pal_rdunique(void) 419 { 420 register unsigned long v0 __asm("$0"); 421 422 __asm volatile("call_pal %1 # PAL_rdunique" 423 : "=r" (v0) 424 : "i" (PAL_rdunique)); 425 426 return (v0); 427 } 428 429 static __inline unsigned long 430 alpha_pal_rdusp(void) 431 { 432 register unsigned long v0 __asm("$0"); 433 434 __asm volatile("call_pal %1 # PAL_OSF1_rdusp" 435 : "=r" (v0) 436 : "i" (PAL_OSF1_rdusp) 437 /* clobbers t0, t8..t11 */ 438 : "$1", "$22", "$23", "$24", "$25"); 439 440 return (v0); 441 } 442 443 static __inline unsigned long 444 alpha_pal_rdval(void) 445 { 446 register unsigned long v0 __asm("$0"); 447 448 __asm volatile("call_pal %1 # PAL_OSF1_rdval" 449 : "=r" (v0) 450 : "i" (PAL_OSF1_rdval) 451 /* clobbers t0, t8..t11 */ 452 : "$1", "$22", "$23", "$24", "$25"); 453 454 return (v0); 455 } 456 457 static __inline unsigned long 458 alpha_pal_swpctx(unsigned long ctx) 459 { 460 register unsigned long a0 __asm("$16") = ctx; 461 register unsigned long v0 __asm("$0"); 462 463 __asm volatile("call_pal %2 # PAL_OSF1_swpctx" 464 : "=r" (a0), "=r" (v0) 465 : "i" (PAL_OSF1_swpctx), "0" (a0) 466 /* clobbers t0, t8..t11, a0 (above) */ 467 : "$1", "$22", "$23", "$24", "$25", "memory"); 468 469 return (v0); 470 } 471 472 static __inline unsigned long 473 alpha_pal_swpipl(unsigned long ipl) 474 { 475 register unsigned long a0 __asm("$16") = ipl; 476 register unsigned long v0 __asm("$0"); 477 478 __asm volatile("call_pal %2 # PAL_OSF1_swpipl" 479 : "=r" (a0), "=r" (v0) 480 : "i" (PAL_OSF1_swpipl), "0" (a0) 481 /* clobbers t0, t8..t11, a0 (above) */ 482 : "$1", "$22", "$23", "$24", "$25", "memory"); 483 484 return (v0); 485 } 486 487 static __inline void 488 alpha_pal_tbi(unsigned long op, vaddr_t va) 489 { 490 register unsigned long a0 __asm("$16") = op; 491 register unsigned long a1 __asm("$17") = va; 492 493 __asm volatile("call_pal %2 # PAL_OSF1_tbi" 494 : "=r" (a0), "=r" (a1) 495 : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1) 496 /* clobbers t0, t8..t11, a0 (above), a1 (above) */ 497 : "$1", "$22", "$23", "$24", "$25"); 498 } 499 500 static __inline unsigned long 501 alpha_pal_whami(void) 502 { 503 register unsigned long v0 __asm("$0"); 504 505 __asm volatile("call_pal %1 # PAL_OSF1_whami" 506 : "=r" (v0) 507 : "i" (PAL_OSF1_whami) 508 /* clobbers t0, t8..t11 */ 509 : "$1", "$22", "$23", "$24", "$25"); 510 511 return (v0); 512 } 513 514 static __inline void 515 alpha_pal_wrfen(unsigned long onoff) 516 { 517 register unsigned long a0 __asm("$16") = onoff; 518 519 __asm volatile("call_pal %1 # PAL_OSF1_wrfen" 520 : "=r" (a0) 521 : "i" (PAL_OSF1_wrfen), "0" (a0) 522 /* clobbers t0, t8..t11, a0 (above) */ 523 : "$1", "$22", "$23", "$24", "$25"); 524 } 525 526 static __inline void 527 alpha_pal_wripir(unsigned long cpu_id) 528 { 529 register unsigned long a0 __asm("$16") = cpu_id; 530 531 __asm volatile("call_pal %1 # PAL_ipir" 532 : "=r" (a0) 533 : "i" (PAL_ipir), "0" (a0) 534 /* clobbers t0, t8..t11, a0 (above) */ 535 : "$1", "$22", "$23", "$24", "$25"); 536 } 537 538 static __inline void 539 alpha_pal_wrunique(unsigned long unique) 540 { 541 register unsigned long a0 __asm("$16") = unique; 542 543 __asm volatile("call_pal %1 # PAL_wrunique" 544 : "=r" (a0) 545 : "i" (PAL_wrunique), "0" (a0)); 546 } 547 548 static __inline void 549 alpha_pal_wrusp(unsigned long usp) 550 { 551 register unsigned long a0 __asm("$16") = usp; 552 553 __asm volatile("call_pal %1 # PAL_OSF1_wrusp" 554 : "=r" (a0) 555 : "i" (PAL_OSF1_wrusp), "0" (a0) 556 /* clobbers t0, t8..t11, a0 (above) */ 557 : "$1", "$22", "$23", "$24", "$25"); 558 } 559 560 static __inline void 561 alpha_pal_wrmces(unsigned long mces) 562 { 563 register unsigned long a0 __asm("$16") = mces; 564 565 __asm volatile("call_pal %1 # PAL_OSF1_wrmces" 566 : "=r" (a0) 567 : "i" (PAL_OSF1_wrmces), "0" (a0) 568 /* clobbers t0, t8..t11 */ 569 : "$1", "$22", "$23", "$24", "$25"); 570 } 571 572 static __inline void 573 alpha_pal_wrval(unsigned long val) 574 { 575 register unsigned long a0 __asm("$16") = val; 576 577 __asm volatile("call_pal %1 # PAL_OSF1_wrval" 578 : "=r" (a0) 579 : "i" (PAL_OSF1_wrval), "0" (a0) 580 /* clobbers t0, t8..t11, a0 (above) */ 581 : "$1", "$22", "$23", "$24", "$25"); 582 } 583 584 #endif /* _KERNEL */ 585 586 #endif /* __ALPHA_ALPHA_CPU_H__ */ 587
Indexes created Tue Sep 30 10:09:55 GMT 2025