alpha_cpu.h revision 1.7.2.2
1 /* $NetBSD: alpha_cpu.h,v 1.7.2.2 1997/06/06 00:14:03 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifndef __ALPHA_ALPHA_CPU_H__ 32 #define __ALPHA_ALPHA_CPU_H__ 33 34 /* 35 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 36 * 37 * Definitions for: 38 * 39 * Process Control Block 40 * Interrupt/Exception/Syscall Stack Frame 41 * Processor Status Register 42 * Machine Check Error Summary Register 43 * Machine Check Logout Area 44 * Virtual Memory Management 45 * Kernel Entry Vectors 46 * MMCSR Fault Type Codes 47 * Translation Buffer Invalidation 48 * 49 * and miscellaneous PALcode operations. 50 */ 51 52 53 /* 54 * Process Control Block definitions [OSF/1 PALcode Specific] 55 */ 56 57 struct alpha_pcb { 58 unsigned long apcb_ksp; /* kernel stack ptr */ 59 unsigned long apcb_usp; /* user stack ptr */ 60 unsigned long apcb_ptbr; /* page table base reg */ 61 unsigned int apcb_cpc; /* charged process cycles */ 62 unsigned int apcb_asn; /* address space number */ 63 unsigned long apcb_unique; /* process unique value */ 64 unsigned long apcb_flags; /* flags; see below */ 65 unsigned long apcb_decrsv0; /* DEC reserved */ 66 unsigned long apcb_decrsv1; /* DEC reserved */ 67 }; 68 69 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 70 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 71 72 /* 73 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 74 * Stack Frame definitions 75 * 76 * These are quadword offsets from the sp on kernel entry, i.e. 77 * to get to the value in question you access (sp + (offset * 8)). 78 * 79 * On syscall entry, A0-A2 aren't written to memory but space 80 * _is_ reserved for them. 81 */ 82 83 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 84 #define ALPHA_HWFRAME_PC 1 /* program counter */ 85 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 86 #define ALPHA_HWFRAME_A0 3 /* a0 */ 87 #define ALPHA_HWFRAME_A1 4 /* a1 */ 88 #define ALPHA_HWFRAME_A2 5 /* a2 */ 89 90 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 91 92 /* 93 * Processor Status Register [OSF/1 PALcode Specific] 94 * 95 * Includes user/kernel mode bit, interrupt priority levels, etc. 96 */ 97 98 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 99 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 100 101 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 102 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 103 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 104 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 105 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 106 107 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 108 109 /* Convenience constants: what must be set/clear in user mode */ 110 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 111 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 112 113 /* 114 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 115 * 116 * The following bits are values as read. On write, _PCE, _SCE, and 117 * _MIP are "write 1 to clear." 118 */ 119 120 #define ALPHA_MCES_IMP \ 121 0xffffffff00000000 /* impl. dependent */ 122 #define ALPHA_MCES_RSVD \ 123 0x00000000ffffffe0 /* reserved */ 124 #define ALPHA_MCES_DSC \ 125 0x0000000000000010 /* disable system correctable error reporting */ 126 #define ALPHA_MCES_DPC \ 127 0x0000000000000008 /* disable processor correctable error reporting */ 128 #define ALPHA_MCES_PCE \ 129 0x0000000000000004 /* processor correctable error in progress */ 130 #define ALPHA_MCES_SCE \ 131 0x0000000000000002 /* system correctable error in progress */ 132 #define ALPHA_MCES_MIP \ 133 0x0000000000000001 /* machine check in progress */ 134 135 /* 136 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 137 */ 138 139 struct alpha_logout_area { 140 unsigned int la_frame_size; /* frame size */ 141 unsigned int la_flags; /* flags; see below */ 142 unsigned int la_cpu_offset; /* offset to cpu area */ 143 unsigned int la_system_offset; /* offset to system area */ 144 }; 145 146 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 147 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 148 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 149 150 #define ALPHA_LOGOUT_NOT_BUILT \ 151 (struct alpha_logout_area *)0xffffffffffffffff) 152 153 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 154 (unsigned long *)((unsigned char *)(lap) + 16) 155 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 156 ((lap)->la_cpu_offset - 16) 157 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 158 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 159 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 160 ((lap)->la_system_offset - (lap)->la_cpu_offset) 161 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 162 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 163 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 164 ((lap)->la_frame_size - (lap)->la_system_offset) 165 166 /* 167 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 168 * 169 * Includes user and kernel space addresses and information, 170 * page table entry definitions, etc. 171 * 172 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 173 */ 174 175 #define ALPHA_PGSHIFT 13 176 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 177 178 #define ALPHA_USEG_BASE 0 /* virtual */ 179 #define ALPHA_USEG_END 0x000003ffffffffff 180 181 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 182 #define ALPHA_K0SEG_END 0xfffffdffffffffff 183 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 184 #define ALPHA_K1SEG_END 0xffffffffffffffff 185 186 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 187 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 188 189 #define ALPHA_PTE_VALID 0x0001 190 191 #define ALPHA_PTE_FAULT_ON_READ 0x0002 192 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 193 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 194 195 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 196 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 197 198 #define ALPHA_PTE_PROT 0xff00 199 #define ALPHA_PTE_KR 0x0100 200 #define ALPHA_PTE_UR 0x0200 201 #define ALPHA_PTE_KW 0x1000 202 #define ALPHA_PTE_UW 0x2000 203 204 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_KW) 205 206 #define ALPHA_PTE_SOFTWARE 0xffff0000 207 208 #define ALPHA_PTE_PFN 0xffffffff00000000 209 210 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 211 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 212 213 typedef unsigned long alpha_pt_entry_t; 214 215 /* 216 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 217 */ 218 219 #define ALPHA_KENTRY_INT 0 220 #define ALPHA_KENTRY_ARITH 1 221 #define ALPHA_KENTRY_MM 2 222 #define ALPHA_KENTRY_IF 3 223 #define ALPHA_KENTRY_UNA 4 224 #define ALPHA_KENTRY_SYS 5 225 226 /* 227 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 228 */ 229 230 #define ALPHA_MMCSR_INVALTRANS 0 231 #define ALPHA_MMCSR_ACCESS 1 232 #define ALPHA_MMCSR_FOR 2 233 #define ALPHA_MMCSR_FOE 3 234 #define ALPHA_MMCSR_FOW 4 235 236 /* 237 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 238 */ 239 240 #define ALPHA_IF_CODE_BPT 0 241 #define ALPHA_IF_CODE_BUGCHK 1 242 #define ALPHA_IF_CODE_GENTRAP 2 243 #define ALPHA_IF_CODE_FEN 3 244 #define ALPHA_IF_CODE_OPDEC 4 245 246 /* 247 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 248 */ 249 250 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 251 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 252 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 253 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 254 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 255 256 /* 257 * Stubs for Alpha instructions normally inaccessible from C. 258 */ 259 unsigned long alpha_rpcc __P((void)); 260 void alpha_mb __P((void)); 261 void alpha_wmb __P((void)); 262 263 /* 264 * Stubs for OSF/1 PALcode operations. 265 */ 266 void alpha_pal_imb __P((void)); 267 void alpha_pal_draina __P((void)); 268 void alpha_pal_halt __P((void)) __attribute__((__noreturn__)); 269 unsigned long alpha_pal_rdmces __P((void)); 270 unsigned long alpha_pal_rdps __P((void)); 271 unsigned long alpha_pal_rdusp __P((void)); 272 unsigned long alpha_pal_swpipl __P((unsigned long)); 273 unsigned long _alpha_pal_swpipl __P((unsigned long)); /* for profiling */ 274 void alpha_pal_tbi __P((unsigned long, vm_offset_t)); 275 unsigned long alpha_pal_whami __P((void)); 276 void alpha_pal_wrent __P((void *, unsigned long)); 277 void alpha_pal_wrfen __P((unsigned long)); 278 void alpha_pal_wrusp __P((unsigned long)); 279 void alpha_pal_wrvptptr __P((unsigned long)); 280 void alpha_pal_wrmces __P((unsigned long)); 281 282 #endif /* __ALPHA_ALPHA_CPU_H__ */ 283
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