alpha_cpu.h revision 1.7.2.3
1 /* $NetBSD: alpha_cpu.h,v 1.7.2.3 1997/08/12 05:55:16 cgd Exp $ */ 2 3 /* 4 * Copyright Notice: 5 * 6 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 7 * 8 * License: 9 * 10 * This License applies to this software ("Software"), created 11 * by Christopher G. Demetriou ("Author"). 12 * 13 * You may use, copy, modify and redistribute this Software without 14 * charge, in either source code form, binary form, or both, on the 15 * following conditions: 16 * 17 * 1. (a) Binary code: (i) a complete copy of the above copyright notice 18 * must be included within each copy of the Software in binary code form, 19 * and (ii) a complete copy of the above copyright notice and all terms 20 * of this License as presented here must be included within each copy of 21 * all documentation accompanying or associated with binary code, in any 22 * medium, along with a list of the software modules to which the license 23 * applies. 24 * 25 * (b) Source Code: A complete copy of the above copyright notice and all 26 * terms of this License as presented here must be included within: (i) 27 * each copy of the Software in source code form, and (ii) each copy of 28 * all accompanying or associated documentation, in any medium. 29 * 30 * 2. The following Acknowledgment must be used in communications 31 * involving the Software as described below: 32 * 33 * This product includes software developed by 34 * Christopher G. Demetriou for the NetBSD Project. 35 * 36 * The Acknowledgment must be conspicuously and completely displayed 37 * whenever the Software, or any software, products or systems containing 38 * the Software, are mentioned in advertising, marketing, informational 39 * or publicity materials of any kind, whether in print, electronic or 40 * other media (except for information provided to support use of 41 * products containing the Software by existing users or customers). 42 * 43 * 3. The name of the Author may not be used to endorse or promote 44 * products derived from this Software without specific prior written 45 * permission (conditions (1) and (2) above are not considered 46 * endorsement or promotion). 47 * 48 * 4. This license applies to: (a) all copies of the Software, whether 49 * partial or whole, original or modified, and (b) your actions, and the 50 * actions of all those who may act on your behalf. All uses not 51 * expressly permitted are reserved to the Author. 52 * 53 * 5. Disclaimer. THIS SOFTWARE IS MADE AVAILABLE BY THE AUTHOR TO THE 54 * PUBLIC FOR FREE AND "AS IS.'' ALL USERS OF THIS FREE SOFTWARE ARE 55 * SOLELY AND ENTIRELY RESPONSIBLE FOR THEIR OWN CHOICE AND USE OF THIS 56 * SOFTWARE FOR THEIR OWN PURPOSES. BY USING THIS SOFTWARE, EACH USER 57 * AGREES THAT THE AUTHOR SHALL NOT BE LIABLE FOR DAMAGES OF ANY KIND IN 58 * RELATION TO ITS USE OR PERFORMANCE. 59 * 60 * 6. If you have a special need for a change in one or more of these 61 * license conditions, please contact the Author via electronic mail to 62 * 63 * cgd (at) NetBSD.ORG 64 * 65 * or via the contact information on 66 * 67 * http://www.NetBSD.ORG/People/Pages/cgd.html 68 */ 69 70 /* 71 * Copyright (c) 1996 Carnegie-Mellon University. 72 * All rights reserved. 73 * 74 * Author: Chris G. Demetriou 75 * 76 * Permission to use, copy, modify and distribute this software and 77 * its documentation is hereby granted, provided that both the copyright 78 * notice and this permission notice appear in all copies of the 79 * software, derivative works or modified versions, and any portions 80 * thereof, and that both notices appear in supporting documentation. 81 * 82 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 83 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 84 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 85 * 86 * Carnegie Mellon requests users of this software to return to 87 * 88 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 89 * School of Computer Science 90 * Carnegie Mellon University 91 * Pittsburgh PA 15213-3890 92 * 93 * any improvements or extensions that they make and grant Carnegie the 94 * rights to redistribute these changes. 95 */ 96 97 #ifndef __ALPHA_ALPHA_CPU_H__ 98 #define __ALPHA_ALPHA_CPU_H__ 99 100 /* 101 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 102 * 103 * Definitions for: 104 * 105 * Process Control Block 106 * Interrupt/Exception/Syscall Stack Frame 107 * Processor Status Register 108 * Machine Check Error Summary Register 109 * Machine Check Logout Area 110 * Virtual Memory Management 111 * Kernel Entry Vectors 112 * MMCSR Fault Type Codes 113 * Translation Buffer Invalidation 114 * 115 * and miscellaneous PALcode operations. 116 */ 117 118 119 /* 120 * Process Control Block definitions [OSF/1 PALcode Specific] 121 */ 122 123 struct alpha_pcb { 124 unsigned long apcb_ksp; /* kernel stack ptr */ 125 unsigned long apcb_usp; /* user stack ptr */ 126 unsigned long apcb_ptbr; /* page table base reg */ 127 unsigned int apcb_cpc; /* charged process cycles */ 128 unsigned int apcb_asn; /* address space number */ 129 unsigned long apcb_unique; /* process unique value */ 130 unsigned long apcb_flags; /* flags; see below */ 131 unsigned long apcb_decrsv0; /* DEC reserved */ 132 unsigned long apcb_decrsv1; /* DEC reserved */ 133 }; 134 135 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 136 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 137 138 /* 139 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 140 * Stack Frame definitions 141 * 142 * These are quadword offsets from the sp on kernel entry, i.e. 143 * to get to the value in question you access (sp + (offset * 8)). 144 * 145 * On syscall entry, A0-A2 aren't written to memory but space 146 * _is_ reserved for them. 147 */ 148 149 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 150 #define ALPHA_HWFRAME_PC 1 /* program counter */ 151 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 152 #define ALPHA_HWFRAME_A0 3 /* a0 */ 153 #define ALPHA_HWFRAME_A1 4 /* a1 */ 154 #define ALPHA_HWFRAME_A2 5 /* a2 */ 155 156 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 157 158 /* 159 * Processor Status Register [OSF/1 PALcode Specific] 160 * 161 * Includes user/kernel mode bit, interrupt priority levels, etc. 162 */ 163 164 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 165 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 166 167 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 168 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 169 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 170 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 171 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 172 173 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 174 175 /* Convenience constants: what must be set/clear in user mode */ 176 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 177 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 178 179 /* 180 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 181 * 182 * The following bits are values as read. On write, _PCE, _SCE, and 183 * _MIP are "write 1 to clear." 184 */ 185 186 #define ALPHA_MCES_IMP \ 187 0xffffffff00000000 /* impl. dependent */ 188 #define ALPHA_MCES_RSVD \ 189 0x00000000ffffffe0 /* reserved */ 190 #define ALPHA_MCES_DSC \ 191 0x0000000000000010 /* disable system correctable error reporting */ 192 #define ALPHA_MCES_DPC \ 193 0x0000000000000008 /* disable processor correctable error reporting */ 194 #define ALPHA_MCES_PCE \ 195 0x0000000000000004 /* processor correctable error in progress */ 196 #define ALPHA_MCES_SCE \ 197 0x0000000000000002 /* system correctable error in progress */ 198 #define ALPHA_MCES_MIP \ 199 0x0000000000000001 /* machine check in progress */ 200 201 /* 202 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 203 */ 204 205 struct alpha_logout_area { 206 unsigned int la_frame_size; /* frame size */ 207 unsigned int la_flags; /* flags; see below */ 208 unsigned int la_cpu_offset; /* offset to cpu area */ 209 unsigned int la_system_offset; /* offset to system area */ 210 }; 211 212 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 213 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 214 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 215 216 #define ALPHA_LOGOUT_NOT_BUILT \ 217 (struct alpha_logout_area *)0xffffffffffffffff) 218 219 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 220 (unsigned long *)((unsigned char *)(lap) + 16) 221 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 222 ((lap)->la_cpu_offset - 16) 223 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 224 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 225 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 226 ((lap)->la_system_offset - (lap)->la_cpu_offset) 227 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 228 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 229 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 230 ((lap)->la_frame_size - (lap)->la_system_offset) 231 232 /* 233 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 234 * 235 * Includes user and kernel space addresses and information, 236 * page table entry definitions, etc. 237 * 238 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 239 */ 240 241 #define ALPHA_PGSHIFT 13 242 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 243 244 #define ALPHA_USEG_BASE 0 /* virtual */ 245 #define ALPHA_USEG_END 0x000003ffffffffff 246 247 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 248 #define ALPHA_K0SEG_END 0xfffffdffffffffff 249 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 250 #define ALPHA_K1SEG_END 0xffffffffffffffff 251 252 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 253 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 254 255 #define ALPHA_PTE_VALID 0x0001 256 257 #define ALPHA_PTE_FAULT_ON_READ 0x0002 258 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 259 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 260 261 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 262 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 263 264 #define ALPHA_PTE_PROT 0xff00 265 #define ALPHA_PTE_KR 0x0100 266 #define ALPHA_PTE_UR 0x0200 267 #define ALPHA_PTE_KW 0x1000 268 #define ALPHA_PTE_UW 0x2000 269 270 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 271 272 #define ALPHA_PTE_SOFTWARE 0xffff0000 273 274 #define ALPHA_PTE_PFN 0xffffffff00000000 275 276 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 277 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 278 279 typedef unsigned long alpha_pt_entry_t; 280 281 /* 282 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 283 */ 284 285 #define ALPHA_KENTRY_INT 0 286 #define ALPHA_KENTRY_ARITH 1 287 #define ALPHA_KENTRY_MM 2 288 #define ALPHA_KENTRY_IF 3 289 #define ALPHA_KENTRY_UNA 4 290 #define ALPHA_KENTRY_SYS 5 291 292 /* 293 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 294 */ 295 296 #define ALPHA_MMCSR_INVALTRANS 0 297 #define ALPHA_MMCSR_ACCESS 1 298 #define ALPHA_MMCSR_FOR 2 299 #define ALPHA_MMCSR_FOE 3 300 #define ALPHA_MMCSR_FOW 4 301 302 /* 303 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 304 */ 305 306 #define ALPHA_IF_CODE_BPT 0 307 #define ALPHA_IF_CODE_BUGCHK 1 308 #define ALPHA_IF_CODE_GENTRAP 2 309 #define ALPHA_IF_CODE_FEN 3 310 #define ALPHA_IF_CODE_OPDEC 4 311 312 /* 313 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 314 */ 315 316 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 317 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 318 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 319 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 320 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 321 322 /* 323 * Stubs for Alpha instructions normally inaccessible from C. 324 */ 325 unsigned long alpha_rpcc __P((void)); 326 u_int8_t alpha_ldbu __P((volatile u_int8_t *)); 327 u_int16_t alpha_ldwu __P((volatile u_int16_t *)); 328 void alpha_mb __P((void)); 329 void alpha_stb __P((volatile u_int8_t *, u_int8_t)); 330 void alpha_stw __P((volatile u_int16_t *, u_int16_t)); 331 void alpha_wmb __P((void)); 332 333 /* 334 * Stubs for OSF/1 PALcode operations. 335 */ 336 void alpha_pal_imb __P((void)); 337 void alpha_pal_draina __P((void)); 338 void alpha_pal_halt __P((void)) __attribute__((__noreturn__)); 339 unsigned long alpha_pal_rdmces __P((void)); 340 unsigned long alpha_pal_rdps __P((void)); 341 unsigned long alpha_pal_rdusp __P((void)); 342 unsigned long alpha_pal_swpipl __P((unsigned long)); 343 unsigned long _alpha_pal_swpipl __P((unsigned long)); /* for profiling */ 344 void alpha_pal_tbi __P((unsigned long, vm_offset_t)); 345 unsigned long alpha_pal_whami __P((void)); 346 void alpha_pal_wrent __P((void *, unsigned long)); 347 void alpha_pal_wrfen __P((unsigned long)); 348 void alpha_pal_wrusp __P((unsigned long)); 349 void alpha_pal_wrvptptr __P((unsigned long)); 350 void alpha_pal_wrmces __P((unsigned long)); 351 352 #endif /* __ALPHA_ALPHA_CPU_H__ */ 353
Indexes created Thu Oct 23 22:10:10 GMT 2025