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cpu.h revision 1.104
      1 /* $NetBSD: cpu.h,v 1.104 2021/08/14 17:51:18 ryo Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  * NASA Ames Research Center, and by Charles M. Hannum.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 /*
     34  * Copyright (c) 1988 University of Utah.
     35  * Copyright (c) 1982, 1990, 1993
     36  *	The Regents of the University of California.  All rights reserved.
     37  *
     38  * This code is derived from software contributed to Berkeley by
     39  * the Systems Programming Group of the University of Utah Computer
     40  * Science Department.
     41  *
     42  * Redistribution and use in source and binary forms, with or without
     43  * modification, are permitted provided that the following conditions
     44  * are met:
     45  * 1. Redistributions of source code must retain the above copyright
     46  *    notice, this list of conditions and the following disclaimer.
     47  * 2. Redistributions in binary form must reproduce the above copyright
     48  *    notice, this list of conditions and the following disclaimer in the
     49  *    documentation and/or other materials provided with the distribution.
     50  * 3. Neither the name of the University nor the names of its contributors
     51  *    may be used to endorse or promote products derived from this software
     52  *    without specific prior written permission.
     53  *
     54  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     55  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     56  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     57  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     58  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     59  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     60  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     61  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     62  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     63  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     64  * SUCH DAMAGE.
     65  *
     66  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     67  *
     68  *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
     69  */
     70 
     71 #ifndef _ALPHA_CPU_H_
     72 #define _ALPHA_CPU_H_
     73 
     74 #if defined(_KERNEL_OPT)
     75 #include "opt_gprof.h"
     76 #include "opt_multiprocessor.h"
     77 #include "opt_lockdebug.h"
     78 #endif
     79 
     80 /*
     81  * Exported definitions unique to Alpha cpu support.
     82  */
     83 
     84 #include <machine/alpha_cpu.h>
     85 
     86 #if defined(_KERNEL) || defined(_KMEMUSER)
     87 #include <sys/cpu_data.h>
     88 #include <sys/cctr.h>
     89 #include <sys/intr.h>
     90 #include <machine/frame.h>
     91 
     92 /*
     93  * Machine check information.
     94  */
     95 struct mchkinfo {
     96 	volatile int mc_expected;	/* machine check is expected */
     97 	volatile int mc_received;	/* machine check was received */
     98 };
     99 
    100 /*
    101  * Per-cpu information.  Data accessed by MI code is marked [MI].
    102  */
    103 struct cpu_info {
    104 	struct cpu_data ci_data;	/* [MI] general per-cpu data */
    105 	struct lwp *ci_curlwp;		/* [MI] current owner of the cpu */
    106 	struct lwp *ci_onproc;		/* [MI] current user LWP / kthread */
    107 	struct cctr_state ci_cc;	/* [MI] cycle counter state */
    108 
    109 	volatile int ci_mtx_count;	/* [MI] neg count of spin mutexes */
    110 	volatile int ci_mtx_oldspl;	/* [MI] for spin mutex splx() */
    111 
    112 	u_long ci_intrdepth;		/* interrupt trap depth */
    113 	volatile u_long ci_ssir;	/* simulated software interrupt reg */
    114 					/* LWPs for soft intr dispatch */
    115 	struct lwp *ci_silwps[SOFTINT_COUNT];
    116 	struct cpu_softc *ci_softc;	/* pointer to our device */
    117 
    118 	struct pmap *ci_pmap;		/* currently-activated pmap */
    119 	u_int ci_next_asn;		/* next ASN to assign */
    120 	u_long ci_asn_gen;		/* current ASN generation */
    121 
    122 	struct mchkinfo ci_mcinfo;	/* machine check info */
    123 
    124 	/*
    125 	 * The following must be in their own cache line, as they are
    126 	 * stored to regularly by remote CPUs.
    127 	 */
    128 	volatile u_long ci_ipis		/* interprocessor interrupts pending */
    129 			__aligned(64);
    130 	u_int	ci_want_resched;	/* [MI] preempt current process */
    131 
    132 	/*
    133 	 * These are largely static, and will frequently be fetched
    134 	 * by other CPUs.  For that reason, they get their own cache
    135 	 * line, too.
    136 	 */
    137 	struct cpu_info *ci_next	/* next cpu_info structure */
    138 			__aligned(64);
    139 	cpuid_t ci_cpuid;		/* [MI] our CPU ID */
    140 	volatile u_long ci_flags;	/* flags; see below */
    141 	uint64_t ci_pcc_freq;		/* cpu cycles/second */
    142 	struct trapframe *ci_db_regs;	/* registers for debuggers */
    143 	u_int	ci_nintrhand;		/* # of interrupt handlers */
    144 #if defined(GPROF) && defined(MULTIPROCESSOR)
    145 	struct gmonparam *ci_gmon;	/* [MI] per-cpu GPROF */
    146 #endif
    147 };
    148 
    149 /* Ensure some cpu_info fields are within the signed 16-bit displacement. */
    150 __CTASSERT(offsetof(struct cpu_info, ci_curlwp) <= 0x7ff0);
    151 __CTASSERT(offsetof(struct cpu_info, ci_ssir) <= 0x7ff0);
    152 
    153 #endif /* _KERNEL || _KMEMUSER */
    154 
    155 #if defined(_KERNEL)
    156 
    157 #define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
    158 #define	CPUF_PRESENT	0x02		/* CPU is present */
    159 #define	CPUF_RUNNING	0x04		/* CPU is running */
    160 #define	CPUF_PAUSED	0x08		/* CPU is paused */
    161 
    162 extern	struct cpu_info cpu_info_primary;
    163 extern	struct cpu_info *cpu_info_list;
    164 
    165 #define	CPU_INFO_ITERATOR		int __unused
    166 #define	CPU_INFO_FOREACH(cii, ci)	ci = cpu_info_list; \
    167 					ci != NULL; ci = ci->ci_next
    168 
    169 #if defined(MULTIPROCESSOR)
    170 extern	volatile u_long cpus_running;
    171 extern	volatile u_long cpus_paused;
    172 extern	struct cpu_info *cpu_info[];
    173 
    174 #define	curlwp			((struct lwp *)alpha_pal_rdval())
    175 #define	curcpu()		curlwp->l_cpu
    176 #define	CPU_IS_PRIMARY(ci)	((ci)->ci_flags & CPUF_PRIMARY)
    177 
    178 void	cpu_boot_secondary_processors(void);
    179 
    180 void	cpu_pause_resume(unsigned long, int);
    181 void	cpu_pause_resume_all(int);
    182 #else /* ! MULTIPROCESSOR */
    183 #define	curcpu()	(&cpu_info_primary)
    184 #define	curlwp		curcpu()->ci_curlwp
    185 #endif /* MULTIPROCESSOR */
    186 
    187 
    188 /*
    189  * definitions of cpu-dependent requirements
    190  * referenced in generic code
    191  */
    192 #define	cpu_number()		alpha_pal_whami()
    193 #define	cpu_proc_fork(p1, p2)	/* nothing */
    194 
    195 /*
    196  * Arguments to hardclock and gatherstats encapsulate the previous
    197  * machine state in an opaque clockframe.  On the alpha, we use
    198  * what we push on an interrupt (a trapframe).
    199  */
    200 struct clockframe {
    201 	struct trapframe	cf_tf;
    202 };
    203 #define	CLKF_USERMODE(framep)						\
    204 	(((framep)->cf_tf.tf_regs[FRAME_PS] & ALPHA_PSL_USERMODE) != 0)
    205 #define	CLKF_PC(framep)		((framep)->cf_tf.tf_regs[FRAME_PC])
    206 
    207 /*
    208  * This isn't perfect; if the clock interrupt comes in before the
    209  * r/m/w cycle is complete, we won't be counted... but it's not
    210  * like this statistic has to be extremely accurate.
    211  */
    212 #define	CLKF_INTR(framep)						\
    213 	((curcpu()->ci_intrdepth & 0xf) != 0)	/* see interrupt() */
    214 
    215 /*
    216  * This is used during profiling to integrate system time.  It can safely
    217  * assume that the process is resident.
    218  */
    219 #define	LWP_PC(p)		((l)->l_md.md_tf->tf_regs[FRAME_PC])
    220 
    221 void	cpu_need_proftick(struct lwp *);
    222 void	cpu_signotify(struct lwp *);
    223 
    224 #define	aston(l)		((l)->l_md.md_astpending = 1)
    225 #endif /* _KERNEL */
    226 
    227 /*
    228  * CTL_MACHDEP definitions.
    229  */
    230 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */
    231 #define	CPU_ROOT_DEVICE		2	/* string: root device name */
    232 #define	CPU_UNALIGNED_PRINT	3	/* int: print unaligned accesses */
    233 #define	CPU_UNALIGNED_FIX	4	/* int: fix unaligned accesses */
    234 #define	CPU_UNALIGNED_SIGBUS	5	/* int: SIGBUS unaligned accesses */
    235 #define	CPU_BOOTED_KERNEL	6	/* string: booted kernel name */
    236 #define	CPU_FP_SYNC_COMPLETE	7	/* int: always fixup sync fp traps */
    237 #define	CPU_CCTR		8	/* int: using CC timecounter */
    238 #define	CPU_IS_QEMU		9	/* int: running under Qemu */
    239 #define	CPU_FP_COMPLETE_DEBUG	10	/* int: enable FP completion debug */
    240 
    241 
    242 #ifdef _KERNEL
    243 
    244 struct pcb;
    245 struct proc;
    246 struct reg;
    247 struct rpb;
    248 struct trapframe;
    249 
    250 int	badaddr(void *, size_t);
    251 void *	cpu_uarea_alloc(bool);
    252 bool	cpu_uarea_free(void *);
    253 
    254 void	cpu_idle_wtint(void);
    255 extern	void (*cpu_idle_fn)(void);
    256 #define	cpu_idle()	(*cpu_idle_fn)()
    257 
    258 void	cpu_initclocks_secondary(void);
    259 
    260 #endif /* _KERNEL */
    261 #endif /* _ALPHA_CPU_H_ */
    262