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      1  1.9   andvar /* $NetBSD: fpu.h,v 1.9 2025/02/24 21:32:26 andvar Exp $ */
      2  1.2     ross 
      3  1.1     ross /*-
      4  1.4     ross  * Copyright (c) 2001 Ross Harvey
      5  1.1     ross  * All rights reserved.
      6  1.1     ross  *
      7  1.4     ross  * This software was written for NetBSD.
      8  1.4     ross  *
      9  1.1     ross  * Redistribution and use in source and binary forms, with or without
     10  1.1     ross  * modification, are permitted provided that the following conditions
     11  1.1     ross  * are met:
     12  1.1     ross  * 1. Redistributions of source code must retain the above copyright
     13  1.1     ross  *    notice, this list of conditions and the following disclaimer.
     14  1.1     ross  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1     ross  *    notice, this list of conditions and the following disclaimer in the
     16  1.1     ross  *    documentation and/or other materials provided with the distribution.
     17  1.6   martin  * 3. All advertising materials mentioning features or use of this software
     18  1.6   martin  *    must display the following acknowledgement:
     19  1.6   martin  *	This product includes software developed by the NetBSD
     20  1.6   martin  *	Foundation, Inc. and its contributors.
     21  1.6   martin  * 4. Neither the name of The NetBSD Foundation nor the names of its
     22  1.6   martin  *    contributors may be used to endorse or promote products derived
     23  1.6   martin  *    from this software without specific prior written permission.
     24  1.1     ross  *
     25  1.4     ross  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     26  1.4     ross  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  1.4     ross  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  1.4     ross  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     29  1.4     ross  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  1.4     ross  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  1.4     ross  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  1.4     ross  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  1.4     ross  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  1.4     ross  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  1.4     ross  * POSSIBILITY OF SUCH DAMAGE.
     36  1.1     ross  */
     37  1.1     ross 
     38  1.4     ross #ifndef _ALPHA_FPU_H_
     39  1.4     ross #define _ALPHA_FPU_H_
     40  1.4     ross 
     41  1.1     ross /*
     42  1.4     ross  * Most of these next definitions were moved from <ieeefp.h>. Apparently the
     43  1.4     ross  * names happen to match those exported by Compaq and Linux from their fpu.h
     44  1.4     ross  * files.
     45  1.1     ross  */
     46  1.1     ross 
     47  1.8  thorpej /*
     48  1.8  thorpej  * Bits in the Alpha Floating Point Control register.  This is the hardware
     49  1.8  thorpej  * register, and should not be directly manipulated by application software.
     50  1.8  thorpej  */
     51  1.8  thorpej #define	FPCR_SUM	__BIT(63)	/* Summary (OR of all exception bits) */
     52  1.8  thorpej #define	FPCR_INED	__BIT(62)	/* Inexact trap Disable */
     53  1.8  thorpej #define	FPCR_UNFD	__BIT(61)	/* Underflow trap Disable */
     54  1.8  thorpej #define	FPCR_UNDZ	__BIT(60)	/* Underflow to Zero */
     55  1.8  thorpej #define	FPCR_DYN_RM	__BITS(58,59)	/* Dynamic Rounding Mode */
     56  1.8  thorpej 					/* 00 Chopped */
     57  1.8  thorpej 					/* 01 Minus Infinity */
     58  1.8  thorpej 					/* 10 Normal (round nearest) */
     59  1.8  thorpej 					/* 11 Plus Infinity */
     60  1.8  thorpej #define	FPCR_IOV	__BIT(57)	/* Integer Overflow */
     61  1.8  thorpej #define	FPCR_INE	__BIT(56)	/* Inexact Result */
     62  1.8  thorpej #define	FPCR_UNF	__BIT(55)	/* Underflow */
     63  1.8  thorpej #define	FPCR_OVF	__BIT(54)	/* Overflow */
     64  1.8  thorpej #define	FPCR_DZE	__BIT(53)	/* Division By Zero */
     65  1.8  thorpej #define	FPCR_INV	__BIT(52)	/* Invalid Operation */
     66  1.8  thorpej #define	FPCR_OVFD	__BIT(51)	/* Overflow trap Disable */
     67  1.8  thorpej #define	FPCR_DZED	__BIT(50)	/* Division By Zero trap Disable */
     68  1.8  thorpej #define	FPCR_INVD	__BIT(49)	/* Invalid Operation trap Disable */
     69  1.8  thorpej #define	FPCR_DNZ	__BIT(48)	/* Denormal Operands to Zero */
     70  1.8  thorpej #define	FPCR_DNOD	__BIT(47)	/* Denormal Operation tap Disable */
     71  1.1     ross 
     72  1.4     ross #define	FPCR_MIRRORED (FPCR_INE | FPCR_UNF | FPCR_OVF | FPCR_DZE | FPCR_INV)
     73  1.4     ross #define FPCR_MIR_START 52
     74  1.1     ross 
     75  1.8  thorpej /* NetBSD default - no traps enabled, round-to-nearest */
     76  1.8  thorpej #define	FPCR_DEFAULT	(__SHIFTIN(FP_RN, FPCR_DYN_RM) |		\
     77  1.8  thorpej 			 FPCR_INED | FPCR_UNFD | FPCR_OVFD |		\
     78  1.8  thorpej 			 FPCR_DZED | FPCR_INVD | FPCR_DNOD)
     79  1.8  thorpej 
     80  1.1     ross /*
     81  1.8  thorpej  * IEEE Floating Point Control (FP_C) Quadword.  This is a software
     82  1.8  thorpej  * virtual register that abstracts the FPCR and software complation
     83  1.8  thorpej  * performed by the kernel.
     84  1.8  thorpej  *
     85  1.4     ross  * The AARM specifies the bit positions of the software word used for
     86  1.4     ross  * user mode interface to the control and status of the kernel completion
     87  1.4     ross  * routines. Although it largely just redefines the FPCR, it shuffles
     88  1.4     ross  * the bit order. The names of the bits are defined in the AARM, and
     89  1.4     ross  * the definition prefix can easily be determined from public domain
     90  1.4     ross  * programs written to either the Compaq or Linux interfaces, which
     91  1.4     ross  * appear to be identical.
     92  1.8  thorpej  *
     93  1.8  thorpej  * Bits 63-48 are reserved for implementation software.
     94  1.9   andvar  * Bits 47-23 are reserved for future architecture definition.
     95  1.8  thorpej  * Bits 16-12 are reserved for implementation software.
     96  1.8  thorpej  * Bits 11-7 are reserved for future architecture definition.
     97  1.8  thorpej  * Bit 0 is reserved for implementation software.
     98  1.1     ross  */
     99  1.1     ross 
    100  1.8  thorpej #define	IEEE_STATUS_DNO __BIT(22)	/* Denormal Operand */
    101  1.8  thorpej #define	IEEE_STATUS_INE __BIT(21)	/* Inexact Result */
    102  1.8  thorpej #define	IEEE_STATUS_UNF __BIT(20)	/* Underflow */
    103  1.8  thorpej #define	IEEE_STATUS_OVF __BIT(19)	/* Overflow */
    104  1.8  thorpej #define	IEEE_STATUS_DZE __BIT(18)	/* Division By Zero */
    105  1.8  thorpej #define	IEEE_STATUS_INV __BIT(17)	/* Invalid Operation */
    106  1.8  thorpej 
    107  1.8  thorpej #define	IEEE_TRAP_ENABLE_DNO __BIT(6)	/* Denormal Operation trap */
    108  1.8  thorpej #define	IEEE_TRAP_ENABLE_INE __BIT(5)	/* Inexact Result trap */
    109  1.8  thorpej #define	IEEE_TRAP_ENABLE_UNF __BIT(4)	/* Underflow trap */
    110  1.8  thorpej #define	IEEE_TRAP_ENABLE_OVF __BIT(3)	/* Overflow trap */
    111  1.8  thorpej #define	IEEE_TRAP_ENABLE_DZE __BIT(2)	/* Division By Zero trap */
    112  1.8  thorpej #define	IEEE_TRAP_ENABLE_INV __BIT(1)	/* Invalid Operation trap */
    113  1.8  thorpej 
    114  1.8  thorpej #define	IEEE_INHERIT __BIT(14)
    115  1.8  thorpej #define	IEEE_MAP_UMZ __BIT(13)		/* Map underflowed outputs to zero */
    116  1.8  thorpej #define	IEEE_MAP_DMZ __BIT(12)		/* Map denormal inputs to zero */
    117  1.4     ross 
    118  1.8  thorpej #define	FP_C_ALLBITS	__BITS(1,22)
    119  1.8  thorpej 
    120  1.8  thorpej #define	FP_C_MIRRORED	(IEEE_STATUS_INE | IEEE_STATUS_UNF | IEEE_STATUS_OVF \
    121  1.8  thorpej 			 | IEEE_STATUS_DZE | IEEE_STATUS_INV)
    122  1.4     ross #define	FP_C_MIR_START 17
    123  1.4     ross 
    124  1.8  thorpej /* NetBSD default - no traps enabled (see FPCR default) */
    125  1.8  thorpej #define	FP_C_DEFAULT	0
    126  1.8  thorpej 
    127  1.4     ross #ifdef _KERNEL
    128  1.4     ross 
    129  1.4     ross #define	FLD_MASK(len) ((1UL << (len)) - 1)
    130  1.4     ross #define FLD_CLEAR(obj, origin, len)	\
    131  1.4     ross 		((obj) & ~(FLD_MASK(len) << (origin)))
    132  1.4     ross #define	FLD_INSERT(obj, origin, len, value)	\
    133  1.4     ross 		(FLD_CLEAR(obj, origin, len) | (value) << origin)
    134  1.4     ross 
    135  1.4     ross #define	FP_C_TO_NETBSD_MASK(fp_c) 	((fp_c) >> 1 & 0x3f)
    136  1.4     ross #define	FP_C_TO_NETBSD_FLAG(fp_c) 	((fp_c) >> 17 & 0x3f)
    137  1.4     ross #define NETBSD_MASK_TO_FP_C(m)		(((m) & 0x3f) << 1)
    138  1.4     ross #define NETBSD_FLAG_TO_FP_C(s)		(((s) & 0x3f) << 17)
    139  1.4     ross #define	CLEAR_FP_C_MASK(fp_c)		((fp_c) & ~(0x3f << 1))
    140  1.4     ross #define	CLEAR_FP_C_FLAG(fp_c)		((fp_c) & ~(0x3f << 17))
    141  1.4     ross #define	SET_FP_C_MASK(fp_c, m) (CLEAR_FP_C_MASK(fp_c) | NETBSD_MASK_TO_FP_C(m))
    142  1.4     ross #define	SET_FP_C_FLAG(fp_c, m) (CLEAR_FP_C_FLAG(fp_c) | NETBSD_FLAG_TO_FP_C(m))
    143  1.1     ross 
    144  1.8  thorpej #endif /* _KERNEL */
    145  1.1     ross 
    146  1.8  thorpej #endif /* _ALPHA_FPU_H_ */
    147