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fpu.h revision 1.1 
      1 /*-
      2  * Copyright (c) 1998 Doug Rabson
      3  * All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  * 2. Redistributions in binary form must reproduce the above copyright
     11  *    notice, this list of conditions and the following disclaimer in the
     12  *    documentation and/or other materials provided with the distribution.
     13  *
     14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     24  * SUCH DAMAGE.
     25  *
     26  *	Id: fpu.h,v 1.2 1998/12/23 11:50:51 dfr Exp
     27  */
     28 
     29 #ifndef _MACHINE_FPU_H_
     30 #define _MACHINE_FPU_H_
     31 
     32 /*
     33  * Floating point control register bits.
     34  *
     35  * From Alpha AXP Architecture Reference Manual, Instruction
     36  * Descriptions (I) PP 4-69.
     37  */
     38 
     39 #define FPCR_INVD	(1LL << 49)	/* Invalid Operation DIsable */
     40 #define FPCR_DZED	(1LL << 50)	/* Division by Zero Disable */
     41 #define FPCR_OVFD	(1LL << 51)	/* Overflow Disable */
     42 #define FPCR_INV	(1LL << 52)	/* Invalid Operation */
     43 #define FPCR_DZE	(1LL << 53)	/* Division by Zero */
     44 #define FPCR_OVF	(1LL << 54)	/* Overflow */
     45 #define FPCR_UNF	(1LL << 55)	/* Underflow */
     46 #define FPCR_INE	(1LL << 56)	/* Inexact Result */
     47 #define FPCR_IOV	(1LL << 57)	/* Integer Overflow */
     48 #define FPCR_DYN_CHOPPED (0LL << 58)	/* Chopped rounding mode */
     49 #define FPCR_DYN_MINUS	(1LL << 58)	/* Minus infinity */
     50 #define FPCR_DYN_NORMAL (2LL << 58)	/* Normal rounding */
     51 #define FPCR_DYN_PLUS	(3LL << 58)	/* Plus infinity */
     52 #define FPCR_DYN_MASK	(3LL << 58)	/* Rounding mode mask */
     53 #define FPCR_DYN_SHIFT	58
     54 #define FPCR_UNDZ	(1LL << 60)	/* Underflow to Zero */
     55 #define FPCR_UNFD	(1LL << 61)	/* Underflow Disable */
     56 #define FPCR_INED	(1LL << 62)	/* Inexact Disable */
     57 #define FPCR_SUM	(1LL << 63)	/* Summary Bit */
     58 #define FPCR_MASK	(~0LL << 49)
     59 
     60 /*
     61  * Exception summary bits.
     62  *
     63  * From Alpha AXP Architecture Reference Manual, DEC OSF/1 Exceptions
     64  * and Interrupts (II-B) PP 5-5.
     65  */
     66 
     67 #define EXCSUM_SWC	(1LL << 0)	/* Software completion */
     68 #define EXCSUM_INV	(1LL << 1)	/* Invalid operation */
     69 #define EXCSUM_DZE	(1LL << 2)	/* Division by zero */
     70 #define EXCSUM_OVF	(1LL << 3)	/* Overflow */
     71 #define EXCSUM_UNF	(1LL << 4)	/* Underflow */
     72 #define EXCSUM_INE	(1LL << 5)	/* Inexact result */
     73 #define EXCSUM_IOV	(1LL << 6)	/* Integer overflow */
     74 
     75 /*
     76  * Definitions for IEEE trap enables.  These are implemented in
     77  * software and should be compatible with OSF/1 and Linux.
     78  */
     79 
     80 /* read/write flags */
     81 #define IEEE_TRAP_ENABLE_INV	(1LL << 1) /* Invalid operation */
     82 #define IEEE_TRAP_ENABLE_DZE	(1LL << 2) /* Division by zero */
     83 #define IEEE_TRAP_ENABLE_OVF	(1LL << 3) /* Overflow */
     84 #define IEEE_TRAP_ENABLE_UNF	(1LL << 4) /* Underflow */
     85 #define IEEE_TRAP_ENABLE_INE	(1LL << 5) /* Inexact result */
     86 #define IEEE_TRAP_ENABLE_MASK	(IEEE_TRAP_ENABLE_INV		\
     87 				 | IEEE_TRAP_ENABLE_DZE		\
     88 				 | IEEE_TRAP_ENABLE_OVF		\
     89 				 | IEEE_TRAP_ENABLE_UNF		\
     90 				 | IEEE_TRAP_ENABLE_INE)
     91 
     92 /* read only flags */
     93 #define IEEE_STATUS_INV		(1LL << 17) /* Invalid operation */
     94 #define IEEE_STATUS_DZE		(1LL << 18) /* Division by zero */
     95 #define IEEE_STATUS_OVF		(1LL << 19) /* Overflow */
     96 #define IEEE_STATUS_UNF		(1LL << 20) /* Underflow */
     97 #define IEEE_STATUS_INE		(1LL << 21) /* Inexact result */
     98 #define IEEE_STATUS_MASK	(IEEE_STATUS_INV		\
     99 				 | IEEE_STATUS_DZE		\
    100 				 | IEEE_STATUS_OVF		\
    101 				 | IEEE_STATUS_UNF		\
    102 				 | IEEE_STATUS_INE)
    103 #define IEEE_STATUS_TO_EXCSUM_SHIFT	16 /* convert to excsum */
    104 #define IEEE_STATUS_TO_FPCR_SHIFT	35 /* convert to fpcr */
    105 
    106 #define IEEE_INHERIT		(1LL << 63) /* inherit on fork */
    107 
    108 /* read and write floating point control register */
    109 #define GET_FPCR(x) \
    110 	__asm__("trapb"); \
    111 	__asm__("mf_fpcr %0" : "=f" (x)); \
    112 	__asm__("trapb")
    113 #define SET_FPCR(x) \
    114 	__asm__("trapb"); \
    115 	__asm__("mt_fpcr %0" : : "f" (x)); \
    116 	__asm__("trapb")
    117 
    118 #ifdef KERNEL
    119 
    120 extern int fp_software_completion(u_int64_t regmask, struct proc *p);
    121 
    122 #endif
    123 
    124 #endif /* ! _MACHINE_FPU_H_ */
    125