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fpu.h revision 1.2 
      1 /* $NetBSD: fpu.h,v 1.2 1999/01/18 20:36:22 ross Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1998 Doug Rabson
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  *
     28  *	Id: fpu.h,v 1.2 1998/12/23 11:50:51 dfr Exp
     29  */
     30 
     31 #ifndef _MACHINE_FPU_H_
     32 #define _MACHINE_FPU_H_
     33 
     34 /*
     35  * Floating point control register bits.
     36  *
     37  * From Alpha AXP Architecture Reference Manual, Instruction
     38  * Descriptions (I) PP 4-69.
     39  */
     40 
     41 #define FPCR_INVD	(1LL << 49)	/* Invalid Operation DIsable */
     42 #define FPCR_DZED	(1LL << 50)	/* Division by Zero Disable */
     43 #define FPCR_OVFD	(1LL << 51)	/* Overflow Disable */
     44 #define FPCR_INV	(1LL << 52)	/* Invalid Operation */
     45 #define FPCR_DZE	(1LL << 53)	/* Division by Zero */
     46 #define FPCR_OVF	(1LL << 54)	/* Overflow */
     47 #define FPCR_UNF	(1LL << 55)	/* Underflow */
     48 #define FPCR_INE	(1LL << 56)	/* Inexact Result */
     49 #define FPCR_IOV	(1LL << 57)	/* Integer Overflow */
     50 #define FPCR_DYN_CHOPPED (0LL << 58)	/* Chopped rounding mode */
     51 #define FPCR_DYN_MINUS	(1LL << 58)	/* Minus infinity */
     52 #define FPCR_DYN_NORMAL (2LL << 58)	/* Normal rounding */
     53 #define FPCR_DYN_PLUS	(3LL << 58)	/* Plus infinity */
     54 #define FPCR_DYN_MASK	(3LL << 58)	/* Rounding mode mask */
     55 #define FPCR_DYN_SHIFT	58
     56 #define FPCR_UNDZ	(1LL << 60)	/* Underflow to Zero */
     57 #define FPCR_UNFD	(1LL << 61)	/* Underflow Disable */
     58 #define FPCR_INED	(1LL << 62)	/* Inexact Disable */
     59 #define FPCR_SUM	(1LL << 63)	/* Summary Bit */
     60 #define FPCR_MASK	(~0LL << 49)
     61 
     62 /*
     63  * Exception summary bits.
     64  *
     65  * From Alpha AXP Architecture Reference Manual, DEC OSF/1 Exceptions
     66  * and Interrupts (II-B) PP 5-5.
     67  */
     68 
     69 #define EXCSUM_SWC	(1LL << 0)	/* Software completion */
     70 #define EXCSUM_INV	(1LL << 1)	/* Invalid operation */
     71 #define EXCSUM_DZE	(1LL << 2)	/* Division by zero */
     72 #define EXCSUM_OVF	(1LL << 3)	/* Overflow */
     73 #define EXCSUM_UNF	(1LL << 4)	/* Underflow */
     74 #define EXCSUM_INE	(1LL << 5)	/* Inexact result */
     75 #define EXCSUM_IOV	(1LL << 6)	/* Integer overflow */
     76 
     77 /*
     78  * Definitions for IEEE trap enables.  These are implemented in
     79  * software and should be compatible with OSF/1 and Linux.
     80  */
     81 
     82 /* read/write flags */
     83 #define IEEE_TRAP_ENABLE_INV	(1LL << 1) /* Invalid operation */
     84 #define IEEE_TRAP_ENABLE_DZE	(1LL << 2) /* Division by zero */
     85 #define IEEE_TRAP_ENABLE_OVF	(1LL << 3) /* Overflow */
     86 #define IEEE_TRAP_ENABLE_UNF	(1LL << 4) /* Underflow */
     87 #define IEEE_TRAP_ENABLE_INE	(1LL << 5) /* Inexact result */
     88 #define IEEE_TRAP_ENABLE_MASK	(IEEE_TRAP_ENABLE_INV		\
     89 				 | IEEE_TRAP_ENABLE_DZE		\
     90 				 | IEEE_TRAP_ENABLE_OVF		\
     91 				 | IEEE_TRAP_ENABLE_UNF		\
     92 				 | IEEE_TRAP_ENABLE_INE)
     93 
     94 /* read only flags */
     95 #define IEEE_STATUS_INV		(1LL << 17) /* Invalid operation */
     96 #define IEEE_STATUS_DZE		(1LL << 18) /* Division by zero */
     97 #define IEEE_STATUS_OVF		(1LL << 19) /* Overflow */
     98 #define IEEE_STATUS_UNF		(1LL << 20) /* Underflow */
     99 #define IEEE_STATUS_INE		(1LL << 21) /* Inexact result */
    100 #define IEEE_STATUS_MASK	(IEEE_STATUS_INV		\
    101 				 | IEEE_STATUS_DZE		\
    102 				 | IEEE_STATUS_OVF		\
    103 				 | IEEE_STATUS_UNF		\
    104 				 | IEEE_STATUS_INE)
    105 #define IEEE_STATUS_TO_EXCSUM_SHIFT	16 /* convert to excsum */
    106 #define IEEE_STATUS_TO_FPCR_SHIFT	35 /* convert to fpcr */
    107 
    108 #define IEEE_INHERIT		(1LL << 63) /* inherit on fork */
    109 
    110 /* read and write floating point control register */
    111 #define GET_FPCR(x) \
    112 	__asm__("trapb"); \
    113 	__asm__("mf_fpcr %0" : "=f" (x)); \
    114 	__asm__("trapb")
    115 #define SET_FPCR(x) \
    116 	__asm__("trapb"); \
    117 	__asm__("mt_fpcr %0" : : "f" (x)); \
    118 	__asm__("trapb")
    119 
    120 #ifdef KERNEL
    121 
    122 extern int fp_software_completion(u_int64_t regmask, struct proc *p);
    123 
    124 #endif
    125 
    126 #endif /* ! _MACHINE_FPU_H_ */
    127