fpu.h revision 1.9 1 /* $NetBSD: fpu.h,v 1.9 2025/02/24 21:32:26 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2001 Ross Harvey
5 * All rights reserved.
6 *
7 * This software was written for NetBSD.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the NetBSD
20 * Foundation, Inc. and its contributors.
21 * 4. Neither the name of The NetBSD Foundation nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _ALPHA_FPU_H_
39 #define _ALPHA_FPU_H_
40
41 /*
42 * Most of these next definitions were moved from <ieeefp.h>. Apparently the
43 * names happen to match those exported by Compaq and Linux from their fpu.h
44 * files.
45 */
46
47 /*
48 * Bits in the Alpha Floating Point Control register. This is the hardware
49 * register, and should not be directly manipulated by application software.
50 */
51 #define FPCR_SUM __BIT(63) /* Summary (OR of all exception bits) */
52 #define FPCR_INED __BIT(62) /* Inexact trap Disable */
53 #define FPCR_UNFD __BIT(61) /* Underflow trap Disable */
54 #define FPCR_UNDZ __BIT(60) /* Underflow to Zero */
55 #define FPCR_DYN_RM __BITS(58,59) /* Dynamic Rounding Mode */
56 /* 00 Chopped */
57 /* 01 Minus Infinity */
58 /* 10 Normal (round nearest) */
59 /* 11 Plus Infinity */
60 #define FPCR_IOV __BIT(57) /* Integer Overflow */
61 #define FPCR_INE __BIT(56) /* Inexact Result */
62 #define FPCR_UNF __BIT(55) /* Underflow */
63 #define FPCR_OVF __BIT(54) /* Overflow */
64 #define FPCR_DZE __BIT(53) /* Division By Zero */
65 #define FPCR_INV __BIT(52) /* Invalid Operation */
66 #define FPCR_OVFD __BIT(51) /* Overflow trap Disable */
67 #define FPCR_DZED __BIT(50) /* Division By Zero trap Disable */
68 #define FPCR_INVD __BIT(49) /* Invalid Operation trap Disable */
69 #define FPCR_DNZ __BIT(48) /* Denormal Operands to Zero */
70 #define FPCR_DNOD __BIT(47) /* Denormal Operation tap Disable */
71
72 #define FPCR_MIRRORED (FPCR_INE | FPCR_UNF | FPCR_OVF | FPCR_DZE | FPCR_INV)
73 #define FPCR_MIR_START 52
74
75 /* NetBSD default - no traps enabled, round-to-nearest */
76 #define FPCR_DEFAULT (__SHIFTIN(FP_RN, FPCR_DYN_RM) | \
77 FPCR_INED | FPCR_UNFD | FPCR_OVFD | \
78 FPCR_DZED | FPCR_INVD | FPCR_DNOD)
79
80 /*
81 * IEEE Floating Point Control (FP_C) Quadword. This is a software
82 * virtual register that abstracts the FPCR and software complation
83 * performed by the kernel.
84 *
85 * The AARM specifies the bit positions of the software word used for
86 * user mode interface to the control and status of the kernel completion
87 * routines. Although it largely just redefines the FPCR, it shuffles
88 * the bit order. The names of the bits are defined in the AARM, and
89 * the definition prefix can easily be determined from public domain
90 * programs written to either the Compaq or Linux interfaces, which
91 * appear to be identical.
92 *
93 * Bits 63-48 are reserved for implementation software.
94 * Bits 47-23 are reserved for future architecture definition.
95 * Bits 16-12 are reserved for implementation software.
96 * Bits 11-7 are reserved for future architecture definition.
97 * Bit 0 is reserved for implementation software.
98 */
99
100 #define IEEE_STATUS_DNO __BIT(22) /* Denormal Operand */
101 #define IEEE_STATUS_INE __BIT(21) /* Inexact Result */
102 #define IEEE_STATUS_UNF __BIT(20) /* Underflow */
103 #define IEEE_STATUS_OVF __BIT(19) /* Overflow */
104 #define IEEE_STATUS_DZE __BIT(18) /* Division By Zero */
105 #define IEEE_STATUS_INV __BIT(17) /* Invalid Operation */
106
107 #define IEEE_TRAP_ENABLE_DNO __BIT(6) /* Denormal Operation trap */
108 #define IEEE_TRAP_ENABLE_INE __BIT(5) /* Inexact Result trap */
109 #define IEEE_TRAP_ENABLE_UNF __BIT(4) /* Underflow trap */
110 #define IEEE_TRAP_ENABLE_OVF __BIT(3) /* Overflow trap */
111 #define IEEE_TRAP_ENABLE_DZE __BIT(2) /* Division By Zero trap */
112 #define IEEE_TRAP_ENABLE_INV __BIT(1) /* Invalid Operation trap */
113
114 #define IEEE_INHERIT __BIT(14)
115 #define IEEE_MAP_UMZ __BIT(13) /* Map underflowed outputs to zero */
116 #define IEEE_MAP_DMZ __BIT(12) /* Map denormal inputs to zero */
117
118 #define FP_C_ALLBITS __BITS(1,22)
119
120 #define FP_C_MIRRORED (IEEE_STATUS_INE | IEEE_STATUS_UNF | IEEE_STATUS_OVF \
121 | IEEE_STATUS_DZE | IEEE_STATUS_INV)
122 #define FP_C_MIR_START 17
123
124 /* NetBSD default - no traps enabled (see FPCR default) */
125 #define FP_C_DEFAULT 0
126
127 #ifdef _KERNEL
128
129 #define FLD_MASK(len) ((1UL << (len)) - 1)
130 #define FLD_CLEAR(obj, origin, len) \
131 ((obj) & ~(FLD_MASK(len) << (origin)))
132 #define FLD_INSERT(obj, origin, len, value) \
133 (FLD_CLEAR(obj, origin, len) | (value) << origin)
134
135 #define FP_C_TO_NETBSD_MASK(fp_c) ((fp_c) >> 1 & 0x3f)
136 #define FP_C_TO_NETBSD_FLAG(fp_c) ((fp_c) >> 17 & 0x3f)
137 #define NETBSD_MASK_TO_FP_C(m) (((m) & 0x3f) << 1)
138 #define NETBSD_FLAG_TO_FP_C(s) (((s) & 0x3f) << 17)
139 #define CLEAR_FP_C_MASK(fp_c) ((fp_c) & ~(0x3f << 1))
140 #define CLEAR_FP_C_FLAG(fp_c) ((fp_c) & ~(0x3f << 17))
141 #define SET_FP_C_MASK(fp_c, m) (CLEAR_FP_C_MASK(fp_c) | NETBSD_MASK_TO_FP_C(m))
142 #define SET_FP_C_FLAG(fp_c, m) (CLEAR_FP_C_FLAG(fp_c) | NETBSD_FLAG_TO_FP_C(m))
143
144 #endif /* _KERNEL */
145
146 #endif /* _ALPHA_FPU_H_ */
147