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intr.h revision 1.2 
      1  1.2  cgd /*	$NetBSD: intr.h,v 1.2 1996/07/09 00:33:25 cgd Exp $	*/
      2  1.1  cgd 
      3  1.1  cgd /*
      4  1.1  cgd  * Copyright (c) 1996 Carnegie-Mellon University.
      5  1.1  cgd  * All rights reserved.
      6  1.1  cgd  *
      7  1.1  cgd  * Author: Chris G. Demetriou
      8  1.1  cgd  *
      9  1.1  cgd  * Permission to use, copy, modify and distribute this software and
     10  1.1  cgd  * its documentation is hereby granted, provided that both the copyright
     11  1.1  cgd  * notice and this permission notice appear in all copies of the
     12  1.1  cgd  * software, derivative works or modified versions, and any portions
     13  1.1  cgd  * thereof, and that both notices appear in supporting documentation.
     14  1.1  cgd  *
     15  1.1  cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  1.1  cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  1.1  cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  1.1  cgd  *
     19  1.1  cgd  * Carnegie Mellon requests users of this software to return to
     20  1.1  cgd  *
     21  1.1  cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  1.1  cgd  *  School of Computer Science
     23  1.1  cgd  *  Carnegie Mellon University
     24  1.1  cgd  *  Pittsburgh PA 15213-3890
     25  1.1  cgd  *
     26  1.1  cgd  * any improvements or extensions that they make and grant Carnegie the
     27  1.1  cgd  * rights to redistribute these changes.
     28  1.1  cgd  */
     29  1.1  cgd 
     30  1.2  cgd #ifndef _ALPHA_INTR_H_
     31  1.2  cgd #define _ALPHA_INTR_H_
     32  1.2  cgd 
     33  1.1  cgd #define	IPL_NONE	0	/* disable only this interrupt */
     34  1.1  cgd #define	IPL_BIO		1	/* disable block I/O interrupts */
     35  1.1  cgd #define	IPL_NET		2	/* disable network interrupts */
     36  1.1  cgd #define	IPL_TTY		3	/* disable terminal interrupts */
     37  1.1  cgd #define	IPL_CLOCK	4	/* disable clock interrupts */
     38  1.1  cgd #define	IPL_HIGH	5	/* disable all interrupts */
     39  1.1  cgd 
     40  1.1  cgd #define	IST_NONE	0	/* none (dummy) */
     41  1.1  cgd #define	IST_PULSE	1	/* pulsed */
     42  1.1  cgd #define	IST_EDGE	2	/* edge-triggered */
     43  1.1  cgd #define	IST_LEVEL	3	/* level-triggered */
     44  1.2  cgd 
     45  1.2  cgd #define splx(s)								\
     46  1.2  cgd 	    (s == ALPHA_PSL_IPL_0 ? spl0() : alpha_pal_swpipl(s))
     47  1.2  cgd #define splsoft()               alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT)
     48  1.2  cgd #define splsoftclock()          splsoft()
     49  1.2  cgd #define splsoftnet()            splsoft()
     50  1.2  cgd #define splnet()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     51  1.2  cgd #define splbio()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     52  1.2  cgd #define splimp()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     53  1.2  cgd #define spltty()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     54  1.2  cgd #define splclock()              alpha_pal_swpipl(ALPHA_PSL_IPL_CLOCK)
     55  1.2  cgd #define splstatclock()          alpha_pal_swpipl(ALPHA_PSL_IPL_CLOCK)
     56  1.2  cgd #define splhigh()               alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH)
     57  1.2  cgd 
     58  1.2  cgd /*
     59  1.2  cgd  * simulated software interrupt register
     60  1.2  cgd  */
     61  1.2  cgd extern u_int64_t ssir;
     62  1.2  cgd 
     63  1.2  cgd #define	SIR_NET		0x1
     64  1.2  cgd #define	SIR_CLOCK	0x2
     65  1.2  cgd 
     66  1.2  cgd #define	siroff(x)	ssir &= ~(x)
     67  1.2  cgd #define	setsoftnet()	ssir |= SIR_NET
     68  1.2  cgd #define	setsoftclock()	ssir |= SIR_CLOCK
     69  1.2  cgd 
     70  1.2  cgd #endif
     71