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intr.h revision 1.2 
      1 /*	$NetBSD: intr.h,v 1.2 1996/07/09 00:33:25 cgd Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #ifndef _ALPHA_INTR_H_
     31 #define _ALPHA_INTR_H_
     32 
     33 #define	IPL_NONE	0	/* disable only this interrupt */
     34 #define	IPL_BIO		1	/* disable block I/O interrupts */
     35 #define	IPL_NET		2	/* disable network interrupts */
     36 #define	IPL_TTY		3	/* disable terminal interrupts */
     37 #define	IPL_CLOCK	4	/* disable clock interrupts */
     38 #define	IPL_HIGH	5	/* disable all interrupts */
     39 
     40 #define	IST_NONE	0	/* none (dummy) */
     41 #define	IST_PULSE	1	/* pulsed */
     42 #define	IST_EDGE	2	/* edge-triggered */
     43 #define	IST_LEVEL	3	/* level-triggered */
     44 
     45 #define splx(s)								\
     46 	    (s == ALPHA_PSL_IPL_0 ? spl0() : alpha_pal_swpipl(s))
     47 #define splsoft()               alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT)
     48 #define splsoftclock()          splsoft()
     49 #define splsoftnet()            splsoft()
     50 #define splnet()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     51 #define splbio()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     52 #define splimp()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     53 #define spltty()                alpha_pal_swpipl(ALPHA_PSL_IPL_IO)
     54 #define splclock()              alpha_pal_swpipl(ALPHA_PSL_IPL_CLOCK)
     55 #define splstatclock()          alpha_pal_swpipl(ALPHA_PSL_IPL_CLOCK)
     56 #define splhigh()               alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH)
     57 
     58 /*
     59  * simulated software interrupt register
     60  */
     61 extern u_int64_t ssir;
     62 
     63 #define	SIR_NET		0x1
     64 #define	SIR_CLOCK	0x2
     65 
     66 #define	siroff(x)	ssir &= ~(x)
     67 #define	setsoftnet()	ssir |= SIR_NET
     68 #define	setsoftclock()	ssir |= SIR_CLOCK
     69 
     70 #endif
     71