intr.h revision 1.49
1 /* $NetBSD: intr.h,v 1.49 2001/07/27 00:25:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 41 * Copyright (c) 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #ifndef _ALPHA_INTR_H_ 68 #define _ALPHA_INTR_H_ 69 70 #include <sys/device.h> 71 #include <sys/lock.h> 72 #include <sys/queue.h> 73 #include <machine/atomic.h> 74 75 /* 76 * The Alpha System Control Block. This is 8k long, and you get 77 * 16 bytes per vector (i.e. the vector numbers are spaced 16 78 * apart). 79 * 80 * This is sort of a "shadow" SCB -- rather than the CPU jumping 81 * to (SCBaddr + (16 * vector)), like it does on the VAX, we get 82 * a vector number in a1. We use the SCB to look up a routine/arg 83 * and jump to it. 84 * 85 * Since we use the SCB only for I/O interrupts, we make it shorter 86 * than normal, starting it at vector 0x800 (the start of the I/O 87 * interrupt vectors). 88 */ 89 #define SCB_IOVECBASE 0x0800 90 #define SCB_VECSIZE 0x0010 91 #define SCB_SIZE 0x2000 92 93 #define SCB_VECTOIDX(x) ((x) >> 4) 94 #define SCB_IDXTOVEC(x) ((x) << 4) 95 96 #define SCB_NIOVECS SCB_VECTOIDX(SCB_SIZE - SCB_IOVECBASE) 97 98 struct scbvec { 99 void (*scb_func)(void *, u_long); 100 void *scb_arg; 101 }; 102 103 /* 104 * Alpha interrupts come in at one of 4 levels: 105 * 106 * software interrupt level 107 * i/o level 1 108 * i/o level 2 109 * clock level 110 * 111 * However, since we do not have any way to know which hardware 112 * level a particular i/o interrupt comes in on, we have to 113 * whittle it down to 3. 114 */ 115 116 #define IPL_NONE 1 /* disable only this interrupt */ 117 #define IPL_BIO 1 /* disable block I/O interrupts */ 118 #define IPL_NET 1 /* disable network interrupts */ 119 #define IPL_TTY 1 /* disable terminal interrupts */ 120 #define IPL_CLOCK 2 /* disable clock interrupts */ 121 #define IPL_HIGH 3 /* disable all interrupts */ 122 #define IPL_SERIAL 1 /* disable serial interrupts */ 123 124 #define IPL_SOFTSERIAL 0 /* serial software interrupts */ 125 #define IPL_SOFTNET 1 /* network software interrupts */ 126 #define IPL_SOFTCLOCK 2 /* clock software interrupts */ 127 #define IPL_SOFT 3 /* other software interrupts */ 128 #define IPL_NSOFT 4 129 130 #define IPL_SOFTNAMES { \ 131 "serial", \ 132 "net", \ 133 "clock", \ 134 "misc", \ 135 } 136 137 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 138 #define IST_NONE 0 /* none (dummy) */ 139 #define IST_PULSE 1 /* pulsed */ 140 #define IST_EDGE 2 /* edge-triggered */ 141 #define IST_LEVEL 3 /* level-triggered */ 142 143 #ifdef _KERNEL 144 145 /* Simulated software interrupt register. */ 146 extern __volatile unsigned long ssir; 147 148 /* IPL-lowering/restoring macros */ 149 void spl0(void); 150 151 static __inline void 152 splx(int s) 153 { 154 if (s == ALPHA_PSL_IPL_0 && ssir != 0) 155 spl0(); 156 else 157 alpha_pal_swpipl(s); 158 } 159 #define spllowersoftclock() ((void)alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT)) 160 161 /* IPL-raising functions/macros */ 162 static __inline int 163 _splraise(int s) 164 { 165 int cur = alpha_pal_rdps() & ALPHA_PSL_IPL_MASK; 166 return (s > cur ? alpha_pal_swpipl(s) : cur); 167 } 168 #define splsoft() _splraise(ALPHA_PSL_IPL_SOFT) 169 #define splsoftserial() splsoft() 170 #define splsoftclock() splsoft() 171 #define splsoftnet() splsoft() 172 #define splnet() _splraise(ALPHA_PSL_IPL_IO) 173 #define splbio() _splraise(ALPHA_PSL_IPL_IO) 174 #define splvm() _splraise(ALPHA_PSL_IPL_IO) 175 #define spltty() _splraise(ALPHA_PSL_IPL_IO) 176 #define splserial() _splraise(ALPHA_PSL_IPL_IO) 177 #define splclock() _splraise(ALPHA_PSL_IPL_CLOCK) 178 #define splstatclock() _splraise(ALPHA_PSL_IPL_CLOCK) 179 #define splhigh() _splraise(ALPHA_PSL_IPL_HIGH) 180 181 #define splsched() splhigh() 182 #define spllock() splhigh() 183 #define splipi() splclock() /* AARM, 5-2, II-B */ 184 #define spllpt() spltty() 185 186 /* 187 * Interprocessor interrupts. In order how we want them processed. 188 */ 189 #define ALPHA_IPI_HALT (1UL << 0) 190 #define ALPHA_IPI_MICROSET (1UL << 1) 191 #define ALPHA_IPI_SHOOTDOWN (1UL << 2) 192 #define ALPHA_IPI_IMB (1UL << 3) 193 #define ALPHA_IPI_AST (1UL << 4) 194 #define ALPHA_IPI_SYNCH_FPU (1UL << 5) 195 #define ALPHA_IPI_DISCARD_FPU (1UL << 6) 196 #define ALPHA_IPI_PAUSE (1UL << 7) 197 #define ALPHA_IPI_PMAP_REACTIVATE (1UL << 8) 198 199 #define ALPHA_NIPIS 9 /* must not exceed 64 */ 200 201 struct cpu_info; 202 struct trapframe; 203 204 void alpha_ipi_init(struct cpu_info *); 205 void alpha_ipi_process(struct cpu_info *, struct trapframe *); 206 void alpha_send_ipi(unsigned long, unsigned long); 207 void alpha_broadcast_ipi(unsigned long); 208 void alpha_multicast_ipi(unsigned long, unsigned long); 209 210 /* 211 * Alpha shared-interrupt-line common code. 212 */ 213 214 struct alpha_shared_intrhand { 215 TAILQ_ENTRY(alpha_shared_intrhand) 216 ih_q; 217 struct alpha_shared_intr *ih_intrhead; 218 int (*ih_fn)(void *); 219 void *ih_arg; 220 int ih_level; 221 unsigned int ih_num; 222 }; 223 224 struct alpha_shared_intr { 225 TAILQ_HEAD(,alpha_shared_intrhand) 226 intr_q; 227 struct evcnt intr_evcnt; 228 char *intr_string; 229 void *intr_private; 230 int intr_sharetype; 231 int intr_dfltsharetype; 232 int intr_nstrays; 233 int intr_maxstrays; 234 }; 235 236 #define ALPHA_SHARED_INTR_DISABLE(asi, num) \ 237 ((asi)[num].intr_maxstrays != 0 && \ 238 (asi)[num].intr_nstrays == (asi)[num].intr_maxstrays) 239 240 #define setsoft(x) atomic_setbits_ulong(&ssir, 1 << (x)) 241 242 struct alpha_soft_intrhand { 243 TAILQ_ENTRY(alpha_soft_intrhand) 244 sih_q; 245 struct alpha_soft_intr *sih_intrhead; 246 void (*sih_fn)(void *); 247 void *sih_arg; 248 int sih_pending; 249 }; 250 251 struct alpha_soft_intr { 252 TAILQ_HEAD(, alpha_soft_intrhand) 253 softintr_q; 254 struct evcnt softintr_evcnt; 255 struct simplelock softintr_slock; 256 unsigned long softintr_ipl; 257 }; 258 259 void *softintr_establish(int, void (*)(void *), void *); 260 void softintr_disestablish(void *); 261 void softintr_init(void); 262 void softintr_dispatch(void); 263 264 #define softintr_schedule(arg) \ 265 do { \ 266 struct alpha_soft_intrhand *__sih = (arg); \ 267 struct alpha_soft_intr *__si = __sih->sih_intrhead; \ 268 int __s; \ 269 \ 270 __s = splhigh(); \ 271 simple_lock(&__si->softintr_slock); \ 272 if (__sih->sih_pending == 0) { \ 273 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 274 __sih->sih_pending = 1; \ 275 setsoft(__si->softintr_ipl); \ 276 } \ 277 simple_unlock(&__si->softintr_slock); \ 278 splx(__s); \ 279 } while (0) 280 281 /* XXX For legacy software interrupts. */ 282 extern struct alpha_soft_intrhand *softnet_intrhand; 283 284 #define setsoftnet() softintr_schedule(softnet_intrhand) 285 286 struct alpha_shared_intr *alpha_shared_intr_alloc(unsigned int, unsigned int); 287 int alpha_shared_intr_dispatch(struct alpha_shared_intr *, 288 unsigned int); 289 void *alpha_shared_intr_establish(struct alpha_shared_intr *, 290 unsigned int, int, int, int (*)(void *), void *, const char *); 291 void alpha_shared_intr_disestablish(struct alpha_shared_intr *, 292 void *, const char *); 293 int alpha_shared_intr_get_sharetype(struct alpha_shared_intr *, 294 unsigned int); 295 int alpha_shared_intr_isactive(struct alpha_shared_intr *, 296 unsigned int); 297 int alpha_shared_intr_firstactive(struct alpha_shared_intr *, 298 unsigned int); 299 void alpha_shared_intr_set_dfltsharetype(struct alpha_shared_intr *, 300 unsigned int, int); 301 void alpha_shared_intr_set_maxstrays(struct alpha_shared_intr *, 302 unsigned int, int); 303 void alpha_shared_intr_stray(struct alpha_shared_intr *, unsigned int, 304 const char *); 305 void alpha_shared_intr_set_private(struct alpha_shared_intr *, 306 unsigned int, void *); 307 void *alpha_shared_intr_get_private(struct alpha_shared_intr *, 308 unsigned int); 309 char *alpha_shared_intr_string(struct alpha_shared_intr *, 310 unsigned int); 311 struct evcnt *alpha_shared_intr_evcnt(struct alpha_shared_intr *, 312 unsigned int); 313 314 extern struct scbvec scb_iovectab[]; 315 316 void scb_init(void); 317 void scb_set(u_long, void (*)(void *, u_long), void *); 318 u_long scb_alloc(void (*)(void *, u_long), void *); 319 void scb_free(u_long); 320 321 #define SCB_ALLOC_FAILED ((u_long) -1) 322 323 #endif /* _KERNEL */ 324 #endif /* ! _ALPHA_INTR_H_ */ 325
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