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psl.h revision 1.1 
      1 /*	$NetBSD: psl.h,v 1.1 1995/02/13 23:07:49 cgd Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 /*
     31  * Processor Status register definitions.
     32  */
     33 #define	PSL_U		0x08		/* PS<3> == 1 -> User mode */
     34 #define	PSL_IPL		0x07		/* PS<2:0> -> Interrupt mask */
     35 
     36 /*
     37  * The interrupt priority levels.
     38  * Other IPL's are configured in software, and are listed below.
     39  */
     40 #define	PSL_IPL_0	0		/* all interrupts enabled */
     41 #define PSL_IPL_SOFT	1		/* block software interrupts */
     42 #define	PSL_IPL_IO	4		/* block I/O device interrupts */
     43 #define	PSL_IPL_CLOCK	5		/* block clock interrupts */
     44 #define	PSL_IPL_HIGH	6		/* block everything except mchecks */
     45 
     46 /*
     47  * Miscellaneous PSL definitions
     48  */
     49 #define	PSL_MBZ		(0xfffffffffffffff0)	/* Must be always zero */
     50 #define	PSL_USERSET	(PSL_U)			/* Must be set for user-mode */
     51 #define	PSL_USERCLR	(PSL_MBZ|PSL_IPL)	/* Must be clr for user-mode */
     52 #define	USERMODE(ps)	((ps & PSL_U) != 0)	/* Is it user-mode? */
     53 
     54 #ifdef KERNEL
     55 /*
     56  * Translation buffer invalidation macro definitions.
     57  */
     58 #define	TBI_A		-2		/* Flush all TB entries */
     59 #define	TBI_AP		-1		/* Flush all per-process TB entries */
     60 #define	TBI_SI		1		/* Invalidate ITB entry for va */
     61 #define	TBI_SD		2		/* Invalidate DTB entry for va */
     62 #define	TBI_S		3		/* Invalidate all entries for va */
     63 
     64 #define	TBIA()		pal_tbi(TBI_A, NULL)
     65 #define	TBIAP()		pal_tbi(TBI_AP, NULL)
     66 #define	TBISI(va)	pal_tbi(TBI_SI, va)
     67 #define	TBISD(va)	pal_tbi(TBI_SD, va)
     68 #define	TBIS(va)	pal_tbi(TBI_S, va)
     69 
     70 /*
     71  * Cache invalidation/flush routines.
     72  */
     73 #define	MB()		alpha_mb()	/* Flush all write buffers */
     74 #define	IMB()		pal_imb()	/* Sync instruction cache w/data */
     75 
     76 void alpha_mb __P((void));		/* Flush all write buffers */
     77 void pal_imb __P((void));		/* Sync instruction cache */
     78 u_int64_t pal_swpipl __P((u_int64_t));	/* write new IPL, return old */
     79 void pal_tbi __P((u_int64_t, void *));	/* Invalidate TLB entries */
     80 #endif /* KERNEL */
     81