pte.h revision 1.8 1 1.8 cgd /* $NetBSD: pte.h,v 1.8 1996/11/13 22:21:04 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.8 cgd * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.1 cgd
30 1.1 cgd /*
31 1.1 cgd * Alpha page table entry.
32 1.1 cgd * Things which are in the VMS PALcode but not in the OSF PALcode
33 1.1 cgd * are marked with "(VMS)".
34 1.1 cgd *
35 1.1 cgd * This information derived from pp. (II) 3-3 - (II) 3-6 and
36 1.1 cgd * (III) 3-3 - (III) 3-5 of the "Alpha Architecture Reference Manual" by
37 1.1 cgd * Richard L. Sites.
38 1.1 cgd */
39 1.1 cgd
40 1.1 cgd /*
41 1.1 cgd * Alpha Page Table Entry
42 1.1 cgd */
43 1.5 cgd
44 1.5 cgd #include <machine/alpha_cpu.h>
45 1.5 cgd
46 1.5 cgd typedef alpha_pt_entry_t pt_entry_t;
47 1.5 cgd
48 1.1 cgd #define PT_ENTRY_NULL ((pt_entry_t *) 0)
49 1.1 cgd #define PTESHIFT 3 /* pte size == 1 << PTESHIFT */
50 1.1 cgd
51 1.5 cgd #define PG_V ALPHA_PTE_VALID
52 1.5 cgd #define PG_NV 0
53 1.5 cgd #define PG_FOR ALPHA_PTE_FAULT_ON_READ
54 1.5 cgd #define PG_FOW ALPHA_PTE_FAULT_ON_WRITE
55 1.5 cgd #define PG_FOE ALPHA_PTE_FAULT_ON_EXECUTE
56 1.5 cgd #define PG_ASM ALPHA_PTE_ASM
57 1.5 cgd #define PG_GH ALPHA_PTE_GRANULARITY
58 1.5 cgd #define PG_KRE ALPHA_PTE_KR
59 1.5 cgd #define PG_URE ALPHA_PTE_UR
60 1.5 cgd #define PG_KWE ALPHA_PTE_KW
61 1.5 cgd #define PG_UWE ALPHA_PTE_UW
62 1.5 cgd #define PG_PROT ALPHA_PTE_PROT
63 1.1 cgd #define PG_RSVD 0x000000000000cc80 /* Reserved fpr hardware */
64 1.1 cgd #define PG_WIRED 0x0000000000010000 /* Wired. [SOFTWARE] */
65 1.5 cgd #define PG_FRAME ALPHA_PTE_RAME
66 1.1 cgd #define PG_SHIFT 32
67 1.5 cgd #define PG_PFNUM(x) ALPHA_PTE_TO_PFN(x)
68 1.1 cgd
69 1.5 cgd #if 0 /* XXX NOT HERE */
70 1.1 cgd #define K0SEG_BEGIN 0xfffffc0000000000 /* unmapped, cached */
71 1.1 cgd #define K0SEG_END 0xfffffe0000000000
72 1.1 cgd #define PHYS_UNCACHED 0x0000000040000000
73 1.5 cgd #endif
74 1.1 cgd
75 1.4 mycroft #ifndef _LOCORE
76 1.5 cgd #if 0 /* XXX NOT HERE */
77 1.1 cgd #define k0segtophys(x) ((vm_offset_t)(x) & 0x00000003ffffffff)
78 1.1 cgd #define phystok0seg(x) ((vm_offset_t)(x) | K0SEG_BEGIN)
79 1.1 cgd
80 1.1 cgd #define phystouncached(x) ((vm_offset_t)(x) | PHYS_UNCACHED)
81 1.1 cgd #define uncachedtophys(x) ((vm_offset_t)(x) & ~PHYS_UNCACHED)
82 1.5 cgd #endif
83 1.1 cgd
84 1.1 cgd #define PTEMASK (NPTEPG - 1)
85 1.1 cgd #define vatopte(va) (((va) >> PGSHIFT) & PTEMASK)
86 1.1 cgd #define vatoste(va) (((va) >> SEGSHIFT) & PTEMASK)
87 1.7 cgd #define kvtol1pte(va) \
88 1.7 cgd (((vm_offset_t)(va) >> (PGSHIFT + 2*(PGSHIFT-PTESHIFT))) & PTEMASK)
89 1.7 cgd
90 1.1 cgd #define vatopa(va) \
91 1.1 cgd ((PG_PFNUM(*kvtopte(va)) << PGSHIFT) | ((vm_offset_t)(va) & PGOFSET))
92 1.1 cgd
93 1.3 cgd #define ALPHA_STSIZE ((u_long)NBPG) /* 8k */
94 1.3 cgd #define ALPHA_MAX_PTSIZE ((u_long)(NPTEPG * NBPG)) /* 8M */
95 1.1 cgd
96 1.3 cgd #ifdef _KERNEL
97 1.1 cgd /*
98 1.1 cgd * Kernel virtual address to Sysmap entry and visa versa.
99 1.1 cgd */
100 1.1 cgd #define kvtopte(va) \
101 1.1 cgd (Sysmap + (((vm_offset_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT))
102 1.1 cgd #define ptetokv(pte) \
103 1.1 cgd ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
104 1.1 cgd
105 1.1 cgd #define loadustp(stpte) { \
106 1.1 cgd Lev1map[kvtol1pte(VM_MIN_ADDRESS)] = stpte; \
107 1.6 cgd ALPHA_TBIAP(); \
108 1.1 cgd }
109 1.1 cgd
110 1.1 cgd extern pt_entry_t *Lev1map; /* Alpha Level One page table */
111 1.1 cgd extern pt_entry_t *Sysmap; /* kernel pte table */
112 1.1 cgd extern vm_size_t Sysmapsize; /* number of pte's in Sysmap */
113 1.3 cgd #endif
114 1.1 cgd #endif
115