rpb.h revision 1.1
1 /* $NetBSD: rpb.h,v 1.1 1995/02/13 23:07:54 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * From DEC 3000 300/400/500/600/800 System Programmer's Manual, 32 * EK-D3SYS-PM.A01. 33 */ 34 35 /* 36 * HWRPB (Hardware Restart Parameter Block). 37 */ 38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 39 40 #ifndef ASSEMBLER 41 struct rpb { 42 struct restart_blk *rpb; /* 0: HWRPB phys. address. */ 43 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 44 u_int64_t rpb_version; /* 10 */ 45 u_int64_t rpb_size; /* 18: HWRPB size in bytes */ 46 u_int64_t rpb_primary_cpu_id; /* 20 */ 47 u_int64_t rpb_page_size; /* 28: (8192) */ 48 u_int64_t rpb_phys_addr_size; /* 30: (34) */ 49 u_int64_t rpb_max_asn; /* 38: (16) */ 50 char rpb_ssn[16]; /* 40: only first 10 valid */ 51 52 #define ST_ADU 1 53 #define ST_DEC_4000 2 54 #define ST_DEC_7000 3 55 #define ST_DEC_3000_500 4 56 #define ST_DEC_2000_300 6 57 #define ST_DEC_3000_300 7 58 u_int64_t rpb_type; /* 50: */ 59 60 #define SYSTEM_VAR_MPCAP 0x0001 /* multiprocessor */ 61 62 #define SYSTEM_VAR_CONSOLE 0x001e /* console hardware mask */ 63 #define SYSTEM_VAR_CNSL_DETACHED 0x0002 64 #define SYSTEM_VAR_CNSL_EMBEDDED 0x0004 65 66 #define SYSTEM_VAR_POWERFAIL 0x00e0 /* powerfail mask */ 67 #define SYSTEM_VAR_PF_UNITED 0x0020 68 #define SYSTEM_VAR_PF_SEPARATE 0x0040 69 #define SYSTEM_VAR_PF_BBACKUP 0x0060 70 #define SYSTEM_VAR_PF_ACTION 0x0100 /* 1 -> restart all processors 71 * on powerfail 72 * 0 -> only primary 73 */ 74 #define SYSTEM_VAR_GRAPHICS 0x0200 /* graphic engine present */ 75 #define SYSTEM_VAR_mbz 0xfffffffffffffc00 /* 10:64 -- must be zero */ 76 u_int64_t rpb_variation; /* 58 */ 77 78 char rpb_revision[8]; /* 60; only first 4 valid */ 79 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ 80 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 81 vm_offset_t rpb_vptb; /* 78: */ 82 u_int64_t rpb_reserved_arch; /* 80: */ 83 vm_offset_t rpb_tbhint_off; /* 88: */ 84 u_int64_t rpb_pcs_cnt; /* 90: */ 85 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ 86 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ 87 u_int64_t rpb_ctb_cnt; /* A8: console terminal */ 88 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ 89 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ 90 vm_offset_t rpb_crb_off; /* C0: offset to crb */ 91 vm_offset_t rpb_memdat_off; /* C8: memory data offset */ 92 vm_offset_t rpb_condat_off; /* D0: config data offset */ 93 vm_offset_t rpb_fru_off; /* D8: FRU table offset */ 94 long (*rpb_save_term)(); /* E0: terminal save */ 95 long rpb_save_term_val; /* E8: */ 96 long (*rpb_rest_term)(); /* F0: terminal restore */ 97 long rpb_rest_term_val; /* F8: */ 98 long (*rpb_restart)(); /* 100: restart */ 99 long rpb_restart_val; /* 108: */ 100 u_int64_t rpb_reserve_os; /* 110: */ 101 u_int64_t rpb_reserve_hw; /* 118: */ 102 u_int64_t rpb_checksum; /* 120: HWRPB checksum */ 103 u_int64_t rpb_rxrdy; /* 128: receive ready */ 104 u_int64_t rpb_txrdy; /* 130: transmit ready */ 105 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 106 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ 107 }; 108 109 #ifdef KERNEL 110 extern struct rpb *hwrpb; 111 #endif 112 113 /* 114 * PCS: Per-CPU information. 115 */ 116 struct pcs { 117 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 118 119 #define PCS_BIP 0x000001 /* boot in progress */ 120 #define PCS_RIP 0x000002 /* restart in progress */ 121 #define PCS_PA 0x000004 /* processor available */ 122 #define PCS_PP 0x000008 /* processor present */ 123 #define PCS_OH 0x000010 /* user halted */ 124 #define PCS_CV 0x000020 /* context valid */ 125 #define PCS_PV 0x000040 /* PALcode valid */ 126 #define PCS_PMV 0x000080 /* PALcode memory valid */ 127 #define PCS_PL 0x000100 /* PALcode loaded */ 128 #define PCS_PE 0x000200 /* primary eligible (SMP) */ 129 130 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 131 #define PCS_HALT_DEFAULT 0x000000 132 #define PCS_HALT_SAVE_EXIT 0x010000 133 #define PCS_HALT_COLD_BOOT 0x020000 134 #define PCS_HALT_WARM_BOOT 0x030000 135 #define PCS_HALT_STAY_HALTED 0x040000 136 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 137 u_int64_t pcs_flags; /* 80: */ 138 139 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ 140 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 141 vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ 142 vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ 143 struct { 144 u_int64_t 145 pcs_alpha : 8, /* alphabetic char 'a' - 'z' */ 146 #define PAL_TYPE_STANDARD 0 147 #define PAL_TYPE_ULTRIX 1 148 pcs_pal_type : 8, /* PALcode type: 149 * 0 == standard 150 * 1 == Ultrix 151 * 2-127 DIGITAL reserv. 152 * 128-255 non-DIGITAL reserv. 153 */ 154 sbz1 : 16, 155 pcs_proc_cnt : 7, /* Processor count */ 156 sbz2 : 25; 157 } pcs_pal_rev; /* A8: */ 158 #define pcs_alpha pcs_pal_rev.alpha 159 #define pcs_pal_type pcs_pal_rev.pal_type 160 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 161 162 u_int64_t pcs_proc_type; /* B0: (always 2) */ 163 struct { 164 u_int64_t 165 pcs_vaxfp : 1, /* Vax floating point */ 166 pcs_ieeefp : 1, /* IEEE floating point */ 167 pcs_reserved : 62; 168 } pcs_proc_var; /* B8: */ 169 #define pcs_vaxfp pcs_proc_var.pcs_vaxfp 170 #define pcs_ieeefp pcs_proc_var.pcs_ieeefp 171 172 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 173 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 174 vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ 175 u_int64_t pcs_machcheck_len; /* E0: length in bytes */ 176 vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 177 vm_offset_t pcs_halt_pc; /* F0: halt PC */ 178 u_int64_t pcs_halt_ps; /* F8: halt PS */ 179 u_int64_t pcs_halt_r25; /* 100: halt argument list */ 180 u_int64_t pcs_halt_r26; /* 108: halt return addr list */ 181 u_int64_t pcs_halt_r27; /* 110: halt procedure value */ 182 183 #define PCS_HALT_RESERVED 0 184 #define PCS_HALT_POWERUP 1 185 #define PCS_HALT_CONSOLE_HALT 2 186 #define PCS_HALT_CONSOLE_CRASH 3 187 #define PCS_HALT_KERNEL_MODE 4 188 #define PCS_HALT_KERNEL_STACK_INVALID 5 189 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 190 #define PCS_HALT_SCBB 7 191 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 192 u_int64_t pcs_halt_reason; /* 118: */ 193 194 u_int64_t pcs_reserved_soft; /* 120: preserved software */ 195 u_int64_t pcs_buffer[21]; /* 128: console buffers */ 196 197 #define PALvar_reserved 0 198 #define PALvar_OpenVMS 1 199 #define PALvar_OSF1 2 200 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 201 202 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 203 }; 204 205 /* 206 * CTB: Console Terminal Block 207 */ 208 struct ctb { 209 u_int64_t ctb_type; /* 0: always 4 */ 210 u_int64_t ctb_unit; /* 8: */ 211 u_int64_t ctb_reserved; /* 16: */ 212 u_int64_t ctb_len; /* 24: bytes of info */ 213 u_int64_t ctb_ipl; /* 32: console ipl level */ 214 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ 215 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ 216 217 #define CTB_GRAPHICS 3 /* graphics device */ 218 #define CTB_NETWORK 0xC0 /* network device */ 219 #define CTB_PRINTERPORT 2 /* printer port on the SCC */ 220 u_int64_t ctb_term_type; /* 56: terminal type */ 221 222 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ 223 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ 224 vm_offset_t ctb_keybd_map; /* 80: map table addr */ 225 u_int64_t ctb_keybd_state; /* 88: keyboard flags */ 226 u_int64_t ctb_keybd_last; /* 96: last key entered */ 227 vm_offset_t ctb_font_us; /* 104: US font table addr */ 228 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ 229 u_int64_t ctb_font_width; /* 120: font width, height */ 230 u_int64_t ctb_font_height; /* 128: in pixels */ 231 u_int64_t ctb_mon_width; /* 136: monitor width, height */ 232 u_int64_t ctb_mon_height; /* 144: in pixels */ 233 u_int64_t ctb_dpi; /* 152: monitor dots per inch */ 234 u_int64_t ctb_planes; /* 160: # of planes */ 235 u_int64_t ctb_cur_width; /* 168: cursor width, height */ 236 u_int64_t ctb_cur_height; /* 176: in pixels */ 237 u_int64_t ctb_head_cnt; /* 184: # of heads */ 238 u_int64_t ctb_opwindow; /* 192: opwindow on screen */ 239 vm_offset_t ctb_head_offset; /* 200: offset to head info */ 240 vm_offset_t ctb_putchar; /* 208: output char to TURBO */ 241 u_int64_t ctb_io_state; /* 216: I/O flags */ 242 u_int64_t ctb_listen_state; /* 224: listener flags */ 243 vm_offset_t ctb_xaddr; /* 232: extended info addr */ 244 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 245 u_int64_t ctb_server_off; /* 256: offset to server info */ 246 u_int64_t ctb_line_off; /* 264: line parameter offset */ 247 u_int8_t ctb_csd; /* 272: console specific data */ 248 }; 249 250 /* 251 * CRD: Console Routine Descriptor 252 */ 253 struct crd { 254 int64_t descriptor; 255 int (*code)(); 256 }; 257 258 /* 259 * CRB: Console Routine Block 260 */ 261 struct crb { 262 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 263 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ 264 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 265 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ 266 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ 267 u_int64_t crb_page_cnt; /* 28: pages to be mapped */ 268 }; 269 270 /* 271 * MDDT: Memory Data Descriptor Table 272 */ 273 struct mddt { 274 int64_t mddt_cksum; /* 0: 7-N checksum */ 275 vm_offset_t mddt_physaddr; /* 8: bank config addr 276 * IMPLEMENTATION SPECIFIC 277 */ 278 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ 279 struct { 280 vm_offset_t mddt_pfn; /* 0: starting PFN */ 281 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ 282 u_int64_t mddt_pg_test; /* 10: tested page count */ 283 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ 284 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ 285 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 286 287 #define MDDT_PALCODE 0x01 /* console and PAL only */ 288 #define MDDT_SYSTEM 0x00 /* system software only */ 289 #define MDDT_mbz 0xfffffffffffffffe /* 1:63 -- must be zero */ 290 int64_t mddt_usage; /* 30: bitmap permissions */ 291 } mddt_clusters[1]; /* variable length array */ 292 }; 293 #endif /* ASSEMBLER */ 294
Indexes created Wed Oct 01 07:09:59 GMT 2025