rpb.h revision 1.10
1 /* $NetBSD: rpb.h,v 1.10 1996/11/13 22:21:05 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, 32 * EK-D3SYS-PM.B01. 33 */ 34 35 /* 36 * HWRPB (Hardware Restart Parameter Block). 37 */ 38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 39 40 #ifndef ASSEMBLER 41 struct rpb { 42 struct restart_blk *rpb; /* 0: HWRPB phys. address. */ 43 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 44 u_int64_t rpb_version; /* 10 */ 45 u_int64_t rpb_size; /* 18: HWRPB size in bytes */ 46 u_int64_t rpb_primary_cpu_id; /* 20 */ 47 u_int64_t rpb_page_size; /* 28: (8192) */ 48 u_int64_t rpb_phys_addr_size; /* 30: (34) */ 49 u_int64_t rpb_max_asn; /* 38: (16) */ 50 char rpb_ssn[16]; /* 40: only first 10 valid */ 51 52 #define ST_ADU 1 /* Alpha Demo. Unit (?) */ 53 #define ST_DEC_4000 2 /* "Cobra" (?) */ 54 #define ST_DEC_7000 3 /* "Ruby" (?) */ 55 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ 56 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ 57 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ 58 #define ST_DEC_2100_A500 9 /* "Sable" (?) */ 59 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME?) */ 60 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ 61 #define ST_DEC_21000 12 /* "TurboLaser" (?) */ 62 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ 63 #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */ 64 #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ 65 #define ST_DEC_1000 17 /* "Mikasa" (PCI/ISA?) */ 66 #define ST_EB66 19 /* EB66 (PCI/ISA?) */ 67 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ 68 #define ST_DEC_4100 22 /* "Rawhide" (?) */ 69 #define ST_DEC_EV45_PBP 23 /* "Lego" (?) */ 70 #define ST_DEC_2100A_A500 24 /* "Lynx" (?) */ 71 #define ST_EB164 26 /* EB164 (PCI/ISA) */ 72 #define ST_DEC_1000A 27 /* "Noritake" (?) */ 73 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" (?) */ 74 75 u_int64_t rpb_type; /* 50: */ 76 77 #define SV_MPCAP 0x00000001 /* multiprocessor capable */ 78 79 #define SV_CONSOLE 0x0000001e /* console hardware mask */ 80 #define SV_CONSOLE_DETACHED 0x00000002 81 #define SV_CONSOLE_EMBEDDED 0x00000004 82 83 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ 84 #define SV_PF_UNITED 0x00000020 85 #define SV_PF_SEPARATE 0x00000040 86 #define SV_PF_BBACKUP 0x00000060 87 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ 88 89 #define SV_GRAPHICS 0x00000200 /* graphic engine present */ 90 91 #define SV_ST_MASK 0x0000fc00 /* system type mask */ 92 #define SV_ST_RESERVED 0x00000000 /* RESERVED */ 93 94 /* 95 * System types for the DEC 3000/500 (Flamingo) Family 96 */ 97 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ 98 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ 99 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ 100 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ 101 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ 102 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ 103 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ 104 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ 105 106 /* 107 * System types for ??? 108 */ 109 #define SV_ST_SABLE 0x00000400 /* Sable (???) */ 110 111 /* 112 * System types for the DEC 3000/300 (Pelican) Family 113 */ 114 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ 115 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ 116 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ 117 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ 118 119 /* 120 * System types for the AlphaStation Family 121 */ 122 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ 123 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ 124 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ 125 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ 126 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ 127 128 u_int64_t rpb_variation; /* 58 */ 129 130 char rpb_revision[8]; /* 60; only first 4 valid */ 131 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ 132 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 133 vm_offset_t rpb_vptb; /* 78: */ 134 u_int64_t rpb_reserved_arch; /* 80: */ 135 vm_offset_t rpb_tbhint_off; /* 88: */ 136 u_int64_t rpb_pcs_cnt; /* 90: */ 137 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ 138 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ 139 u_int64_t rpb_ctb_cnt; /* A8: console terminal */ 140 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ 141 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ 142 vm_offset_t rpb_crb_off; /* C0: offset to crb */ 143 vm_offset_t rpb_memdat_off; /* C8: memory data offset */ 144 vm_offset_t rpb_condat_off; /* D0: config data offset */ 145 vm_offset_t rpb_fru_off; /* D8: FRU table offset */ 146 u_int64_t rpb_save_term; /* E0: terminal save */ 147 u_int64_t rpb_save_term_val; /* E8: */ 148 u_int64_t rpb_rest_term; /* F0: terminal restore */ 149 u_int64_t rpb_rest_term_val; /* F8: */ 150 u_int64_t rpb_restart; /* 100: restart */ 151 u_int64_t rpb_restart_val; /* 108: */ 152 u_int64_t rpb_reserve_os; /* 110: */ 153 u_int64_t rpb_reserve_hw; /* 118: */ 154 u_int64_t rpb_checksum; /* 120: HWRPB checksum */ 155 u_int64_t rpb_rxrdy; /* 128: receive ready */ 156 u_int64_t rpb_txrdy; /* 130: transmit ready */ 157 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 158 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ 159 }; 160 161 /* 162 * PCS: Per-CPU information. 163 */ 164 struct pcs { 165 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 166 167 #define PCS_BIP 0x000001 /* boot in progress */ 168 #define PCS_RC 0x000002 /* restart possible */ 169 #define PCS_PA 0x000004 /* processor available */ 170 #define PCS_PP 0x000008 /* processor present */ 171 #define PCS_OH 0x000010 /* user halted */ 172 #define PCS_CV 0x000020 /* context valid */ 173 #define PCS_PV 0x000040 /* PALcode valid */ 174 #define PCS_PMV 0x000080 /* PALcode memory valid */ 175 #define PCS_PL 0x000100 /* PALcode loaded */ 176 177 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 178 #define PCS_HALT_DEFAULT 0x000000 179 #define PCS_HALT_SAVE_EXIT 0x010000 180 #define PCS_HALT_COLD_BOOT 0x020000 181 #define PCS_HALT_WARM_BOOT 0x030000 182 #define PCS_HALT_STAY_HALTED 0x040000 183 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 184 u_int64_t pcs_flags; /* 80: */ 185 186 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ 187 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 188 vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ 189 vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ 190 struct { 191 u_int64_t 192 pcs_alpha : 8, /* alphabetic char 'a' - 'z' */ 193 #define PAL_TYPE_STANDARD 0 194 #define PAL_TYPE_VMS 1 195 #define PAL_TYPE_OSF1 2 196 pcs_pal_type : 8, /* PALcode type: 197 * 0 == standard 198 * 1 == OpenVMS 199 * 2 == OSF/1 200 * 3-127 DIGITAL reserv. 201 * 128-255 non-DIGITAL reserv. 202 */ 203 sbz1 : 16, 204 pcs_proc_cnt : 7, /* Processor count */ 205 sbz2 : 25; 206 } pcs_pal_rev; /* A8: */ 207 #define pcs_alpha pcs_pal_rev.alpha 208 #define pcs_pal_type pcs_pal_rev.pal_type 209 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 210 211 u_int64_t pcs_proc_type; /* B0: processor type */ 212 213 #define PCS_PROC_MAJOR 0x00000000ffffffff 214 #define PCS_PROC_MAJORSHIFT 0 215 #define PCS_PROC_EV3 1 /* EV3 */ 216 #define PCS_PROC_EV4 2 /* EV4: 21064 */ 217 #define PCS_PROC_SIMULATOR 3 /* simulator? */ 218 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ 219 #define PCS_PROC_EV5 5 /* EV5: 21164 */ 220 #define PCS_PROC_EV45 6 /* EV4.5: 21064A */ 221 #define PCS_PROC_EV56 7 /* EV5.6: 21164A */ 222 223 #define PCS_PROC_MINOR 0xffffffff00000000 224 #define PCS_PROC_MINORSHIFT 32 225 #define PCS_PROC_PASS2 0 /* pass 2 or 2.1 */ 226 #define PCS_PROC_PASS3 1 /* pass 3 */ 227 /* 4 == ev4s? or 1 == ... ? */ 228 /* minor on the LCA appears to be pass number */ 229 230 u_int64_t pcs_proc_var; /* B8: processor variation. */ 231 232 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ 233 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ 234 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ 235 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ 236 237 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 238 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 239 vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ 240 u_int64_t pcs_machcheck_len; /* E0: length in bytes */ 241 vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 242 vm_offset_t pcs_halt_pc; /* F0: halt PC */ 243 u_int64_t pcs_halt_ps; /* F8: halt PS */ 244 u_int64_t pcs_halt_r25; /* 100: halt argument list */ 245 u_int64_t pcs_halt_r26; /* 108: halt return addr list */ 246 u_int64_t pcs_halt_r27; /* 110: halt procedure value */ 247 248 #define PCS_HALT_RESERVED 0 249 #define PCS_HALT_POWERUP 1 250 #define PCS_HALT_CONSOLE_HALT 2 251 #define PCS_HALT_CONSOLE_CRASH 3 252 #define PCS_HALT_KERNEL_MODE 4 253 #define PCS_HALT_KERNEL_STACK_INVALID 5 254 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 255 #define PCS_HALT_SCBB 7 256 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 257 u_int64_t pcs_halt_reason; /* 118: */ 258 259 u_int64_t pcs_reserved_soft; /* 120: preserved software */ 260 u_int64_t pcs_buffer[21]; /* 128: console buffers */ 261 262 #define PALvar_reserved 0 263 #define PALvar_OpenVMS 1 264 #define PALvar_OSF1 2 265 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 266 267 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 268 }; 269 270 /* 271 * CTB: Console Terminal Block 272 */ 273 struct ctb { 274 u_int64_t ctb_type; /* 0: always 4 */ 275 u_int64_t ctb_unit; /* 8: */ 276 u_int64_t ctb_reserved; /* 16: */ 277 u_int64_t ctb_len; /* 24: bytes of info */ 278 u_int64_t ctb_ipl; /* 32: console ipl level */ 279 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ 280 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ 281 282 #define CTB_GRAPHICS 3 /* graphics device */ 283 #define CTB_NETWORK 0xC0 /* network device */ 284 #define CTB_PRINTERPORT 2 /* printer port on the SCC */ 285 u_int64_t ctb_term_type; /* 56: terminal type */ 286 287 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ 288 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ 289 vm_offset_t ctb_keybd_map; /* 80: map table addr */ 290 u_int64_t ctb_keybd_state; /* 88: keyboard flags */ 291 u_int64_t ctb_keybd_last; /* 96: last key entered */ 292 vm_offset_t ctb_font_us; /* 104: US font table addr */ 293 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ 294 u_int64_t ctb_font_width; /* 120: font width, height */ 295 u_int64_t ctb_font_height; /* 128: in pixels */ 296 u_int64_t ctb_mon_width; /* 136: monitor width, height */ 297 u_int64_t ctb_mon_height; /* 144: in pixels */ 298 u_int64_t ctb_dpi; /* 152: monitor dots per inch */ 299 u_int64_t ctb_planes; /* 160: # of planes */ 300 u_int64_t ctb_cur_width; /* 168: cursor width, height */ 301 u_int64_t ctb_cur_height; /* 176: in pixels */ 302 u_int64_t ctb_head_cnt; /* 184: # of heads */ 303 u_int64_t ctb_opwindow; /* 192: opwindow on screen */ 304 vm_offset_t ctb_head_offset; /* 200: offset to head info */ 305 vm_offset_t ctb_putchar; /* 208: output char to TURBO */ 306 u_int64_t ctb_io_state; /* 216: I/O flags */ 307 u_int64_t ctb_listen_state; /* 224: listener flags */ 308 vm_offset_t ctb_xaddr; /* 232: extended info addr */ 309 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 310 u_int64_t ctb_server_off; /* 256: offset to server info */ 311 u_int64_t ctb_line_off; /* 264: line parameter offset */ 312 u_int8_t ctb_csd; /* 272: console specific data */ 313 }; 314 315 /* 316 * CRD: Console Routine Descriptor 317 */ 318 struct crd { 319 int64_t descriptor; 320 u_int64_t entry_va; 321 }; 322 323 /* 324 * CRB: Console Routine Block 325 */ 326 struct crb { 327 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 328 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ 329 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 330 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ 331 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ 332 u_int64_t crb_page_cnt; /* 28: pages to be mapped */ 333 }; 334 335 /* 336 * MDDT: Memory Data Descriptor Table 337 */ 338 struct mddt { 339 int64_t mddt_cksum; /* 0: 7-N checksum */ 340 vm_offset_t mddt_physaddr; /* 8: bank config addr 341 * IMPLEMENTATION SPECIFIC 342 */ 343 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ 344 struct { 345 vm_offset_t mddt_pfn; /* 0: starting PFN */ 346 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ 347 u_int64_t mddt_pg_test; /* 10: tested page count */ 348 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ 349 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ 350 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 351 352 #define MDDT_PALCODE 0x01 /* console and PAL only */ 353 #define MDDT_SYSTEM 0x00 /* system software only */ 354 #define MDDT_mbz 0xfffffffffffffffe /* 1:63 -- must be zero */ 355 int64_t mddt_usage; /* 30: bitmap permissions */ 356 } mddt_clusters[1]; /* variable length array */ 357 }; 358 #endif /* ASSEMBLER */ 359
Indexes created Wed Oct 01 15:09:59 GMT 2025