rpb.h revision 1.12.4.1
1 /* $NetBSD: rpb.h,v 1.12.4.1 1997/08/23 07:06:54 thorpej Exp $ */ 2 3 /* 4 * Copyright Notice: 5 * 6 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 7 * 8 * License: 9 * 10 * This License applies to this software ("Software"), created 11 * by Christopher G. Demetriou ("Author"). 12 * 13 * You may use, copy, modify and redistribute this Software without 14 * charge, in either source code form, binary form, or both, on the 15 * following conditions: 16 * 17 * 1. (a) Binary code: (i) a complete copy of the above copyright notice 18 * must be included within each copy of the Software in binary code form, 19 * and (ii) a complete copy of the above copyright notice and all terms 20 * of this License as presented here must be included within each copy of 21 * all documentation accompanying or associated with binary code, in any 22 * medium, along with a list of the software modules to which the license 23 * applies. 24 * 25 * (b) Source Code: A complete copy of the above copyright notice and all 26 * terms of this License as presented here must be included within: (i) 27 * each copy of the Software in source code form, and (ii) each copy of 28 * all accompanying or associated documentation, in any medium. 29 * 30 * 2. The following Acknowledgment must be used in communications 31 * involving the Software as described below: 32 * 33 * This product includes software developed by 34 * Christopher G. Demetriou for the NetBSD Project. 35 * 36 * The Acknowledgment must be conspicuously and completely displayed 37 * whenever the Software, or any software, products or systems containing 38 * the Software, are mentioned in advertising, marketing, informational 39 * or publicity materials of any kind, whether in print, electronic or 40 * other media (except for information provided to support use of 41 * products containing the Software by existing users or customers). 42 * 43 * 3. The name of the Author may not be used to endorse or promote 44 * products derived from this Software without specific prior written 45 * permission (conditions (1) and (2) above are not considered 46 * endorsement or promotion). 47 * 48 * 4. This license applies to: (a) all copies of the Software, whether 49 * partial or whole, original or modified, and (b) your actions, and the 50 * actions of all those who may act on your behalf. All uses not 51 * expressly permitted are reserved to the Author. 52 * 53 * 5. Disclaimer. THIS SOFTWARE IS MADE AVAILABLE BY THE AUTHOR TO THE 54 * PUBLIC FOR FREE AND "AS IS.'' ALL USERS OF THIS FREE SOFTWARE ARE 55 * SOLELY AND ENTIRELY RESPONSIBLE FOR THEIR OWN CHOICE AND USE OF THIS 56 * SOFTWARE FOR THEIR OWN PURPOSES. BY USING THIS SOFTWARE, EACH USER 57 * AGREES THAT THE AUTHOR SHALL NOT BE LIABLE FOR DAMAGES OF ANY KIND IN 58 * RELATION TO ITS USE OR PERFORMANCE. 59 * 60 * 6. If you have a special need for a change in one or more of these 61 * license conditions, please contact the Author via electronic mail to 62 * 63 * cgd (at) NetBSD.ORG 64 * 65 * or via the contact information on 66 * 67 * http://www.NetBSD.ORG/People/Pages/cgd.html 68 */ 69 70 /* 71 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 72 * All rights reserved. 73 * 74 * Author: Keith Bostic, Chris G. Demetriou 75 * 76 * Permission to use, copy, modify and distribute this software and 77 * its documentation is hereby granted, provided that both the copyright 78 * notice and this permission notice appear in all copies of the 79 * software, derivative works or modified versions, and any portions 80 * thereof, and that both notices appear in supporting documentation. 81 * 82 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 83 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 84 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 85 * 86 * Carnegie Mellon requests users of this software to return to 87 * 88 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 89 * School of Computer Science 90 * Carnegie Mellon University 91 * Pittsburgh PA 15213-3890 92 * 93 * any improvements or extensions that they make and grant Carnegie the 94 * rights to redistribute these changes. 95 */ 96 97 /* 98 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, 99 * EK-D3SYS-PM.B01. 100 */ 101 102 /* 103 * HWRPB (Hardware Restart Parameter Block). 104 */ 105 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 106 107 #ifndef ASSEMBLER 108 struct rpb { 109 struct restart_blk *rpb; /* 0: HWRPB phys. address. */ 110 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 111 u_int64_t rpb_version; /* 10 */ 112 u_int64_t rpb_size; /* 18: HWRPB size in bytes */ 113 u_int64_t rpb_primary_cpu_id; /* 20 */ 114 u_int64_t rpb_page_size; /* 28: (8192) */ 115 u_int64_t rpb_phys_addr_size; /* 30: (34) */ 116 u_int64_t rpb_max_asn; /* 38: (16) */ 117 char rpb_ssn[16]; /* 40: only first 10 valid */ 118 119 #define ST_ADU 1 /* Alpha Demo. Unit (?) */ 120 #define ST_DEC_4000 2 /* "Cobra" (?) */ 121 #define ST_DEC_7000 3 /* "Ruby" (?) */ 122 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ 123 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ 124 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ 125 #define ST_DEC_2100_A500 9 /* "Sable" (?) */ 126 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME?) */ 127 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ 128 #define ST_DEC_21000 12 /* "TurboLaser" (?) */ 129 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ 130 #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */ 131 #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ 132 #define ST_DEC_1000 17 /* "Mikasa" (PCI/ISA?) */ 133 #define ST_EB66 19 /* EB66 (PCI/ISA?) */ 134 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ 135 #define ST_ALPHABOOK1 21 /* AlphaBook (?) */ 136 #define ST_DEC_4100 22 /* "Rawhide" (?) */ 137 #define ST_DEC_EV45_PBP 23 /* "Lego" (?) */ 138 #define ST_DEC_2100A_A500 24 /* "Lynx" (?) */ 139 #define ST_EB164 26 /* EB164 (PCI/ISA) */ 140 #define ST_DEC_1000A 27 /* "Noritake" (?) */ 141 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" (?) */ 142 #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */ 143 #define ST_DEC_EV56_PBP 32 /* "Takara" (?) */ 144 #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (?) */ 145 146 u_int64_t rpb_type; /* 50: */ 147 148 #define SV_MPCAP 0x00000001 /* multiprocessor capable */ 149 150 #define SV_CONSOLE 0x0000001e /* console hardware mask */ 151 #define SV_CONSOLE_DETACHED 0x00000002 152 #define SV_CONSOLE_EMBEDDED 0x00000004 153 154 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ 155 #define SV_PF_UNITED 0x00000020 156 #define SV_PF_SEPARATE 0x00000040 157 #define SV_PF_BBACKUP 0x00000060 158 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ 159 160 #define SV_GRAPHICS 0x00000200 /* graphic engine present */ 161 162 #define SV_ST_MASK 0x0000fc00 /* system type mask */ 163 #define SV_ST_RESERVED 0x00000000 /* RESERVED */ 164 165 /* 166 * System types for the DEC 3000/500 (Flamingo) Family 167 */ 168 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ 169 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ 170 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ 171 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ 172 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ 173 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ 174 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ 175 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ 176 177 /* 178 * System types for ??? 179 */ 180 #define SV_ST_SABLE 0x00000400 /* Sable (???) */ 181 182 /* 183 * System types for the DEC 3000/300 (Pelican) Family 184 */ 185 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ 186 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ 187 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ 188 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ 189 190 /* 191 * System types for the AlphaStation Family 192 */ 193 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ 194 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ 195 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ 196 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ 197 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ 198 199 u_int64_t rpb_variation; /* 58 */ 200 201 char rpb_revision[8]; /* 60; only first 4 valid */ 202 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ 203 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 204 vm_offset_t rpb_vptb; /* 78: */ 205 u_int64_t rpb_reserved_arch; /* 80: */ 206 vm_offset_t rpb_tbhint_off; /* 88: */ 207 u_int64_t rpb_pcs_cnt; /* 90: */ 208 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ 209 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ 210 u_int64_t rpb_ctb_cnt; /* A8: console terminal */ 211 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ 212 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ 213 vm_offset_t rpb_crb_off; /* C0: offset to crb */ 214 vm_offset_t rpb_memdat_off; /* C8: memory data offset */ 215 vm_offset_t rpb_condat_off; /* D0: config data offset */ 216 vm_offset_t rpb_fru_off; /* D8: FRU table offset */ 217 u_int64_t rpb_save_term; /* E0: terminal save */ 218 u_int64_t rpb_save_term_val; /* E8: */ 219 u_int64_t rpb_rest_term; /* F0: terminal restore */ 220 u_int64_t rpb_rest_term_val; /* F8: */ 221 u_int64_t rpb_restart; /* 100: restart */ 222 u_int64_t rpb_restart_val; /* 108: */ 223 u_int64_t rpb_reserve_os; /* 110: */ 224 u_int64_t rpb_reserve_hw; /* 118: */ 225 u_int64_t rpb_checksum; /* 120: HWRPB checksum */ 226 u_int64_t rpb_rxrdy; /* 128: receive ready */ 227 u_int64_t rpb_txrdy; /* 130: transmit ready */ 228 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 229 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ 230 }; 231 232 /* 233 * PCS: Per-CPU information. 234 */ 235 struct pcs { 236 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 237 238 #define PCS_BIP 0x000001 /* boot in progress */ 239 #define PCS_RC 0x000002 /* restart possible */ 240 #define PCS_PA 0x000004 /* processor available */ 241 #define PCS_PP 0x000008 /* processor present */ 242 #define PCS_OH 0x000010 /* user halted */ 243 #define PCS_CV 0x000020 /* context valid */ 244 #define PCS_PV 0x000040 /* PALcode valid */ 245 #define PCS_PMV 0x000080 /* PALcode memory valid */ 246 #define PCS_PL 0x000100 /* PALcode loaded */ 247 248 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 249 #define PCS_HALT_DEFAULT 0x000000 250 #define PCS_HALT_SAVE_EXIT 0x010000 251 #define PCS_HALT_COLD_BOOT 0x020000 252 #define PCS_HALT_WARM_BOOT 0x030000 253 #define PCS_HALT_STAY_HALTED 0x040000 254 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 255 u_int64_t pcs_flags; /* 80: */ 256 257 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ 258 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 259 vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ 260 vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ 261 struct { 262 u_int64_t 263 pcs_alpha : 8, /* alphabetic char 'a' - 'z' */ 264 #define PAL_TYPE_STANDARD 0 265 #define PAL_TYPE_VMS 1 266 #define PAL_TYPE_OSF1 2 267 pcs_pal_type : 8, /* PALcode type: 268 * 0 == standard 269 * 1 == OpenVMS 270 * 2 == OSF/1 271 * 3-127 DIGITAL reserv. 272 * 128-255 non-DIGITAL reserv. 273 */ 274 sbz1 : 16, 275 pcs_proc_cnt : 7, /* Processor count */ 276 sbz2 : 25; 277 } pcs_pal_rev; /* A8: */ 278 #define pcs_alpha pcs_pal_rev.alpha 279 #define pcs_pal_type pcs_pal_rev.pal_type 280 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 281 282 u_int64_t pcs_proc_type; /* B0: processor type */ 283 284 #define PCS_PROC_MAJOR 0x00000000ffffffff 285 #define PCS_PROC_MAJORSHIFT 0 286 287 #define PCS_PROC_EV3 1 /* EV3 */ 288 #define PCS_PROC_EV4 2 /* EV4: 21064 */ 289 #define PCS_PROC_SIMULATION 3 /* Simulation */ 290 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ 291 #define PCS_PROC_EV5 5 /* EV5: 21164 */ 292 #define PCS_PROC_EV45 6 /* EV45: 21064A */ 293 #define PCS_PROC_EV56 7 /* EV56: 21164A */ 294 #define PCS_PROC_EV6 8 /* EV6: 21264 */ 295 #define PCS_PROC_PCA56 9 /* PCA256: 21164PC */ 296 297 #define PCS_PROC_MINOR 0xffffffff00000000 298 #define PCS_PROC_MINORSHIFT 32 299 300 /* Minor number interpretation is processor specific. See cpu.c. */ 301 302 u_int64_t pcs_proc_var; /* B8: processor variation. */ 303 304 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ 305 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ 306 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ 307 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ 308 309 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 310 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 311 vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ 312 u_int64_t pcs_machcheck_len; /* E0: length in bytes */ 313 vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 314 vm_offset_t pcs_halt_pc; /* F0: halt PC */ 315 u_int64_t pcs_halt_ps; /* F8: halt PS */ 316 u_int64_t pcs_halt_r25; /* 100: halt argument list */ 317 u_int64_t pcs_halt_r26; /* 108: halt return addr list */ 318 u_int64_t pcs_halt_r27; /* 110: halt procedure value */ 319 320 #define PCS_HALT_RESERVED 0 321 #define PCS_HALT_POWERUP 1 322 #define PCS_HALT_CONSOLE_HALT 2 323 #define PCS_HALT_CONSOLE_CRASH 3 324 #define PCS_HALT_KERNEL_MODE 4 325 #define PCS_HALT_KERNEL_STACK_INVALID 5 326 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 327 #define PCS_HALT_SCBB 7 328 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 329 u_int64_t pcs_halt_reason; /* 118: */ 330 331 u_int64_t pcs_reserved_soft; /* 120: preserved software */ 332 u_int64_t pcs_buffer[21]; /* 128: console buffers */ 333 334 #define PALvar_reserved 0 335 #define PALvar_OpenVMS 1 336 #define PALvar_OSF1 2 337 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 338 339 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 340 }; 341 342 /* 343 * CTB: Console Terminal Block 344 */ 345 struct ctb { 346 u_int64_t ctb_type; /* 0: always 4 */ 347 u_int64_t ctb_unit; /* 8: */ 348 u_int64_t ctb_reserved; /* 16: */ 349 u_int64_t ctb_len; /* 24: bytes of info */ 350 u_int64_t ctb_ipl; /* 32: console ipl level */ 351 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ 352 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ 353 354 #define CTB_GRAPHICS 3 /* graphics device */ 355 #define CTB_NETWORK 0xC0 /* network device */ 356 #define CTB_PRINTERPORT 2 /* printer port on the SCC */ 357 u_int64_t ctb_term_type; /* 56: terminal type */ 358 359 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ 360 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ 361 vm_offset_t ctb_keybd_map; /* 80: map table addr */ 362 u_int64_t ctb_keybd_state; /* 88: keyboard flags */ 363 u_int64_t ctb_keybd_last; /* 96: last key entered */ 364 vm_offset_t ctb_font_us; /* 104: US font table addr */ 365 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ 366 u_int64_t ctb_font_width; /* 120: font width, height */ 367 u_int64_t ctb_font_height; /* 128: in pixels */ 368 u_int64_t ctb_mon_width; /* 136: monitor width, height */ 369 u_int64_t ctb_mon_height; /* 144: in pixels */ 370 u_int64_t ctb_dpi; /* 152: monitor dots per inch */ 371 u_int64_t ctb_planes; /* 160: # of planes */ 372 u_int64_t ctb_cur_width; /* 168: cursor width, height */ 373 u_int64_t ctb_cur_height; /* 176: in pixels */ 374 u_int64_t ctb_head_cnt; /* 184: # of heads */ 375 u_int64_t ctb_opwindow; /* 192: opwindow on screen */ 376 vm_offset_t ctb_head_offset; /* 200: offset to head info */ 377 vm_offset_t ctb_putchar; /* 208: output char to TURBO */ 378 u_int64_t ctb_io_state; /* 216: I/O flags */ 379 u_int64_t ctb_listen_state; /* 224: listener flags */ 380 vm_offset_t ctb_xaddr; /* 232: extended info addr */ 381 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 382 u_int64_t ctb_server_off; /* 256: offset to server info */ 383 u_int64_t ctb_line_off; /* 264: line parameter offset */ 384 u_int8_t ctb_csd; /* 272: console specific data */ 385 }; 386 387 /* 388 * CRD: Console Routine Descriptor 389 */ 390 struct crd { 391 int64_t descriptor; 392 u_int64_t entry_va; 393 }; 394 395 /* 396 * CRB: Console Routine Block 397 */ 398 struct crb { 399 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 400 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ 401 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 402 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ 403 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ 404 u_int64_t crb_page_cnt; /* 28: pages to be mapped */ 405 }; 406 407 /* 408 * MDDT: Memory Data Descriptor Table 409 */ 410 struct mddt { 411 int64_t mddt_cksum; /* 0: 7-N checksum */ 412 vm_offset_t mddt_physaddr; /* 8: bank config addr 413 * IMPLEMENTATION SPECIFIC 414 */ 415 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ 416 struct { 417 vm_offset_t mddt_pfn; /* 0: starting PFN */ 418 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ 419 u_int64_t mddt_pg_test; /* 10: tested page count */ 420 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ 421 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ 422 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 423 424 #define MDDT_PALCODE 0x01 /* console and PAL only */ 425 #define MDDT_SYSTEM 0x00 /* system software only */ 426 #define MDDT_mbz 0xfffffffffffffffe /* 1:63 -- must be zero */ 427 int64_t mddt_usage; /* 30: bitmap permissions */ 428 } mddt_clusters[1]; /* variable length array */ 429 }; 430 #endif /* ASSEMBLER */ 431
Indexes created Tue Oct 28 12:10:06 GMT 2025