rpb.h revision 1.22
1 /* $NetBSD: rpb.h,v 1.22 1998/06/03 23:07:38 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, 32 * EK-D3SYS-PM.B01. 33 */ 34 35 /* 36 * HWRPB (Hardware Restart Parameter Block). 37 */ 38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 39 40 #ifndef ASSEMBLER 41 struct rpb { 42 u_int64_t rpb_phys; /* 0: HWRPB phys. address. */ 43 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 44 u_int64_t rpb_version; /* 10 */ 45 u_int64_t rpb_size; /* 18: HWRPB size in bytes */ 46 u_int64_t rpb_primary_cpu_id; /* 20 */ 47 u_int64_t rpb_page_size; /* 28: (8192) */ 48 u_int64_t rpb_phys_addr_size; /* 30: (34) */ 49 u_int64_t rpb_max_asn; /* 38: (16) */ 50 char rpb_ssn[16]; /* 40: only first 10 valid */ 51 52 #define ST_ADU 1 /* Alpha Demo. Unit (?) */ 53 #define ST_DEC_4000 2 /* "Cobra" (?) */ 54 #define ST_DEC_7000 3 /* "Ruby" (?) */ 55 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ 56 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ 57 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ 58 #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */ 59 #define ST_DEC_2100_A500 9 /* "Sable" (?) */ 60 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME?) */ 61 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ 62 #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */ 63 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ 64 #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */ 65 #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ 66 #define ST_DEC_1000 17 /* "Mikasa" (PCI/ISA?) */ 67 #define ST_EB66 19 /* EB66 (PCI/ISA?) */ 68 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ 69 #define ST_ALPHABOOK1 21 /* Alphabook (?) */ 70 #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */ 71 #define ST_DEC_EV45_PBP 23 /* "Lego" (?) */ 72 #define ST_DEC_2100A_A500 24 /* "Lynx" (?) */ 73 #define ST_EB164 26 /* EB164 (PCI/ISA) */ 74 #define ST_DEC_1000A 27 /* "Noritake" (?) */ 75 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" (?) */ 76 #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */ 77 #define ST_DEC_EV56_PBP 32 /* "Takara" (?) */ 78 #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME?) */ 79 80 u_int64_t rpb_type; /* 50: */ 81 82 #define SV_MPCAP 0x00000001 /* multiprocessor capable */ 83 84 #define SV_CONSOLE 0x0000001e /* console hardware mask */ 85 #define SV_CONSOLE_DETACHED 0x00000002 86 #define SV_CONSOLE_EMBEDDED 0x00000004 87 88 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ 89 #define SV_PF_UNITED 0x00000020 90 #define SV_PF_SEPARATE 0x00000040 91 #define SV_PF_BBACKUP 0x00000060 92 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ 93 94 #define SV_GRAPHICS 0x00000200 /* graphic engine present */ 95 96 #define SV_ST_MASK 0x0000fc00 /* system type mask */ 97 #define SV_ST_RESERVED 0x00000000 /* RESERVED */ 98 99 /* 100 * System types for the DEC 3000/500 (Flamingo) Family 101 */ 102 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ 103 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ 104 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ 105 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ 106 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ 107 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ 108 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ 109 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ 110 111 /* 112 * System types for ??? 113 */ 114 #define SV_ST_SABLE 0x00000400 /* Sable (???) */ 115 116 /* 117 * System types for the DEC 3000/300 (Pelican) Family 118 */ 119 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ 120 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ 121 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ 122 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ 123 124 /* 125 * System types for the AlphaStation Family 126 */ 127 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ 128 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ 129 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ 130 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ 131 #define SV_ST_AVANTI_4_266 0x00002000 132 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ 133 #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */ 134 135 #define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */ 136 137 /* 138 * System types for the AXPvme Family 139 */ 140 #define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */ 141 #define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */ 142 #define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */ 143 #define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */ 144 #define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */ 145 #define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */ 146 #define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */ 147 148 /* 149 * System types for the EB164 Family 150 */ 151 #define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */ 152 #define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */ 153 #define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */ 154 #define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */ 155 #define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */ 156 #define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */ 157 #define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */ 158 #define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */ 159 #define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */ 160 #define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */ 161 #define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */ 162 #define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */ 163 #define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */ 164 #define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */ 165 #define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */ 166 167 u_int64_t rpb_variation; /* 58 */ 168 169 char rpb_revision[8]; /* 60; only first 4 valid */ 170 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ 171 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 172 vm_offset_t rpb_vptb; /* 78: */ 173 u_int64_t rpb_reserved_arch; /* 80: */ 174 vm_offset_t rpb_tbhint_off; /* 88: */ 175 u_int64_t rpb_pcs_cnt; /* 90: */ 176 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ 177 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ 178 u_int64_t rpb_ctb_cnt; /* A8: console terminal */ 179 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ 180 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ 181 vm_offset_t rpb_crb_off; /* C0: offset to crb */ 182 vm_offset_t rpb_memdat_off; /* C8: memory data offset */ 183 vm_offset_t rpb_condat_off; /* D0: config data offset */ 184 vm_offset_t rpb_fru_off; /* D8: FRU table offset */ 185 u_int64_t rpb_save_term; /* E0: terminal save */ 186 u_int64_t rpb_save_term_val; /* E8: */ 187 u_int64_t rpb_rest_term; /* F0: terminal restore */ 188 u_int64_t rpb_rest_term_val; /* F8: */ 189 u_int64_t rpb_restart; /* 100: restart */ 190 u_int64_t rpb_restart_val; /* 108: */ 191 u_int64_t rpb_reserve_os; /* 110: */ 192 u_int64_t rpb_reserve_hw; /* 118: */ 193 u_int64_t rpb_checksum; /* 120: HWRPB checksum */ 194 u_int64_t rpb_rxrdy; /* 128: receive ready */ 195 u_int64_t rpb_txrdy; /* 130: transmit ready */ 196 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 197 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ 198 }; 199 200 /* 201 * PCS: Per-CPU information. 202 */ 203 struct pcs { 204 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 205 206 #define PCS_BIP 0x000001 /* boot in progress */ 207 #define PCS_RC 0x000002 /* restart possible */ 208 #define PCS_PA 0x000004 /* processor available */ 209 #define PCS_PP 0x000008 /* processor present */ 210 #define PCS_OH 0x000010 /* user halted */ 211 #define PCS_CV 0x000020 /* context valid */ 212 #define PCS_PV 0x000040 /* PALcode valid */ 213 #define PCS_PMV 0x000080 /* PALcode memory valid */ 214 #define PCS_PL 0x000100 /* PALcode loaded */ 215 216 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 217 #define PCS_HALT_DEFAULT 0x000000 218 #define PCS_HALT_SAVE_EXIT 0x010000 219 #define PCS_HALT_COLD_BOOT 0x020000 220 #define PCS_HALT_WARM_BOOT 0x030000 221 #define PCS_HALT_STAY_HALTED 0x040000 222 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 223 u_int64_t pcs_flags; /* 80: */ 224 225 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ 226 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 227 vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ 228 vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ 229 struct { 230 u_int64_t 231 minorrev : 8, /* alphabetic char 'a' - 'z' */ 232 majorrev : 8, /* alphabetic char 'a' - 'z' */ 233 #define PAL_TYPE_STANDARD 0 234 #define PAL_TYPE_VMS 1 235 #define PAL_TYPE_OSF1 2 236 pal_type : 8, /* PALcode type: 237 * 0 == standard 238 * 1 == OpenVMS 239 * 2 == OSF/1 240 * 3-127 DIGITAL reserv. 241 * 128-255 non-DIGITAL reserv. 242 */ 243 sbz1 : 8, 244 compatibility : 16, /* Compatibility revision */ 245 proc_cnt : 16; /* Processor count */ 246 } pcs_pal_rev; /* A8: */ 247 #define pcs_minorrev pcs_pal_rev.minorrev 248 #define pcs_majorrev pcs_pal_rev.majorrev 249 #define pcs_pal_type pcs_pal_rev.pal_type 250 #define pcs_compatibility pcs_pal_rev.compatibility 251 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 252 253 u_int64_t pcs_proc_type; /* B0: processor type */ 254 255 #define PCS_PROC_MAJOR 0x00000000ffffffff 256 #define PCS_PROC_MAJORSHIFT 0 257 258 #define PCS_PROC_EV3 1 /* EV3 */ 259 #define PCS_PROC_EV4 2 /* EV4: 21064 */ 260 #define PCS_PROC_SIMULATION 3 /* Simulation */ 261 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ 262 #define PCS_PROC_EV5 5 /* EV5: 21164 */ 263 #define PCS_PROC_EV45 6 /* EV45: 21064A */ 264 #define PCS_PROC_EV56 7 /* EV56: 21164A */ 265 #define PCS_PROC_EV6 8 /* EV6: 21264 */ 266 #define PCS_PROC_PCA56 9 /* PCA256: 21164PC */ 267 268 #define PCS_PROC_MINOR 0xffffffff00000000 269 #define PCS_PROC_MINORSHIFT 32 270 271 /* Minor number interpretation is processor specific. See cpu.c. */ 272 273 u_int64_t pcs_proc_var; /* B8: processor variation. */ 274 275 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ 276 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ 277 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ 278 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ 279 280 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 281 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 282 vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ 283 u_int64_t pcs_machcheck_len; /* E0: length in bytes */ 284 vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 285 vm_offset_t pcs_halt_pc; /* F0: halt PC */ 286 u_int64_t pcs_halt_ps; /* F8: halt PS */ 287 u_int64_t pcs_halt_r25; /* 100: halt argument list */ 288 u_int64_t pcs_halt_r26; /* 108: halt return addr list */ 289 u_int64_t pcs_halt_r27; /* 110: halt procedure value */ 290 291 #define PCS_HALT_RESERVED 0 292 #define PCS_HALT_POWERUP 1 293 #define PCS_HALT_CONSOLE_HALT 2 294 #define PCS_HALT_CONSOLE_CRASH 3 295 #define PCS_HALT_KERNEL_MODE 4 296 #define PCS_HALT_KERNEL_STACK_INVALID 5 297 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 298 #define PCS_HALT_SCBB 7 299 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 300 u_int64_t pcs_halt_reason; /* 118: */ 301 302 u_int64_t pcs_reserved_soft; /* 120: preserved software */ 303 u_int64_t pcs_buffer[21]; /* 128: console buffers */ 304 305 #define PALvar_reserved 0 306 #define PALvar_OpenVMS 1 307 #define PALvar_OSF1 2 308 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 309 310 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 311 }; 312 313 /* 314 * CTB: Console Terminal Block 315 */ 316 struct ctb { 317 u_int64_t ctb_type; /* 0: always 4 */ 318 u_int64_t ctb_unit; /* 8: */ 319 u_int64_t ctb_reserved; /* 16: */ 320 u_int64_t ctb_len; /* 24: bytes of info */ 321 u_int64_t ctb_ipl; /* 32: console ipl level */ 322 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ 323 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ 324 325 #define CTB_GRAPHICS 3 /* graphics device */ 326 #define CTB_NETWORK 0xC0 /* network device */ 327 #define CTB_PRINTERPORT 2 /* printer port on the SCC */ 328 u_int64_t ctb_term_type; /* 56: terminal type */ 329 330 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ 331 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ 332 vm_offset_t ctb_keybd_map; /* 80: map table addr */ 333 u_int64_t ctb_keybd_state; /* 88: keyboard flags */ 334 u_int64_t ctb_keybd_last; /* 96: last key entered */ 335 vm_offset_t ctb_font_us; /* 104: US font table addr */ 336 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ 337 u_int64_t ctb_font_width; /* 120: font width, height */ 338 u_int64_t ctb_font_height; /* 128: in pixels */ 339 u_int64_t ctb_mon_width; /* 136: monitor width, height */ 340 u_int64_t ctb_mon_height; /* 144: in pixels */ 341 u_int64_t ctb_dpi; /* 152: monitor dots per inch */ 342 u_int64_t ctb_planes; /* 160: # of planes */ 343 u_int64_t ctb_cur_width; /* 168: cursor width, height */ 344 u_int64_t ctb_cur_height; /* 176: in pixels */ 345 u_int64_t ctb_head_cnt; /* 184: # of heads */ 346 u_int64_t ctb_opwindow; /* 192: opwindow on screen */ 347 vm_offset_t ctb_head_offset; /* 200: offset to head info */ 348 vm_offset_t ctb_putchar; /* 208: output char to TURBO */ 349 u_int64_t ctb_io_state; /* 216: I/O flags */ 350 u_int64_t ctb_listen_state; /* 224: listener flags */ 351 vm_offset_t ctb_xaddr; /* 232: extended info addr */ 352 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 353 u_int64_t ctb_server_off; /* 256: offset to server info */ 354 u_int64_t ctb_line_off; /* 264: line parameter offset */ 355 u_int8_t ctb_csd; /* 272: console specific data */ 356 }; 357 358 /* 359 * CRD: Console Routine Descriptor 360 */ 361 struct crd { 362 int64_t descriptor; 363 u_int64_t entry_va; 364 }; 365 366 /* 367 * CRB: Console Routine Block 368 */ 369 struct crb { 370 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 371 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ 372 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 373 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ 374 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ 375 u_int64_t crb_page_cnt; /* 28: pages to be mapped */ 376 }; 377 378 /* 379 * MDDT: Memory Data Descriptor Table 380 */ 381 struct mddt { 382 int64_t mddt_cksum; /* 0: 7-N checksum */ 383 vm_offset_t mddt_physaddr; /* 8: bank config addr 384 * IMPLEMENTATION SPECIFIC 385 */ 386 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ 387 struct mddt_cluster { 388 vm_offset_t mddt_pfn; /* 0: starting PFN */ 389 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ 390 u_int64_t mddt_pg_test; /* 10: tested page count */ 391 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ 392 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ 393 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 394 395 #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */ 396 #define MDDT_PALCODE 0x01 /* console and PAL only */ 397 #define MDDT_SYSTEM 0x00 /* system software only */ 398 #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */ 399 int64_t mddt_usage; /* 30: bitmap permissions */ 400 } mddt_clusters[1]; /* variable length array */ 401 }; 402 403 /* 404 * DSR: Dynamic System Recognition. We're interested in the sysname 405 * offset. The data pointed to by sysname is: 406 * 407 * [8 bytes: length of system name][N bytes: system name string] 408 * 409 * The system name string is NUL-terminated. 410 */ 411 struct dsrdb { 412 int64_t dsr_smm; /* 0: SMM number */ 413 u_int64_t dsr_lurt_off; /* 8: LURT table offset */ 414 u_int64_t dsr_sysname_off; /* 16: offset to sysname */ 415 }; 416 417 /* 418 * The DSR appeared in version 5 of the HWRPB. 419 */ 420 #define HWRPB_DSRDB_MINVERS 5 421 422 #ifdef _KERNEL 423 int cputype; 424 #endif 425 426 #endif /* ASSEMBLER */ 427
Indexes created Wed Oct 01 15:09:59 GMT 2025