rpb.h revision 1.3
1 /* $NetBSD: rpb.h,v 1.3 1995/03/24 15:00:51 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, 32 * EK-D3SYS-PM.B01. 33 */ 34 35 /* 36 * HWRPB (Hardware Restart Parameter Block). 37 */ 38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 39 40 #ifndef ASSEMBLER 41 struct rpb { 42 struct restart_blk *rpb; /* 0: HWRPB phys. address. */ 43 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 44 u_int64_t rpb_version; /* 10 */ 45 u_int64_t rpb_size; /* 18: HWRPB size in bytes */ 46 u_int64_t rpb_primary_cpu_id; /* 20 */ 47 u_int64_t rpb_page_size; /* 28: (8192) */ 48 u_int64_t rpb_phys_addr_size; /* 30: (34) */ 49 u_int64_t rpb_max_asn; /* 38: (16) */ 50 char rpb_ssn[16]; /* 40: only first 10 valid */ 51 52 #define ST_ADU 1 /* Alpha Demo. Unit (?) */ 53 #define ST_DEC_4000 2 /* "Cobra" (?) */ 54 #define ST_DEC_7000 3 /* "Ruby" (?) */ 55 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ 56 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ 57 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ 58 #define ST_DEC_2100_A500 9 /* "Sable" (?) */ 59 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME?) */ 60 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA?) */ 61 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ 62 #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */ 63 #define ST_DEC_1000 17 /* "Mikasa" (PCI/ISA?) */ 64 65 u_int64_t rpb_type; /* 50: */ 66 67 #define SV_MPCAP 0x00000001 /* multiprocessor capable */ 68 69 #define SV_CONSOLE 0x0000001e /* console hardware mask */ 70 #define SV_CONSOLE_DETACHED 0x00000002 71 #define SV_CONSOLE_EMBEDDED 0x00000004 72 73 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ 74 #define SV_PF_UNITED 0x00000020 75 #define SV_PF_SEPARATE 0x00000040 76 #define SV_PF_BBACKUP 0x00000060 77 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ 78 79 #define SV_GRAPHICS 0x00000200 /* graphic engine present */ 80 81 #define SV_ST_MASK 0x0000fc00 /* system type mask */ 82 #define SV_ST_RESERVED 0x00000000 /* RESERVED */ 83 84 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ 85 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ 86 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ 87 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ 88 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ 89 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ 90 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ 91 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ 92 93 #define SV_ST_SABLE 0x00000400 /* Sable (???) */ 94 95 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ 96 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ 97 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ 98 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ 99 100 u_int64_t rpb_variation; /* 58 */ 101 102 char rpb_revision[8]; /* 60; only first 4 valid */ 103 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ 104 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 105 vm_offset_t rpb_vptb; /* 78: */ 106 u_int64_t rpb_reserved_arch; /* 80: */ 107 vm_offset_t rpb_tbhint_off; /* 88: */ 108 u_int64_t rpb_pcs_cnt; /* 90: */ 109 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ 110 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ 111 u_int64_t rpb_ctb_cnt; /* A8: console terminal */ 112 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ 113 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ 114 vm_offset_t rpb_crb_off; /* C0: offset to crb */ 115 vm_offset_t rpb_memdat_off; /* C8: memory data offset */ 116 vm_offset_t rpb_condat_off; /* D0: config data offset */ 117 vm_offset_t rpb_fru_off; /* D8: FRU table offset */ 118 long (*rpb_save_term)(); /* E0: terminal save */ 119 long rpb_save_term_val; /* E8: */ 120 long (*rpb_rest_term)(); /* F0: terminal restore */ 121 long rpb_rest_term_val; /* F8: */ 122 long (*rpb_restart)(); /* 100: restart */ 123 long rpb_restart_val; /* 108: */ 124 u_int64_t rpb_reserve_os; /* 110: */ 125 u_int64_t rpb_reserve_hw; /* 118: */ 126 u_int64_t rpb_checksum; /* 120: HWRPB checksum */ 127 u_int64_t rpb_rxrdy; /* 128: receive ready */ 128 u_int64_t rpb_txrdy; /* 130: transmit ready */ 129 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 130 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ 131 }; 132 133 #ifdef KERNEL 134 extern struct rpb *hwrpb; 135 #endif 136 137 /* 138 * PCS: Per-CPU information. 139 */ 140 struct pcs { 141 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 142 143 #define PCS_BIP 0x000001 /* boot in progress */ 144 #define PCS_RIP 0x000002 /* restart in progress */ 145 #define PCS_PA 0x000004 /* processor available */ 146 #define PCS_PP 0x000008 /* processor present */ 147 #define PCS_OH 0x000010 /* user halted */ 148 #define PCS_CV 0x000020 /* context valid */ 149 #define PCS_PV 0x000040 /* PALcode valid */ 150 #define PCS_PMV 0x000080 /* PALcode memory valid */ 151 #define PCS_PL 0x000100 /* PALcode loaded */ 152 #define PCS_PE 0x000200 /* primary eligible (SMP) */ 153 154 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 155 #define PCS_HALT_DEFAULT 0x000000 156 #define PCS_HALT_SAVE_EXIT 0x010000 157 #define PCS_HALT_COLD_BOOT 0x020000 158 #define PCS_HALT_WARM_BOOT 0x030000 159 #define PCS_HALT_STAY_HALTED 0x040000 160 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 161 u_int64_t pcs_flags; /* 80: */ 162 163 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ 164 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 165 vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ 166 vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ 167 struct { 168 u_int64_t 169 pcs_alpha : 8, /* alphabetic char 'a' - 'z' */ 170 #define PAL_TYPE_STANDARD 0 171 #define PAL_TYPE_VMS 1 172 #define PAL_TYPE_OSF1 2 173 pcs_pal_type : 8, /* PALcode type: 174 * 0 == standard 175 * 1 == OpenVMS 176 * 2 == OSF/1 177 * 3-127 DIGITAL reserv. 178 * 128-255 non-DIGITAL reserv. 179 */ 180 sbz1 : 16, 181 pcs_proc_cnt : 7, /* Processor count */ 182 sbz2 : 25; 183 } pcs_pal_rev; /* A8: */ 184 #define pcs_alpha pcs_pal_rev.alpha 185 #define pcs_pal_type pcs_pal_rev.pal_type 186 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 187 188 u_int64_t pcs_proc_type; /* B0: processor type */ 189 190 #define PCS_PROC_MAJOR 0x00000000ffffffff 191 #define PCS_PROC_MAJORSHIFT 0 192 #define PCS_PROC_EV3 1 /* EV3 */ 193 #define PCS_PROC_EV4 2 /* EV4: 21064 */ 194 #define PCS_PROC_SIMULATOR 3 /* simulation */ 195 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ 196 #define PCS_PROC_EV45 6 /* EV45: 21064A */ 197 #ifdef XXX_UNKNOWN 198 #define PCS_PROC_EV5 ??? /* EV5: 21164 */ 199 #endif 200 201 #define PCS_PROC_MINOR 0xffffffff00000000 202 #define PCS_PROC_MINORSHIFT 32 203 #define PCS_PROC_PASS2 0 /* pass 2 or 2.1 */ 204 #define PCS_PROC_PASS3 1 /* pass 3 */ 205 206 u_int64_t pcs_proc_var; /* B8: processor variation. */ 207 208 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ 209 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ 210 #define PCS_VAR_RESERVED 0xfffffffffffffffc /* Reserved */ 211 212 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 213 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 214 vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ 215 u_int64_t pcs_machcheck_len; /* E0: length in bytes */ 216 vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 217 vm_offset_t pcs_halt_pc; /* F0: halt PC */ 218 u_int64_t pcs_halt_ps; /* F8: halt PS */ 219 u_int64_t pcs_halt_r25; /* 100: halt argument list */ 220 u_int64_t pcs_halt_r26; /* 108: halt return addr list */ 221 u_int64_t pcs_halt_r27; /* 110: halt procedure value */ 222 223 #define PCS_HALT_RESERVED 0 224 #define PCS_HALT_POWERUP 1 225 #define PCS_HALT_CONSOLE_HALT 2 226 #define PCS_HALT_CONSOLE_CRASH 3 227 #define PCS_HALT_KERNEL_MODE 4 228 #define PCS_HALT_KERNEL_STACK_INVALID 5 229 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 230 #define PCS_HALT_SCBB 7 231 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 232 u_int64_t pcs_halt_reason; /* 118: */ 233 234 u_int64_t pcs_reserved_soft; /* 120: preserved software */ 235 u_int64_t pcs_buffer[21]; /* 128: console buffers */ 236 237 #define PALvar_reserved 0 238 #define PALvar_OpenVMS 1 239 #define PALvar_OSF1 2 240 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 241 242 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 243 }; 244 245 /* 246 * CTB: Console Terminal Block 247 */ 248 struct ctb { 249 u_int64_t ctb_type; /* 0: always 4 */ 250 u_int64_t ctb_unit; /* 8: */ 251 u_int64_t ctb_reserved; /* 16: */ 252 u_int64_t ctb_len; /* 24: bytes of info */ 253 u_int64_t ctb_ipl; /* 32: console ipl level */ 254 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ 255 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ 256 257 #define CTB_GRAPHICS 3 /* graphics device */ 258 #define CTB_NETWORK 0xC0 /* network device */ 259 #define CTB_PRINTERPORT 2 /* printer port on the SCC */ 260 u_int64_t ctb_term_type; /* 56: terminal type */ 261 262 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ 263 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ 264 vm_offset_t ctb_keybd_map; /* 80: map table addr */ 265 u_int64_t ctb_keybd_state; /* 88: keyboard flags */ 266 u_int64_t ctb_keybd_last; /* 96: last key entered */ 267 vm_offset_t ctb_font_us; /* 104: US font table addr */ 268 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ 269 u_int64_t ctb_font_width; /* 120: font width, height */ 270 u_int64_t ctb_font_height; /* 128: in pixels */ 271 u_int64_t ctb_mon_width; /* 136: monitor width, height */ 272 u_int64_t ctb_mon_height; /* 144: in pixels */ 273 u_int64_t ctb_dpi; /* 152: monitor dots per inch */ 274 u_int64_t ctb_planes; /* 160: # of planes */ 275 u_int64_t ctb_cur_width; /* 168: cursor width, height */ 276 u_int64_t ctb_cur_height; /* 176: in pixels */ 277 u_int64_t ctb_head_cnt; /* 184: # of heads */ 278 u_int64_t ctb_opwindow; /* 192: opwindow on screen */ 279 vm_offset_t ctb_head_offset; /* 200: offset to head info */ 280 vm_offset_t ctb_putchar; /* 208: output char to TURBO */ 281 u_int64_t ctb_io_state; /* 216: I/O flags */ 282 u_int64_t ctb_listen_state; /* 224: listener flags */ 283 vm_offset_t ctb_xaddr; /* 232: extended info addr */ 284 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 285 u_int64_t ctb_server_off; /* 256: offset to server info */ 286 u_int64_t ctb_line_off; /* 264: line parameter offset */ 287 u_int8_t ctb_csd; /* 272: console specific data */ 288 }; 289 290 /* 291 * CRD: Console Routine Descriptor 292 */ 293 struct crd { 294 int64_t descriptor; 295 int (*code)(); 296 }; 297 298 /* 299 * CRB: Console Routine Block 300 */ 301 struct crb { 302 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 303 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ 304 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 305 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ 306 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ 307 u_int64_t crb_page_cnt; /* 28: pages to be mapped */ 308 }; 309 310 /* 311 * MDDT: Memory Data Descriptor Table 312 */ 313 struct mddt { 314 int64_t mddt_cksum; /* 0: 7-N checksum */ 315 vm_offset_t mddt_physaddr; /* 8: bank config addr 316 * IMPLEMENTATION SPECIFIC 317 */ 318 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ 319 struct { 320 vm_offset_t mddt_pfn; /* 0: starting PFN */ 321 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ 322 u_int64_t mddt_pg_test; /* 10: tested page count */ 323 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ 324 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ 325 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 326 327 #define MDDT_PALCODE 0x01 /* console and PAL only */ 328 #define MDDT_SYSTEM 0x00 /* system software only */ 329 #define MDDT_mbz 0xfffffffffffffffe /* 1:63 -- must be zero */ 330 int64_t mddt_usage; /* 30: bitmap permissions */ 331 } mddt_clusters[1]; /* variable length array */ 332 }; 333 #endif /* ASSEMBLER */ 334
Indexes created Tue Sep 30 20:09:53 GMT 2025