1 1.9 thorpej /* $NetBSD: tc_machdep.h,v 1.9 2025/03/09 01:06:42 thorpej Exp $ */ 2 1.1 cgd 3 1.1 cgd /* 4 1.1 cgd * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 1.1 cgd * All rights reserved. 6 1.1 cgd * 7 1.1 cgd * Author: Chris G. Demetriou 8 1.1 cgd * 9 1.1 cgd * Permission to use, copy, modify and distribute this software and 10 1.1 cgd * its documentation is hereby granted, provided that both the copyright 11 1.1 cgd * notice and this permission notice appear in all copies of the 12 1.1 cgd * software, derivative works or modified versions, and any portions 13 1.1 cgd * thereof, and that both notices appear in supporting documentation. 14 1.1 cgd * 15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 1.1 cgd * 19 1.1 cgd * Carnegie Mellon requests users of this software to return to 20 1.1 cgd * 21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 1.1 cgd * School of Computer Science 23 1.1 cgd * Carnegie Mellon University 24 1.1 cgd * Pittsburgh PA 15213-3890 25 1.1 cgd * 26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the 27 1.1 cgd * rights to redistribute these changes. 28 1.1 cgd */ 29 1.1 cgd 30 1.1 cgd /* 31 1.7 flxd * Machine-specific definitions for TURBOchannel support. 32 1.1 cgd * 33 1.1 cgd * This file must typedef the following types: 34 1.1 cgd * 35 1.7 flxd * tc_addr_t TURBOchannel bus address 36 1.7 flxd * tc_offset_t TURBOchannel bus address difference (offset) 37 1.1 cgd * 38 1.1 cgd * This file must prototype or define the following functions 39 1.1 cgd * or macros (one or more of which may be no-ops): 40 1.1 cgd * 41 1.1 cgd * tc_mb() read/write memory barrier (any CPU<->memory 42 1.1 cgd * reads/writes before must complete before any 43 1.1 cgd * CPU<->memory reads/writes after). 44 1.1 cgd * tc_wmb() write memory barrier (any CPU<->memory writes 45 1.1 cgd * before must complete before any CPU<->memory 46 1.1 cgd * writes after). 47 1.1 cgd * tc_syncbus() sync TC bus; make sure CPU writes are 48 1.7 flxd * propagated across the TURBOchannel bus. 49 1.1 cgd * tc_badaddr() return non-zero if the given address is invalid. 50 1.1 cgd * TC_DENSE_TO_SPARSE() 51 1.1 cgd * convert the given physical address in 52 1.7 flxd * TURBOchannel dense space to the corresponding 53 1.7 flxd * address in TURBOchannel sparse space. 54 1.1 cgd * TC_PHYS_TO_UNCACHED() 55 1.1 cgd * convert the given system memory physical address 56 1.1 cgd * to the physical address of the corresponding 57 1.1 cgd * region that is not cached. 58 1.1 cgd */ 59 1.1 cgd 60 1.5 matt typedef uint64_t tc_addr_t; 61 1.1 cgd typedef int32_t tc_offset_t; 62 1.1 cgd 63 1.3 cgd #define tc_mb() alpha_mb() 64 1.3 cgd #define tc_wmb() alpha_wmb() 65 1.1 cgd 66 1.1 cgd /* 67 1.1 cgd * A junk address to read from, to make sure writes are complete. See 68 1.1 cgd * System Programmer's Manual, section 9.3 (p. 9-4), and sacrifice a 69 1.1 cgd * chicken. 70 1.1 cgd */ 71 1.1 cgd #define tc_syncbus() \ 72 1.1 cgd do { \ 73 1.5 matt volatile uint32_t no_optimize; \ 74 1.8 thorpej /* \ 75 1.8 thorpej * WMB does not order reads with respect to writes, so a \ 76 1.8 thorpej * MB is required here. \ 77 1.8 thorpej */ \ 78 1.8 thorpej alpha_mb(); \ 79 1.1 cgd no_optimize = \ 80 1.5 matt *(volatile uint32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \ 81 1.6 christos __USE(no_optimize); \ 82 1.6 christos } while (/*CONSTCOND*/0) 83 1.1 cgd 84 1.1 cgd #define tc_badaddr(tcaddr) \ 85 1.5 matt badaddr((void *)(tcaddr), sizeof (uint32_t)) 86 1.1 cgd 87 1.1 cgd #define TC_SPACE_IND 0xffffffffe0000003 88 1.1 cgd #define TC_SPACE_DENSE 0x0000000000000000 89 1.1 cgd #define TC_SPACE_DENSE_OFFSET 0x0000000007fffffc 90 1.1 cgd #define TC_SPACE_SPARSE 0x0000000010000000 91 1.1 cgd #define TC_SPACE_SPARSE_OFFSET 0x000000000ffffff8 92 1.1 cgd 93 1.1 cgd #define TC_DENSE_TO_SPARSE(addr) \ 94 1.1 cgd (((addr) & TC_SPACE_IND) | TC_SPACE_SPARSE | \ 95 1.1 cgd (((addr) & TC_SPACE_DENSE_OFFSET) << 1)) 96 1.1 cgd 97 1.1 cgd #define TC_PHYS_TO_UNCACHED(addr) \ 98 1.1 cgd (addr) 99 1.3 cgd 100 1.3 cgd /* 101 1.3 cgd * These functions are private, and may not be called by 102 1.3 cgd * machine-independent code. 103 1.3 cgd */ 104 1.9 thorpej void tc_find_bootdev(device_t, void *); 105 1.9 thorpej bus_space_tag_t tc_bus_mem_init(void *memv); 106 1.9 thorpej void tc_dma_init(void); 107 1.3 cgd 108 1.3 cgd /* 109 1.3 cgd * Address of scatter/gather SRAM on the 3000/500-series. 110 1.3 cgd * 111 1.3 cgd * There is room for 32K entries, yielding 256M of sgva space. 112 1.3 cgd * The page table is readable in both dense and sparse space. 113 1.3 cgd * The page table is writable only in sparse space. 114 1.3 cgd * 115 1.3 cgd * In sparse space, the 32-bit PTEs are followed by 32-bits 116 1.3 cgd * of pad. 117 1.3 cgd */ 118 1.3 cgd #define TC_SGSRAM_DENSE 0x0000001c2800000UL 119 1.3 cgd #define TC_SGSRAM_SPARSE 0x0000001d5000000UL 120