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tc_machdep.h revision 1.3
      1  1.3  cgd /* $NetBSD: tc_machdep.h,v 1.3 1999/03/19 03:12:31 cgd Exp $ */
      2  1.1  cgd 
      3  1.1  cgd /*
      4  1.1  cgd  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
      5  1.1  cgd  * All rights reserved.
      6  1.1  cgd  *
      7  1.1  cgd  * Author: Chris G. Demetriou
      8  1.1  cgd  *
      9  1.1  cgd  * Permission to use, copy, modify and distribute this software and
     10  1.1  cgd  * its documentation is hereby granted, provided that both the copyright
     11  1.1  cgd  * notice and this permission notice appear in all copies of the
     12  1.1  cgd  * software, derivative works or modified versions, and any portions
     13  1.1  cgd  * thereof, and that both notices appear in supporting documentation.
     14  1.1  cgd  *
     15  1.1  cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  1.1  cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  1.1  cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  1.1  cgd  *
     19  1.1  cgd  * Carnegie Mellon requests users of this software to return to
     20  1.1  cgd  *
     21  1.1  cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  1.1  cgd  *  School of Computer Science
     23  1.1  cgd  *  Carnegie Mellon University
     24  1.1  cgd  *  Pittsburgh PA 15213-3890
     25  1.1  cgd  *
     26  1.1  cgd  * any improvements or extensions that they make and grant Carnegie the
     27  1.1  cgd  * rights to redistribute these changes.
     28  1.1  cgd  */
     29  1.1  cgd 
     30  1.1  cgd /*
     31  1.1  cgd  * Machine-specific definitions for TurboChannel support.
     32  1.1  cgd  *
     33  1.1  cgd  * This file must typedef the following types:
     34  1.1  cgd  *
     35  1.1  cgd  *	tc_addr_t	TurboChannel bus address
     36  1.1  cgd  *	tc_offset_t	TurboChannel bus address difference (offset)
     37  1.1  cgd  *
     38  1.1  cgd  * This file must prototype or define the following functions
     39  1.1  cgd  * or macros (one or more of which may be no-ops):
     40  1.1  cgd  *
     41  1.1  cgd  *	tc_mb()		read/write memory barrier (any CPU<->memory
     42  1.1  cgd  *			reads/writes before must complete before any
     43  1.1  cgd  *			CPU<->memory reads/writes after).
     44  1.1  cgd  *	tc_wmb()	write memory barrier (any CPU<->memory writes
     45  1.1  cgd  *			before must complete before any CPU<->memory
     46  1.1  cgd  *			writes after).
     47  1.1  cgd  *	tc_syncbus()	sync TC bus; make sure CPU writes are
     48  1.1  cgd  *			propagated across the TurboChannel bus.
     49  1.1  cgd  *	tc_badaddr()	return non-zero if the given address is invalid.
     50  1.1  cgd  *	TC_DENSE_TO_SPARSE()
     51  1.1  cgd  *			convert the given physical address in
     52  1.1  cgd  *			TurboChannel dense space to the corresponding
     53  1.1  cgd  *			address in TurboChannel sparse space.
     54  1.1  cgd  *	TC_PHYS_TO_UNCACHED()
     55  1.1  cgd  *			convert the given system memory physical address
     56  1.1  cgd  *			to the physical address of the corresponding
     57  1.1  cgd  *			region that is not cached.
     58  1.1  cgd  */
     59  1.1  cgd 
     60  1.1  cgd typedef u_int64_t	tc_addr_t;
     61  1.1  cgd typedef int32_t		tc_offset_t;
     62  1.1  cgd 
     63  1.3  cgd #define	tc_mb()		alpha_mb()
     64  1.3  cgd #define	tc_wmb()	alpha_wmb()
     65  1.1  cgd 
     66  1.1  cgd /*
     67  1.1  cgd  * A junk address to read from, to make sure writes are complete.  See
     68  1.1  cgd  * System Programmer's Manual, section 9.3 (p. 9-4), and sacrifice a
     69  1.1  cgd  * chicken.
     70  1.1  cgd  */
     71  1.1  cgd #define	tc_syncbus()							\
     72  1.1  cgd     do {								\
     73  1.1  cgd 	volatile u_int32_t no_optimize;					\
     74  1.1  cgd 	no_optimize =	 						\
     75  1.3  cgd 	    *(volatile u_int32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \
     76  1.1  cgd     } while (0)
     77  1.1  cgd 
     78  1.1  cgd #define	tc_badaddr(tcaddr)						\
     79  1.1  cgd     badaddr((void *)(tcaddr), sizeof (u_int32_t))
     80  1.1  cgd 
     81  1.1  cgd #define	TC_SPACE_IND		0xffffffffe0000003
     82  1.1  cgd #define	TC_SPACE_DENSE		0x0000000000000000
     83  1.1  cgd #define TC_SPACE_DENSE_OFFSET	0x0000000007fffffc
     84  1.1  cgd #define	TC_SPACE_SPARSE		0x0000000010000000
     85  1.1  cgd #define	TC_SPACE_SPARSE_OFFSET	0x000000000ffffff8
     86  1.1  cgd 
     87  1.1  cgd #define	TC_DENSE_TO_SPARSE(addr)					\
     88  1.1  cgd     (((addr) & TC_SPACE_IND) | TC_SPACE_SPARSE |			\
     89  1.1  cgd 	(((addr) & TC_SPACE_DENSE_OFFSET) << 1))
     90  1.1  cgd 
     91  1.1  cgd #define	TC_PHYS_TO_UNCACHED(addr)					\
     92  1.1  cgd     (addr)
     93  1.3  cgd 
     94  1.3  cgd /*
     95  1.3  cgd  * These functions are private, and may not be called by
     96  1.3  cgd  * machine-independent code.
     97  1.3  cgd  */
     98  1.3  cgd bus_space_tag_t tc_bus_mem_init __P((void *memv));
     99  1.3  cgd void tc_dma_init __P((void));
    100  1.3  cgd 
    101  1.3  cgd /*
    102  1.3  cgd  * Address of scatter/gather SRAM on the 3000/500-series.
    103  1.3  cgd  *
    104  1.3  cgd  * There is room for 32K entries, yielding 256M of sgva space.
    105  1.3  cgd  * The page table is readable in both dense and sparse space.
    106  1.3  cgd  * The page table is writable only in sparse space.
    107  1.3  cgd  *
    108  1.3  cgd  * In sparse space, the 32-bit PTEs are followed by 32-bits
    109  1.3  cgd  * of pad.
    110  1.3  cgd  */
    111  1.3  cgd #define	TC_SGSRAM_DENSE		0x0000001c2800000UL
    112  1.3  cgd #define	TC_SGSRAM_SPARSE	0x0000001d5000000UL
    113