jensenio_intr.c revision 1.10
1 /* $NetBSD: jensenio_intr.c,v 1.10 2012/02/06 02:14:14 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: jensenio_intr.c,v 1.10 2012/02/06 02:14:14 matt Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/syslog.h> 44 45 #include <machine/autoconf.h> 46 47 #include <dev/eisa/eisavar.h> 48 49 #include <dev/isa/isareg.h> 50 #include <dev/isa/isavar.h> 51 52 #include <alpha/jensenio/jenseniovar.h> 53 54 static bus_space_tag_t pic_iot; 55 static bus_space_handle_t pic_ioh[2]; 56 static bus_space_handle_t pic_elcr_ioh; 57 58 int jensenio_eisa_intr_map(void *, u_int, eisa_intr_handle_t *); 59 const char *jensenio_eisa_intr_string(void *, int); 60 const struct evcnt *jensenio_eisa_intr_evcnt(void *, int); 61 void *jensenio_eisa_intr_establish(void *, int, int, int, 62 int (*)(void *), void *); 63 void jensenio_eisa_intr_disestablish(void *, void *); 64 int jensenio_eisa_intr_alloc(void *, int, int, int *); 65 66 #define JENSEN_MAX_IRQ 16 67 68 struct alpha_shared_intr *jensenio_eisa_intr; 69 70 void jensenio_iointr(void *, u_long); 71 72 void jensenio_enable_intr(int, int); 73 void jensenio_setlevel(int, int); 74 void jensenio_pic_init(void); 75 76 const int jensenio_intr_deftype[JENSEN_MAX_IRQ] = { 77 IST_EDGE, /* 0: interval timer 0 output */ 78 IST_EDGE, /* 1: line printer */ 79 IST_UNUSABLE, /* 2: (cascade) */ 80 IST_NONE, /* 3: EISA pin B25 */ 81 IST_NONE, /* 4: EISA pin B24 */ 82 IST_NONE, /* 5: EISA pin B23 */ 83 IST_NONE, /* 6: EISA pin B22 (floppy) */ 84 IST_NONE, /* 7: EISA pin B21 */ 85 IST_EDGE, /* 8: RTC */ 86 IST_NONE, /* 9: EISA pin B04 */ 87 IST_NONE, /* 10: EISA pin D03 */ 88 IST_NONE, /* 11: EISA pin D04 */ 89 IST_NONE, /* 12: EISA pin D05 */ 90 IST_UNUSABLE, /* 13: not connected */ 91 IST_NONE, /* 14: EISA pin D07 (SCSI) */ 92 IST_NONE, /* 15: EISA pin D06 */ 93 }; 94 95 static inline void 96 jensenio_specific_eoi(int irq) 97 { 98 99 if (irq > 7) 100 bus_space_write_1(pic_iot, pic_ioh[1], 101 0, 0x20 | (irq & 0x07)); 102 bus_space_write_1(pic_iot, pic_ioh[0], 103 0, 0x20 | (irq > 7 ? 2 : irq)); 104 } 105 106 void 107 jensenio_intr_init(struct jensenio_config *jcp) 108 { 109 eisa_chipset_tag_t ec = &jcp->jc_ec; 110 isa_chipset_tag_t ic = &jcp->jc_ic; 111 char *cp; 112 int i; 113 114 pic_iot = &jcp->jc_eisa_iot; 115 116 jensenio_pic_init(); 117 118 jensenio_eisa_intr = alpha_shared_intr_alloc(JENSEN_MAX_IRQ, 16); 119 for (i = 0; i < JENSEN_MAX_IRQ; i++) { 120 alpha_shared_intr_set_dfltsharetype(jensenio_eisa_intr, 121 i, jensenio_intr_deftype[i]); 122 /* Don't bother with stray interrupts. */ 123 alpha_shared_intr_set_maxstrays(jensenio_eisa_intr, 124 i, 0); 125 126 cp = alpha_shared_intr_string(jensenio_eisa_intr, i); 127 sprintf(cp, "irq %d", i); 128 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 129 jensenio_eisa_intr, i), EVCNT_TYPE_INTR, 130 NULL, "eisa", cp); 131 } 132 133 /* 134 * The cascasde interrupt must be edge triggered and always enabled. 135 */ 136 jensenio_setlevel(2, 0); 137 jensenio_enable_intr(2, 1); 138 139 /* 140 * Initialize the EISA chipset. 141 */ 142 ec->ec_v = jcp; 143 ec->ec_intr_map = jensenio_eisa_intr_map; 144 ec->ec_intr_string = jensenio_eisa_intr_string; 145 ec->ec_intr_evcnt = jensenio_eisa_intr_evcnt; 146 ec->ec_intr_establish = jensenio_eisa_intr_establish; 147 ec->ec_intr_disestablish = jensenio_eisa_intr_disestablish; 148 149 /* 150 * Initialize the ISA chipset. 151 */ 152 ic->ic_v = jcp; 153 ic->ic_intr_establish = jensenio_eisa_intr_establish; 154 ic->ic_intr_disestablish = jensenio_eisa_intr_disestablish; 155 ic->ic_intr_alloc = jensenio_eisa_intr_alloc; 156 ic->ic_intr_evcnt = jensenio_eisa_intr_evcnt; 157 } 158 159 int 160 jensenio_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 161 { 162 163 if (eirq >= JENSEN_MAX_IRQ) { 164 printf("jensenio_eisa_intr_map: bogus IRQ %d", eirq); 165 *ihp = -1; 166 return (1); 167 } 168 169 if (jensenio_intr_deftype[eirq] == IST_UNUSABLE) { 170 printf("jensenio_eisa_intr_map: unusable irq %d\n", 171 eirq); 172 *ihp = -1; 173 return (1); 174 } 175 176 *ihp = eirq; 177 return (0); 178 } 179 180 const char * 181 jensenio_eisa_intr_string(void *v, int eirq) 182 { 183 static char irqstr[64]; 184 185 if (eirq >= JENSEN_MAX_IRQ) 186 panic("jensenio_eisa_intr_string: bogus IRQ %d", eirq); 187 188 sprintf(irqstr, "eisa irq %d", eirq); 189 190 return (irqstr); 191 } 192 193 const struct evcnt * 194 jensenio_eisa_intr_evcnt(void *v, int eirq) 195 { 196 197 if (eirq >= JENSEN_MAX_IRQ) 198 panic("jensenio_eisa_intr_evcnt: bogus IRQ %d", eirq); 199 200 return (alpha_shared_intr_evcnt(jensenio_eisa_intr, eirq)); 201 } 202 203 void * 204 jensenio_eisa_intr_establish(void *v, int irq, int type, int level, 205 int (*fn)(void *), void *arg) 206 { 207 void *cookie; 208 209 if (irq >= JENSEN_MAX_IRQ || type == IST_NONE) 210 panic("jensenio_eisa_intr_establish: bogus irq or type"); 211 212 if (jensenio_intr_deftype[irq] == IST_UNUSABLE) { 213 printf("jensenio_eisa_intr_establish: IRQ %d not usable\n", 214 irq); 215 return (NULL); 216 } 217 218 cookie = alpha_shared_intr_establish(jensenio_eisa_intr, irq, 219 type, level, fn, arg, "eisa irq"); 220 221 if (cookie != NULL && 222 alpha_shared_intr_firstactive(jensenio_eisa_intr, irq)) { 223 scb_set(0x800 + SCB_IDXTOVEC(irq), jensenio_iointr, NULL, 224 level); 225 jensenio_setlevel(irq, 226 alpha_shared_intr_get_sharetype(jensenio_eisa_intr, 227 irq) == IST_LEVEL); 228 jensenio_enable_intr(irq, 1); 229 } 230 231 return (cookie); 232 } 233 234 void 235 jensenio_eisa_intr_disestablish(void *v, void *cookie) 236 { 237 struct alpha_shared_intrhand *ih = cookie; 238 int s, irq = ih->ih_num; 239 240 s = splhigh(); 241 242 /* Remove it from the link. */ 243 alpha_shared_intr_disestablish(jensenio_eisa_intr, cookie, 244 "eisa irq"); 245 246 if (alpha_shared_intr_isactive(jensenio_eisa_intr, irq) == 0) { 247 jensenio_enable_intr(irq, 0); 248 alpha_shared_intr_set_dfltsharetype(jensenio_eisa_intr, 249 irq, jensenio_intr_deftype[irq]); 250 scb_free(0x800 + SCB_IDXTOVEC(irq)); 251 } 252 253 splx(s); 254 } 255 256 int 257 jensenio_eisa_intr_alloc(void *v, int mask, int type, int *rqp) 258 { 259 260 /* XXX Not supported right now. */ 261 return (1); 262 } 263 264 void 265 jensenio_iointr(void *framep, u_long vec) 266 { 267 int irq; 268 269 irq = SCB_VECTOIDX(vec - 0x800); 270 271 if (!alpha_shared_intr_dispatch(jensenio_eisa_intr, irq)) 272 alpha_shared_intr_stray(jensenio_eisa_intr, irq, "eisa irq"); 273 274 jensenio_specific_eoi(irq); 275 } 276 277 void 278 jensenio_enable_intr(int irq, int onoff) 279 { 280 int pic; 281 uint8_t bit, mask; 282 283 pic = irq >> 3; 284 bit = 1 << (irq & 0x7); 285 286 mask = bus_space_read_1(pic_iot, pic_ioh[pic], 1); 287 if (onoff) 288 mask &= ~bit; 289 else 290 mask |= bit; 291 bus_space_write_1(pic_iot, pic_ioh[pic], 1, mask); 292 } 293 294 void 295 jensenio_setlevel(int irq, int level) 296 { 297 int elcr; 298 uint8_t bit, mask; 299 300 elcr = irq >> 3; 301 bit = 1 << (irq & 0x7); 302 303 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 304 if (level) 305 mask |= bit; 306 else 307 mask &= ~bit; 308 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 309 } 310 311 void 312 jensenio_pic_init(void) 313 { 314 static const int picaddr[2] = { IO_ICU1, IO_ICU2 }; 315 int pic; 316 317 /* 318 * Map the PICs and mask off the interrupts on them. 319 */ 320 for (pic = 0; pic < 2; pic++) { 321 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, &pic_ioh[pic])) 322 panic("jensenio_init_intr: unable to map PIC %d", pic); 323 bus_space_write_1(pic_iot, pic_ioh[pic], 1, 0xff); 324 } 325 326 /* 327 * Map the ELCR registers. 328 */ 329 if (bus_space_map(pic_iot, 0x4d0, 2, 0, &pic_elcr_ioh)) 330 panic("jensenio_init_intr: unable to map ELCR registers"); 331 } 332
Indexes created Tue Sep 30 06:09:59 GMT 2025