1 1.3 cgd /* $NetBSD: apecs_bus_io.c,v 1.3 1997/04/07 06:36:40 cgd Exp $ */ 2 1.1 cgd 3 1.1 cgd /* 4 1.1 cgd * Copyright (c) 1996 Carnegie-Mellon University. 5 1.1 cgd * All rights reserved. 6 1.1 cgd * 7 1.1 cgd * Author: Chris G. Demetriou 8 1.1 cgd * 9 1.1 cgd * Permission to use, copy, modify and distribute this software and 10 1.1 cgd * its documentation is hereby granted, provided that both the copyright 11 1.1 cgd * notice and this permission notice appear in all copies of the 12 1.1 cgd * software, derivative works or modified versions, and any portions 13 1.1 cgd * thereof, and that both notices appear in supporting documentation. 14 1.1 cgd * 15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 1.1 cgd * 19 1.1 cgd * Carnegie Mellon requests users of this software to return to 20 1.1 cgd * 21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 1.1 cgd * School of Computer Science 23 1.1 cgd * Carnegie Mellon University 24 1.1 cgd * Pittsburgh PA 15213-3890 25 1.1 cgd * 26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the 27 1.1 cgd * rights to redistribute these changes. 28 1.1 cgd */ 29 1.3 cgd 30 1.3 cgd #include <machine/options.h> /* Pull in config options headers */ 31 1.1 cgd 32 1.1 cgd #include <sys/param.h> 33 1.1 cgd #include <sys/systm.h> 34 1.1 cgd #include <sys/malloc.h> 35 1.1 cgd #include <sys/syslog.h> 36 1.1 cgd #include <sys/device.h> 37 1.1 cgd #include <vm/vm.h> 38 1.1 cgd 39 1.1 cgd #include <machine/bus.h> 40 1.1 cgd 41 1.1 cgd #include <alpha/pci/apecsreg.h> 42 1.1 cgd #include <alpha/pci/apecsvar.h> 43 1.1 cgd 44 1.1 cgd #define CHIP apecs 45 1.1 cgd 46 1.1 cgd #define CHIP_EX_MALLOC_SAFE(v) (((struct apecs_config *)(v))->ac_mallocsafe) 47 1.1 cgd #define CHIP_IO_EXTENT(v) (((struct apecs_config *)(v))->ac_io_ex) 48 1.1 cgd 49 1.1 cgd /* IO region 1 */ 50 1.1 cgd #define CHIP_IO_W1_BUS_START(v) 0x00000000UL 51 1.1 cgd #define CHIP_IO_W1_BUS_END(v) 0x0003ffffUL 52 1.1 cgd #define CHIP_IO_W1_SYS_START(v) APECS_PCI_SIO 53 1.1 cgd #define CHIP_IO_W1_SYS_END(v) (APECS_PCI_SIO + (0x00040000UL << 5) - 1) 54 1.1 cgd 55 1.1 cgd /* IO region 2 */ 56 1.1 cgd #define CHIP_IO_W2_BUS_START(v) \ 57 1.1 cgd ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \ 58 1.1 cgd 0x00040000UL) 59 1.1 cgd #define CHIP_IO_W2_BUS_END(v) \ 60 1.1 cgd ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \ 61 1.1 cgd 0x00ffffffUL) 62 1.1 cgd #define CHIP_IO_W2_SYS_START(v) (APECS_PCI_SIO + (0x00040000UL << 5)) 63 1.1 cgd #define CHIP_IO_W2_SYS_END(v) (APECS_PCI_SIO + (0x01000000UL << 5) - 1) 64 1.1 cgd 65 1.1 cgd #include "pcs_bus_io_common.c" 66